DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on February 17, 2026 has been entered.
Response to Amendment
This Office Action is in response to Applicant's amendments filed February 17, 2026. Claims 1 and 5 have been amended. No claims have been added. No claims have been canceled. Claims 7-12 stand withdrawn. Currently, claims 1-6, and 13 are pending.
Response to Arguments
Applicant’s arguments with respect to claim 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Claim 1 requires that the logic substrate (3) includes a second connection wire (28), which is another conductor wire directly connecting the first wire (11) and the second wire (12) to each other as shown in Fig. 9. Claim 2 further requires the first terminal (6) and the second terminal (7) are not electrically connected together in the second wire layer (28) as shown in Fig. 5. However, there is no figure that shows both the second connection wire and the first and second terminals not electrically connected in the second wire layer. Therefore, all the limitations of claim 2 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Claim 3 further requires the joint portion (5) further includes a third wire (41) connecting the first terminal (6) to the pixel substrate (2), and
a fourth wire (42) connecting the second terminal (7) to the pixel substrate (2) as shown in Fig. 7. However, there is no figure that shows both the second connection wire in the logic substrate and the third and fourth wire in the joint portion. Therefore, all the limitations of claim 3 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Further, claim 5 requires the logic circuit (8) further has a third terminal (6B) and a fourth terminal (7B) that are other nodes identical to each other as shown in Fig. 8. However, there is no figure that shown both the second connection wire and the third and fourth terminals in the logic substrate. Therefore, all the limitations of claim 5 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 2 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 2, the claim recites that limitation “the first terminal and the second terminal are not electrically connected to each other in the second wire layer, and
the first terminal and the second terminal are electrically connected to each other in only the first wire layer” in lines 5-8. Claim 1 provides antecedent basis for the first terminal and the second terminal and describes them as directly connected by wires and conductor in both the logic substrate and the pixel substrate. It is not clear how the terminals can be directly connected by wires and conductor in the logic substrate and not electrically connected at the same time.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, and 13 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Horikoshi (US 20220406834 A1).
Regarding claim 1, Figs. 1 and 20 of Horikoshi disclose a solid-state image pickup element (Fig. 1, semiconductor device 1, ¶ [0056]) comprising:
a pixel substrate (Fig. 1, first substrate 2, ¶ [0056]) having a pixel array (Fig. 20, pixel unit 103, ¶ [0103]) in which a unit pixel (Fig. 20, pixels 102, ¶ [0103]) including a photoelectric-conversion element (Fig. 20, “The pixel unit 103 is composed of an effective pixel region in which light is actually received, and a signal charge generated by photoelectric conversion”, ¶ [0105]) is disposed in rows and columns (Fig. 20, “The pixel unit 103 is composed of a plurality of pixels 102 that are regularly arranged in a 2D array form”, ¶ [0105]);
a logic substrate (Fig. 1, second substrate 3, ¶ [0056]) having a logic circuit (Fig. 1, “the second substrate 3, for example, a logic substrate in which circuits for processing electrical signals from photoelectric conversion units are integrated”, ¶ [0056]) that is associated with the pixel array, and that is stacked on the pixel substrate (2); and
a joint portion (Fig. 1, substrate connection 24, ¶ [0071]) joined in such a manner, that uppermost-layer wires of the pixel substrate (2) and the logic substrate (3) face each other, to electrically connect the pixel substrate (2) and the logic substrate (3) to each other,
wherein the logic circuit (8) has a first terminal (see Annotation 1, Fig. 1 of Horikoshi, T1) and a second terminal (see Annotation 1, Fig. 1 of Horikoshi, T2) that include nodes identical to each other, the node of the first terminal (T1) and the node of the second terminal (T2) are nodes that are used for a circuit operation on only the logic substrate (3),
the joint portion (24) includes a first wire (see Annotation 1, Fig. 1 of Horikoshi, W1) connecting the first terminal (T1) to the pixel substrate (2), and
a second wire (see Annotation 1, Fig. 1 of Horikoshi, W2) connecting the second terminal (T2) to the pixel substrate (2),
the pixel substrate (2) includes a first connection wire (see Annotation 1, Fig. 1 of Horikoshi, CW1), which is a conductor wire directly connecting the first wire (W1) and the second wire (W2) to each other, and
the logic substrate (3) includes a second connection wire (see Annotation 1, Fig. 1 of Horikoshi, CW2), which is another conductor wire directly connecting the first wire (W1) and the second wire (W2) to each other.
PNG
media_image1.png
660
765
media_image1.png
Greyscale
Annotation 1, Fig. 1 of Horikoshi
Regarding claim 2, Figs. 1 and 20 of Horikoshi disclose the solid-state image pickup element according to claim 1 as applied above, and Fig. 1 of Horikoshi further discloses wherein the pixel substrate (2) further includes a first wire layer (Fig. 1, fourth wiring layer 5d, ¶ [0066]),
the logic substrate (3) includes a second wire layer (Fig. 1, fifth wiring layer 15e, ¶ [0063]),
the first terminal (T1) and the second terminal (T2) are not electrically connected to each other in the second wire layer (15e), and
the first terminal (T1) and the second terminal (T2) are electrically connected to each other in only the first wire layer (5d).
regarding claim 13, Figs. 1 and 20 of Horikoshi disclose the solid-state image pickup element according to claim 1 as applied above, and Fig. 27 of Horikoshi further discloses an electronic device (Fig. 27, imaging device 201, ¶ [0189]) comprising the solid-state image pickup element (1) according to claim 1 (“Fig. 27 is a diagram showing an example of a schematic configuration of an imaging device as an electronic device to which the technology according to the present disclosure (the present technology) can be applied”, ¶ [0188]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3-5 are rejected under 35 U.S.C. 103 as being unpatentable over Horikoshi (US 20220406834 A1) in view of Nakamura et al. (US 20220359600 A1) herein after “Nakamura”.
Regarding claim 3, Figs. 1 and 20 of Horikoshi disclose the solid-state image pickup element according to claim 1 as applied above, and Figs. 24-25 of Horikoshi further disclose wherein the logic circuit (8) includes a pixel driving circuit (Figs. 24-25, a circuit configuration of the solid-state imaging device 101, ¶ [0163]) for driving the unit pixel (102), and
a signal processing circuit (Fig. 24, “the plurality of MOS transistors formed in the second substrate 181 are a second transfer transistor Tr2, a reset transistor Tr3, an amplifying transistor Tr4, and a select transistor Tr5”, ¶ [0150]) for processing a signal output from the pixel array (103).
Horikoshi fails to disclose the joint portion further includes:
a third wire connecting the first terminal to the pixel substrate, and
a fourth wire connecting the second terminal to the pixel substrate.
In the similar field of endeavor of solid state imaging apparatuses, Fig. 6 of Nakamura discloses the joint portion (Fig. 6, “The capacitor unit 22 and the signal processing unit 13 are electrically connected via junction contacts 24a and 24b”, ¶ [0033]) further includes:
a third wire (Fig. 6 shows a third wire connecting to 24a in 2) connecting the first terminal (Fig. 6, junction contacts 24a, ¶ [0033]) to the pixel substrate (Fig. 6, second semiconductor component 2, ¶ [0032]), and
a fourth wire (Fig. 6 shows a fourth wire connecting to 24b in 2) connecting the second terminal (Fig. 6, junction contacts 24b, ¶ [0033]) to the pixel substrate (2).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the solid-state image pickup element of Horikoshi with the additional junction contacts as disclosed by Nakamura, to reduce impedance and suppress voltage variation (see Nakamura, ¶ [0054]).
Regarding claim 4, Figs. 1 and 20 of Horikoshi disclose the solid-state image pickup element according to claim 1 as applied above, but Horikoshi fails to disclose wherein the first terminal is one of a power source terminal and a ground terminal, and the second terminal is another one of the power source terminal and the ground terminal.
In the similar field of endeavor of solid state imaging apparatuses, Fig. 1 of Nakamura discloses wherein the first terminal (24a) is one of a power source terminal and a ground terminal (“the power source wiring VDD is connected to the junction contact 24a”, ¶ [0047]), and
the second terminal (24b) is another one of the power source terminal and the ground terminal (“the ground wiring GND is connected to the junction contact 24b”, ¶ [0047]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the solid-state image pickup element of Horikoshi with the terminals as disclosed by Nakamura, to reduce impedance and suppress voltage variation (see Nakamura, ¶ [0054]).
Regarding claim 5, Figs. 1 and 20 of Horikoshi disclose the solid-state image pickup element according to claim 1 as applied above, and Horikoshi discloses a connection wire (CW1), which is a conductor wire directly connecting the wires (W1, W2).
Horikoshi fails to disclose wherein the logic circuit further has a third terminal and a fourth terminal that include other nodes identical to each other,
the joint portion further includes:
a fifth wire connecting the third terminal to the pixel substrate, and
a sixth wire connecting the fourth terminal to the pixel substrate, and
the pixel substrate further includes a third connection wire.
In the similar field of endeavor of solid state imaging apparatuses, Fig. 6 of Nakamura discloses wherein the logic circuit (11-14) further has a third terminal (24a) and a fourth terminal (24b) that include other nodes identical to each other,
the joint portion further includes:
a fifth wire (Fig. 6 shows a fifth wire connecting to 24a in 2) connecting the third terminal (24a) to the pixel substrate (2), and
a sixth wire (Fig. 6 shows a sixth wire connecting to 24b in 2) connecting the fourth terminal (24b) to the pixel substrate (2), and
the pixel substrate (2) further includes a second connection wire (N1, N2).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the solid-state image pickup element of Horikoshi with the wires as disclosed by Nakamura, to reduce impedance and suppress voltage variation (see Nakamura, ¶ [0054]).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Horikoshi (US 20220406834 A1) in view of Suzuki et al. (US 20200185433 A1) herein after “Suzuki”.
Regarding claim 6, Fig. 1 of Horikoshi disclose the solid-state image pickup element according to claim 2 as applied above, and Fig. 1 of Horikoshi further discloses wherein the first wire layer (5d) is a multi-layer wire layer (Fig. 1 shows wiring layers 5a-5d in the pixel substrate),
the first connection wire (CW1) is formed in one or more layers of the multi-layer wire layer (shown in Fig. 1).
Horikoshi fails to disclose the first connection wire has a structure comprising a plurality of first connection wires, including the first connection wire, connected to each other while crisscrossing in a lattice manner.
In the similar field of endeavor of solid-state image pickup elements, Figs. 5-6 of Suzuki discloses the first connection wire has a structure comprising a plurality of first connection wires (Fig. 6, dummy wires 35a and 35b, ¶ [0070]), including the first connection wire, connected to each other while crisscrossing in a lattice manner (Fig. 5, “the dummy wires D are disposed in a lattice pattern”, ¶ [0089]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the first connection wire of Horikoshi with the lattice pattern as disclosed by Suzuki, to suppress capacitance fluctuations (see Suzuki, ¶ [0092-0093]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CORALIE NETTLES whose telephone number is (571)270-5374. The examiner can normally be reached Mon-Fri. 11:30am-7pm ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Yara J Green can be reached at (571) 270-3035. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/C.A.N./ Examiner, Art Unit 2893
/YARA B GREEN/ Supervisor Patent Examiner, Art Unit 2893
Prosecution Insights