Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on January 5, 2026 has been entered.
Response to Amendment
Amendment to claims 1 and 8 submitted on January 5, 2026 are acknowledged and have since been entered.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
Claims 5-6 and 11-12 are rejected under 35 U.S.C. 112(a) as failing to comply with the enablement requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to enable one skilled in the art to which it pertains, or with which it is most nearly connected, to make and/or use the invention:
Claims 5 and 11 each cite “wherein the spacer is in the first trench” as drawn to the embodiments of Figs. 9 and 10 in the instant application. However, these embodiments teach away from the previously cited limitation “a contact etch stop layer (CESL) on and directly contacting a top surface of the STI between the gate structure and the first trench and in the first trench” as drawn to the embodiments of Figs. 4-7. As such, the claimed subject matter does not describe in the specification a way as to enable one skilled in the art to make or use the described invention.
Claims 6 and 12 further cite “a bottom surface of the spacer is lower than a top surface of the STI”, which is drawn to the embodiments of Figs. 9-10 and teaches away from the embodiments of Figs. 4-7. Additionally, “a top surface of the STI” lacks clarity as whether this surface is intended to be a distinct surface from the previously cited top surface of the STI between the gate structure and the first trench.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 5 and 11 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
Claims 5 and 11 each cite “wherein the spacer is in the first trench” as drawn to the embodiments of Figs. 9 and 10 in the instant application. However, these embodiments teach away from the previously cited limitation “a contact etch stop layer (CESL) on and directly contacting a top surface of the STI between the gate structure and the first trench and in the first trench” as drawn to the embodiments of Figs. 4-7. It is unclear how a contact etch stop layer is intended to be interpreted as “on and directly contacting a top surface of the STI” while simultaneously having “the spacer adjacent to the gate structure and in the first trench.”
For examination purposes, claims 5 and 11 are interpreted to read “the spacer adjacent the gate structure” as shown in the embodiments of Figs. 4-7.
Claims 6 and 12 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
Claims 6 and 12 further cite “a bottom surface of the spacer is lower than a top surface of the STI”, which is drawn to the embodiments of Figs. 9-10 and teaches away from the embodiments of Figs. 4-7. Additionally, “a top surface of the STI” lacks clarity as whether this surface is intended to be a distinct surface from the previously cited top surface of the STI between the gate structure and the first trench.
For examination purposes, claims 6 and 12 are interpreted to read “a bottom surface of the spacer is adjacent to a top surface of the STI” as is suggested in the embodiments of Figs. 4-7.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-13 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee (US 10103265 B1).
Regarding Claim 1, Lee teaches a method for fabricating a semiconductor device (100), comprising:
forming a shallow trench isolation (STI) (14, shown Fig. 1) in a substrate (10);
forming a gate structure (22) on the STI and the substrate (shown Fig. 2), wherein a first end and a second end of the gate structure are directly on the STI (shown Fig. 2, wherein a top-down view shows a first end and a second end of the gate structure being directly on the STI);
forming a first trench (36) in the STI adjacent to the gate structure (shown Fig. 4); and
forming a contact etch stop layer (CESL) (41, shown Fig. 6) on and directly contacting a top surface (14a) of the STI between the gate structure and the first trench (shown Fig. 6, wherein a top surface 14a meets and directly contacts the CESL at a point between the gate and the trench).
Regarding Claim 2, Lee teaches the method of claim 1, further comprising:
forming a spacer (22b) around the gate structure;
forming a patterned mask (32) on the STI and the gate structure (shown Fig. 4);
using the patterned mask to form the first trench (shown Fig. 4);
removing the patterned mask (shown Fig. 5);
forming the CESL on the gate structure and in the first trench (shown Fig. 6);
forming an interlayer dielectric (ILD) layer (42) on the CESL (shown Fig. 6);
planarizing the ILD layer (shown Fig. 7); and
performing a replacement metal gate (RMG) process (shown Fig. 7, replacing structures 22 to 220) to transform the gate structure into a metal gate (220).
Regarding Claim 3, Lee teaches the method of claim 2, wherein the patterned mask comprises an opening (34) exposing the STI (shown Fig. 4), the method comprising:
performing an etching process to remove the STI for forming the first trench (36) adjacent to one side of the gate structure and a second trench (36, other side of active region 12) adjacent to another side of the gate structure (shown Fig. 4);
removing the patterned mask (shown Fig. 5); and
forming the CESL on the gate structure and in the first trench and the second trench (shown Fig. 6).
Regarding Claim 4, Lee teaches the method of claim 1, further comprising:
forming a patterned mask (32) on the STI and the gate structure (shown Fig. 4);
using the patterned mask to form the first trench (forming trench 36 using the patterned mask);
removing the patterned mask (shown Fig. 5);
forming a spacer (22b) around the gate structure (shown Fig. 5);
forming the CESL on the gate structure and the spacer (shown Fig. 6);
forming an interlayer dielectric (ILD) layer (42) on the CESL (shown Fig. 6);
planarizing the ILD layer (shown Fig. 7); and
performing a replacement metal gate (RMG) process (shown Fig. 7) to transform the gate structure into a metal gate (220).
Regarding Claim 5, Lee teaches the method of claim 4, further comprising forming the spacer adjacent to the gate structure (shown Fig. 6).
Regarding Claim 6, Lee teaches the method of claim 4, wherein a bottom surface of the spacer is adjacent to a top surface of the STI (shown Fig. 6).
Regarding Claim 7, Lee teaches the method of claim 1, wherein a depth of the first trench is between 20-200 nm (see Col. 5, Ln. 23-24 and Fig. 4 which gives a range between 80 nm and 120 nm).
Regarding Claim 8, Lee teaches a semiconductor device (100, see fIg. 6), comprising:
a shallow trench isolation (STI) (14) in a substrate (10);
a gate structure (22) on the STI and the substrate, wherein a first end and a second end of the gate structure are directly on the STI (see also Fig. 2, which gives a top-down view showing a first end and a second end directly on the STI);
a first trench (36) in the STI adjacent to one side of the gate structure (shown Fig. 4); and
a contact etch stop layer (CESL) (41, shown Fig. 6) on and directly contacting a top surface (14a) of the STI between the gate structure and the first trench (shown Fig. 6, wherein a top surface 14a meets and directly contacts the CESL at a point between the gate and the trench).
Regarding Claim 9, Lee teaches the semiconductor device of claim 8, further comprising:
a spacer (22b) around the gate structure;
a second trench (36, shown Fig. 4) in the STI adjacent to another side of the gate structure (interpreted as the trench on the opposite side of the active region 12);
the CESL on the spacer and in the first trench and the second trench (shown Fig. 6); and
an interlayer dielectric (ILD) layer (42) on the CESL (shown Fig. 6).
Regarding Claim 10, Lee teaches the semiconductor device of claim 8, further comprising:
a spacer (22b) adjacent to the gate structure and the STI under the gate structure (shown Fig. 4);
a second trench (36, shown Fig. 4) in the STI adjacent to another side of the gate structure (interpreted as the trench on the opposite side of the active region 12);
the CESL on the spacer and in the first trench and the second trench (shown Fig. 6); and
an interlayer dielectric (ILD) layer (42) on the CESL (shown Fig. 6).
Regarding Claim 11, Lee teaches the semiconductor device of claim 10 further comprising forming the spacer adjacent to the gate structure (shown Fig. 6).
Regarding Claim 12, Lee teaches the semiconductor device of claim 10 wherein a bottom surface of the spacer is adjacent to a top surface of the STI (shown Fig. 6).
Regarding Claim 13, Lee teaches the semiconductor device of claim 8, wherein a depth of the first trench is between 20-200 nm (see Col. 5, Ln. 23-24 and Fig. 4 which gives a range between 80 nm and 120 nm).
Response to Arguments
Applicant’s arguments with respect to claim(s) 1 and 8 have been considered but are not persuasive. Applicant argues that Lee fails to teach the CESL being on and directly contacting a top surface of the STI between the gate structure and the first trench and in the first trench. Examiner respectfully disagrees, and notes that a top surface of the STI (14a) is shown directly contacting a portion of the CESL (41) in Fig. 6 wherein the two features are shown intersecting at a top of a sidewall of the trench and the CESL further extends into the trench.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Liang (US 20080303102 A1) teaches an isolation trench having localized stressors, interpreted as a CESL layer (810, shown Fig. 8) wherein the CESL layer extends into a trench within an isolation structure (210) and further is on and in direct contact with an uppermost surface of the isolation structure between a gate structure (414) and the trench (shown Fig. 8).
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/C.P.B./Examiner, Art Unit 2893
/Britt Hanley/Supervisory Patent Examiner, Art Unit 2893