DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Applicant’s arguments and amendments filed on August 14, 2025 have been entered and considered.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 9-11 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Yoo et al. (US 6168984 B1).
Regarding claim 9, Yoo et al. (region 99) teaches:
A semiconductor device, comprising:
a substrate [1/70, Col. 4, Lines 51-62, Fig. 1-10] having an impurity region [15, Col. 7, Lines 6-14, Fig. 7-10] positioned in the substrate [1/70, Fig. 1-10];
a first gate structure [14 (left) in region 99, Col. 6, Lines 65-67 to Col. 7, Lines 1-23; Col. 7, Lines 51-56, Fig. 6-10] positioned on the substrate [1/70, Fig. 1-10];
a second gate structure [14 (right) in region 99, Col. 6, Lines 65-67 to Col. 7, Lines 1-23; Col. 7, Lines 51-56, Fig. 6-10] positioned on the substrate [1/70, Fig. 1-10] and next to the first gate structure [14 (left), Fig. 1-10];
a lower portion positioned between the first gate structure [14 (left), Fig. 1-10] and the second gate structure [14 (right), Fig. 1-10];
an upper portion [Fig. 10] positioned on the lower portion [Fig. 10]; and
a plurality of first spacers [16, Col. 7, Lines 21-23, Fig. 7-10] positioned between lower portion and the first gate structure [14 (left), Fig. 7-10] and between the lower portion and the second gate structure [14 (right), Fig. 7-10];
wherein the lower portion and the upper portion configure a contact structure [25/26, Col. 8, Lines 16-30, Fig. 10]; wherein a width of the upper portion is greater than a width of the lower portion [Col. 7, Lines 56-59, Fig. 10];
wherein the upper portion is positioned above the first spacers [16, Fig. 10], the first gate structure [14 (left), Fig. 10], and the second gate structure [14 (right), Fig. 10].
Yoo et al. teaches in the same embodiment but a different gate structure in region 88:
wherein the first gate structure [gate structure in region 88] comprises:
a first gate insulating layer [3, Col. 5, Lines 22-26, Fig. 2-10] positioned on and in contact with the substrate [1/70, Col. 5, Lines 43-46, Fig. 2-10];
a first gate conductive layer [4, Col. 5, Lines 26-33, Fig. 2-10] positioned on and in contact with the first gate insulating layer [3, Fig. 2-10]; and
a first gate capping layer [8, Col. 6, Lines 21-39, Fig. 5-10] positioned on and in contact with the first gate conductive layer [4, Fig. 5-10];
wherein a height of each of the first spacers [6, Col. 6, Lines 5-6, Fig. 4-10] is equal to a height of the lower portion and is equal to a sum of heights of the first gate insulating layer [3, Fig. 2-10], the first gate conductive layer [4, Fig. 2-10], and the first gate capping layer [8, Fig. 5-10].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Yoo et al. (region 88) into the teachings of Yoo et al. (region 99) to include wherein the first gate structure comprises: a first gate insulating layer positioned on and in contact with the substrate; a first gate conductive layer positioned on and in contact with the first gate insulating layer; and a first gate capping layer positioned on and in contact with the first gate conductive layer; wherein a height of each of the first spacers is equal to a height of the lower portion and is equal to a sum of heights of the first gate insulating layer, the first gate conductive layer, and the first gate capping layer. The ordinary artisan would have been motivated to modify Yoo et al. (region 99) in the above manner for the purpose of improving current flow control, performance and reliability, and minimizing leakage and power consumption.
Regarding claim 10, Yoo et al. (region 88 and 99) teaches the semiconductor device of claim 9,
Yoo et al. (region 99) further teaches:
wherein the width of the lower portion is gradually decreased towards the substrate [1/70, Fig. 4-10], wherein at least a portion of the upper portion is in contact with a top surface of one of the first gate structure [14 (left), Fig. 10] and the second gate structure [14 (right), Fig. 10].
Regarding claim 11, Yoo et al. (region 88 and 99) teaches the semiconductor device of claim 9,
Yoo et al. (region 99) further teaches:
further comprising a dielectric layer [17, Col. 7, Lines 24-28, Fig. 8-10] positioned on the substrate [1/70, Fig. 8-10], covering the first gate structure [14 (left), Fig. 8-10] and the second gate structure [14 (right), Fig. 8-10], and surrounding the upper portion, wherein the impurity region [15, Fig. 10] of the substrate [1/70, Fig. 10] is positioned between the first gate structure [14 (left), Fig. 8-10] and the second gate structure [14 (right), Fig. 8-10] at a position that a width of the impurity region [15, Fig. 10] of the substrate [1/70, Fig. 8-10] is equal to a distance between the first gate structure [14 (left), Fig. 8-10] and the second gate structure [14 (right), Fig. 8-10].
Regarding claim 13, Yoo et al. (region 88 and 99) teaches the semiconductor device of claim 9,
Yoo et al. (region 99) further teaches:
wherein a thickness of the first gate capping layer [13, Col. 6, Lines 62-65, Fig. 6-10] is less than a thickness of the first gate conductive layer [10, Col. 6, Lines 51-53, Fig. 6-10] and is larger than a thickness of the first gate insulating layer [9, Col. 6, Lines 47-51, Fig. 6-10].
It should be noted that the limitation of claim 13 also applies to the gate structure in Yoo et al. region 88.
wherein a thickness of the first gate capping layer [8, Col. 6, Lines 21-29, Fig. 6-10] is less than a thickness of the first gate conductive layer [4, Col. 5, Lines 26-29, Fig. 6-10] and is larger than a thickness of the first gate insulating layer [3, Col. 5, Lines 22-26, Fig. 6-10].
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Yoo et al. (US 6168984 B1) as applied to claim 9 above, and further in view of Jeon et al. (US 20070063295 A1) and Chuang et al. (US 9831235 B2).
Regarding claim 12, Yoo et al. (region 88 and 99) teaches the semiconductor device of claim 9,
Yoo et al. (region 99) further teaches:
wherein the plurality of first spacers [16, Col. 7, Lines 21-23, Fig. 7-10] comprise silicon nitride, silicon oxynitride, or silicon nitride oxide;
wherein the gate insulating layer [9, Fig. 6-10], the gate conductive layer [10, Fig. 6-10], and the first gate capping layer [13, Fig. 6-10] are equal in width;
wherein the first spacers [16, Fig. 7-10] and the lower portion are upwardly extended within the impurity region [15, Fig. 7-10] of the substrate [1/70, Fig. 1-10], such that the width of the lower portion is less than the width of the impurity region [15, Fig. 10];
Yoo et al. (region 88 and 99) does not teach:
wherein the first gate insulating layer comprises a high-k material.
Jeon et al. teaches:
wherein the first gate insulating layer [135, paragraph [0037], Claim 22, Fig. 1-2, 3E] comprises a high-k material.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Jeon et al. into the teachings of Yoo et al. (region 88 and 99) to include wherein the first gate insulating layer comprises a high-k material. The ordinary artisan would have been motivated to modify Yoo et al. (region 88 and 99) in the above manner for the purpose of preventing leakage, improving power consumption and reliability, decreasing thickness and increasing density and capacitance.
Yoo et al. (region 88 and 99) and Jeon et al. do not teach:
wherein the first gate conductive layer is made of titanium nitride or tungsten.
Chuang et al. teaches:
wherein the first gate conductive layer [120, Col. 3, Lines 6-7, Fig. 1A] is made of titanium nitride or tungsten.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Chuang et al. into the teachings of Yoo et al. (region 88 and 99) and Jeon et al. to include wherein the first gate conductive layer is made of titanium nitride or tungsten. The ordinary artisan would have been motivated to modify Yoo et al. (region 88 and 99) and Jeon et al. in the above manner for the purpose of increased hardness preventing deformation, improving thermal conductivity and heat dissipation, enhancing lifespan, and improving electrical conductivity.
Response to Arguments
Applicant’s arguments, see page 1, Election/Restrictions in remarks, filed August 14, 2025, with respect to claim 10 have been fully considered and are persuasive. The Examiners Election withdrawal of claim 10 has been withdrawn.
Applicant’s arguments, see page 1, Claim Rejections – 35 USC §112 in remarks, filed August 14, 2025, with respect to claims 9 and 13 have been fully considered and are persuasive. The 35 USC §112 rejection of claims 9 and 13 has been withdrawn.
Applicant's arguments filed August, 14, 2025 have been fully considered but they are not persuasive. Applicant argues on pages 2-3, section (a) and (b), of remarks filed August 14, 2025 that current primary reference Yoo et al. (US 6168984 B1) does not teach the amendments to claim 9. Examiner disagrees with Applicant, the amended limitations of claim 9 can be overcome by Yoo et al. as cited on page 12 of non-final rejection filed July 29, 2025, and after a new line of consideration.
Applicant's arguments filed August, 14, 2025 have been fully considered but they are not persuasive. Applicant argues on pages 3-4, section (c), of remarks filed August 14, 2025 that current primary reference Yoo et al. (US 6168984 B1) does not teach the amendments to claim 12. Examiner agrees with Applicant, however after a new line of search and consideration the amended limitations of claim 12 can be overcome by Chuang et al. (US 9831235 B2).
Applicant's arguments filed August, 14, 2025 have been fully considered but they are not persuasive. Applicant argues on page 4, section (d), of remarks filed August 14, 2025 that current primary reference Yoo et al. (US 6168984 B1) does not teach the amendments to claim 13. Examiner disagrees with Applicant, the amended limitation of claim 13 can be overcome by primary reference Yoo et al. (US 6168984 B1).
In summary, the amendments to claims 9, 12 and 13 can be overcome by new considerations of Yoo et al. (US 6168984 B1), and by newly added reference Chuang et al. (US 9831235 B2). All claims directly or indirectly dependent on claims 9, 12 and 13 are also unpatentable for at least the reasons mentioned above.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/D.M.H./Examiner, Art Unit 2815 10/17/2025
/MONICA D HARRISON/Primary Examiner, Art Unit 2815