Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 1/26/2026 has been entered.
Response to Amendment
The amendment filed 1/26/2026 has been entered. Claims 1-26 remain pending.
Applicant’s amendments of claims 19, 24, and 25 have overcome the 112(a) and 112(b) rejections. Thus, Examiner withdraws the 112(a) and 112(b) rejections of these claims.
Response to Arguments
Applicant's arguments with respect to amended claim 1 have been fully considered but they are not persuasive.
Applicant chiefly argues that NakashimaA and Kakefu do not disclose that the switching elements exist in rows and columns as shown, for example, in Fig. 1 of the instant application. However, as noted below in the Claim Rejections, NakashimaA does disclose adding more switching elements to the configuration of Fig. 24. If these elements are arranged in the same manner as NakashimaA currently arranges the switching elements and the diodes, they would be arranged in the manner described by Applicant. Accordingly, Examiner is rejecting the amended claim 1 in view of NakashimaA and Kakefu, and the other claims by extension.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-9 are rejected under 35 U.S.C. 103 as being unpatentable over US20190237448A1 (NakashimaA) in view of US20200395343A1 (Kakefu).
Regarding Claim 1, NakashimaA discloses a semiconductor unit (Fig. 24 – see below, el. 500, Para. [0128]) comprising: a plurality of semiconductor chips (Fig. 24, els. 516A, 516B, Para. [0130]]), each of which has an output electrode (Fig. 4, el. 16e, Para. [0058]) and a control electrode (Fig. 4, el. 16g, Para. [0059]) on a front surface thereof (see Fig. 4) and an input electrode (Fig. 4, el. 16c, Para. [0058]) on a rear surface thereof (see Fig. 4, where 16c is on the back surface); and an insulated circuit board (Fig. 3, see the stack up of els. 1,20, and 19, Para. [0053]), including an insulating plate (Fig. 3, el. 20, which corresponds to Fig. 24, el. 520, Para. [0129]) having, in a plan view of the semiconductor unit, a rectangular shape surrounded by a first side and a second side that are opposite to each other, and a third side and a fourth side that are perpendicular to the first side and the second side and opposite to each other (see Fig. 24), an output circuit pattern (Fig. 24, el. 551, Para. [0129]) provided on a front surface of the insulating plate (see Fig. 24), and an input circuit pattern (Fig. 24, el. 507, Para. [0129]) provided on the front surface of the insulating plate (see Fig. 24), and having a chip area extending from the third side to the fourth side (see annotated Fig. 24 below), the rear surfaces of the plurality of semiconductor chips being bonded to the input circuit pattern in the chip area, to thereby form a plurality of bonding areas (see annotated Fig. 24 below), wherein the output circuit pattern and the input circuit pattern each extend in one direction from the third side to the fourth side (see Fig. 24 below), and the input circuit pattern and the output circuit pattern are disposed in this order side by side in a main current direction that is a direction from the first side toward the second side, wherein the input circuit pattern further has an input terminal area (see annotated Fig. 24 below) that is connected to an electrode (Fig. 24, el. 503, Para. [0128]), wherein the output circuit pattern has an output terminal area that is connected to an electrode (Fig. 24, el. 550, Para. [0128]), and wherein the plurality of bonding areas is arranged in a plurality of columns (see Fig. 24, where the 516A and 516B are arranged in two columns).
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NakashimaA does not disclose a plurality of input terminal connection areas, each of the plurality of input terminal connection areas connected to a first lead frame, does not disclose a plurality of output terminal connection areas, each of which is connected to a second lead frame, does not disclose that the input terminal area, the chip area, and the output terminal are arranged in this order in the main current direction, and does not disclose that the plurality of bonding areas is arranged in a plurality of rows, and is aligned in both the main current direction and a direction perpendicular to the main current direction.
NakashimaA further discloses that the number of semiconductor switching elements may be 3 or more (Para. [0055]).
Kakefu discloses a semiconductor unit (Fig. 7, el. 30, Para. [0037]) with an input circuit pattern (Fig. 7, el. 24a, Para. [0038]), an output circuit pattern (Fig. 7, el. 24c, Para. [0040]), an input terminal connection area (Fig. 7, el. 24a1, Para. [0038]), a plurality of output terminal connection areas (Fig. 7, el. 24c1, Para. Para. 0040]), an input terminal that is connected to a lead frame (Para. [0044]), an output terminal that is connected to a lead frame (Para. [0044]), a chip area (Fig. 7, see region where els. 25 and 26 are mounted), wherein the input terminal area, the chip area, and the output terminal area are arranged in this order in the main current direction (see annotated Fig. 7 below).
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It would have been obvious to one skilled in the art before the effective filing date of the claimed invention to add two more semiconductor elements underneath the two semiconductor elements 516A and 516B so that the resulting configuration has a plurality of rows and columns. NakashimaA already discloses such a geometry (Fig. 24), where 517B and 517A are diodes. Since NakashimaA already contemplates adding more switching elements (see above and Para. [0055]), it would be a simple modification to place them in a similar manner to what has already been discloses (see also MPEP 2144 (VI)(B)).
Further, it would have been obvious to rearrange the input terminal and output terminal such that the input terminal, chip area, and output terminal are arranged in this order in the main current direction, as has been disclosed by Kakefu, for the benefit of a simpler layout structure, where the input terminal is on one side of the chip, and the output terminal is on the opposite, with the chips in between. It would also have been obvious to connect the input and output terminals to lead frames for the purpose of interfacing the chip to the outside (Kakefu, Para. [0031]). Finally, it would have been obvious to have a plurality of input terminal connection areas in order to handle extra current in high power devices.
Regarding Claim 2, NakashimaA in view of Kakefu discloses the semiconductor unit according to claim 1, further comprising output wiring members extending in the main current direction and connecting the output electrodes and the output circuit pattern (see Fig. 24, where wires connect output electrodes of 516a to output circuit pattern 551).
Regarding Claim 3, NakashimaA in view of Kakefu discloses the semiconductor unit according to claim 2, further comprising: a first control circuit pattern (Fig. 24, el. 509, Para. [0129]) provided on the front surface of the insulating plate closer to the first side than is the input circuit pattern (see Fig. 24 above, where the first control circuit pattern 509 is closer to the first side than is the input circuit pattern 507) and being electrically connected to the control electrodes of the plurality of semiconductor chips (see Fig. 24); and a second control circuit pattern (Fig. 24, el. 559, Para. [0129]) provided on the front surface of the insulating plate closer to the second side than is the output circuit pattern (see Fig. 24, where the second control circuit pattern 559 is closer to the second side than the output circuit pattern 551), and being not electrically connected to the control electrodes of the plurality of semiconductor chips (the second control circuit pattern 59 is not connected to the control electrodes of the plurality of semiconductor chips 516a).
Regarding Claim 4, NakashimaA in view of Kakefu discloses the semiconductor unit according to claim 3, wherein the first control circuit pattern is provided adjacent to the input circuit pattern (see Fig. 24, where the first control circuit pattern 509 is adjacent to the input circuit pattern 507).
Regarding Claim 5, NakashimaA in view of Kakefu discloses the semiconductor unit according to claim 3, further comprising control wiring members extending in the main current direction and connecting the control electrodes and the first control circuit pattern (see Fig. 24, where there are control wiring members extending in the main current direction and connecting the control electrodes of 516a with the first control circuit pattern 509).
Regarding Claim 6, NakashimaA in view of Kakefu discloses the semiconductor unit according to claim 3, further comprising: a first sense circuit pattern (Fig. 24, el. 510, Para. [0129]) provided on the front surface of the insulating plate closer to the first side than is the input circuit pattern (see Fig. 24, where the first sense circuit pattern 510 is closer to the first side than is the input circuit pattern 507), and being electrically connected to the output electrodes of the plurality of semiconductor chips (Fig. 24, where the first sense circuit pattern 510 is electrically connected to the output electrodes of the semiconductor chips 516a); and a second sense circuit pattern (Fig. 24, el. 560, Para. [0129]) provided on the front surface of the insulating plate closer to the second side than is the output circuit pattern (see Fig. 24, where the second sense circuit pattern 560 is closer to the second side than the output circuit pattern 551), and being not electrically connected to the output electrodes of the plurality of semiconductor chips (the second sense circuit pattern 560 is not connected to the output electrodes of the semiconductor chips 516a).
Regarding Claim 7, NakashimaA in view of Kakefu discloses the semiconductor unit according to claim 6, further comprising sense wiring members extending in the main current direction and connecting the output electrodes and the first sense circuit pattern (see Fig. 24, where there are sense wiring members extending in the main current direction connecting the first sense circuit pattern 510 and the output electrodes of the semiconductor chips 516a).
Regarding Claim 8, NakashimaA in view of Kakefu discloses the semiconductor unit according to claim 6, wherein the first sense circuit pattern and the second sense circuit pattern are equally distanced from a center line that is perpendicular to the main current direction and passes through a center of the insulating plate (see Fig. 24, where a line that is perpendicular to the main current direction can be drawn in the center, and the first sense circuit pattern 510 and the second sense circuit pattern 560 are equally distanced from the line), and are equally distanced from the first side and the second side, respectively (see Fig. 24, where the first 510 and second 560 sense circuit patterns are equally distanced from the first side and second side).
Regarding Claim 9, NakashimaA in view of Kakefu discloses the semiconductor unit according to claim 6, wherein the first sense circuit pattern is provided closer to the first side than is the first control circuit pattern (see Fig. 24, where the first sense circuit pattern 510 is closer to the first side than the first control circuit pattern 509), and the second sense circuit pattern is provided closer to the second side than is the second control circuit pattern (see Fig. 24, where the second sense circuit pattern 560 is closer to the second side than is the second control circuit pattern 559).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over NakashimaA in view of Kafeku.
Regarding Claim 10, NakashimaA in view of Kafeku discloses the semiconductor unit according to claim 6, wherein the input circuit pattern includes two end portions respectively parallel to and facing the third side and the fourth side (see Fig. 24, where the input circuit pattern 507 is rectangular, and has two end sides that are parallel to the third and fourth side), and the first control circuit pattern extends from one of the two end portions to the other one of the two end portions (see Fig. 24, where the first control circuit pattern 509 extends from one of the two end portions to the other one of the two end portions).
NakashimaA and Kafeku do not disclose that the first sense circuit pattern has a U shape in the plan view, and is provided between the third side and the fourth side so as to surround the first control circuit pattern.
It would have been obvious to one skilled in the art before the effective filing date of the
claimed invention to change the shape of the first sense circuit pattern from the rectangular shape disclosed by NakashimaA to a U shape, and to have it surround the first control circuit. Regarding the U shape, there is no evidence in the specification that the U shape is significant, and so a person of ordinary skill in the art would have found it obvious to shape it that way (see MPEP 2144.04(IV)(B)). Furthermore, once the shape is in a U shape, it would have been obvious to have the first sense circuit pattern surround the first control circuit pattern as this is also a change in shape that has no material significance (none has been provided in the specification).
Regarding Claim 11, NakashimaA in view of Kakefu discloses the semiconductor unit according to claim 6, wherein the second control circuit pattern and the second sense circuit pattern each extend from the third side to the fourth side (see Fig. 24, where the second control circuit pattern 559 and the second sense circuit pattern 560 each extend from the third side to the fourth side).
Regarding Claim 12, NakashimaA in view of Kakefu discloses the semiconductor unit according to claim 3, wherein the first control circuit pattern and the second control circuit pattern are arranged symmetrically with respect to a center line that is perpendicular to the main current direction and passes through a center of each of the third and fourth sides (see Fig. 24, where a center line perpendicular to the main current direction can be drawn, and the first control circuit pattern 509 and the second control circuit pattern 559 are symmetrical with respect to it), and are equally distanced from the first side and the second side, respectively (see Fig. 24, where the first 509 and second 559 control circuit patterns are equally distanced from the first side and second side).
Regarding Claim 13, NakashimaA in view of Kakefu discloses the semiconductor unit according to claim 3, wherein the first control circuit pattern is provided adjacent to the input circuit pattern (see Fig. 24, where the first control circuit pattern 509 is adjacent to the input circuit pattern 507), and the second control circuit pattern is provided adjacent to the output circuit pattern (see Fig. 24, where the second control circuit pattern 560 is adjacent to the output circuit pattern 551).
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over NakashimaA in view of Kakefu.
Regarding Claim 14, NakashimaA in view of Kakefu discloses the semiconductor unit according to claim 1.
NakashimaA does not disclose wherein the input terminal area and the output terminal area are equally distanced from a center line that is perpendicular to the main current direction and passes through a center of each of the third and fourth sides, and are approximately equally distanced from the first side and the second side, respectively.
It would have been obvious to one skilled in the art before the effective filing date of the
claimed invention to take the semiconductor unit disclosed by NakashimaA in view of Kakefu and add input and output terminals to enable the unit to interface with other devices, as is commonly known. Furthermore, it would have been obvious to place the input and output terminals such that they are equally distanced from a center line that is perpendicular to the main current direction, and approximately equally distanced form the first side and the second side, as a matter of design choice because changing the position of the input and output terminals will not change the operation of the device (see MPEP 2144.04(VI)(C).
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over NakashimaA in view of Kakefu.
Regarding Claim 15, NakashimaA in view of Kakefu discloses the semiconductor unit according to claim 1.
NakashimaA in view of Kakefu does not disclose wherein the input circuit pattern has input terminal areas provided closer to the first side than are the plurality of semiconductor chips, and wherein the input terminal areas are linearly disposed along a line parallel to the first side.
It would have been obvious to one skilled in the art before the effective filing date of the
claimed invention to take the semiconductor unit disclosed by Nakashima and add input terminals for the purpose of allowing the unit to interface with other devices. Furthermore, it would have been obvious to place the input terminal areas closer to the first side than are the plurality of semiconductor chips as a way to make it easier to access the terminals. Finally, it would have been obvious to dispose the terminal areas linearly along a line parallel to the first side as a simple design choice that would not modify the operation of the device (see MPEP 2144.04(VI)(C)).
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over NakashimaA in view of Kafeku.
Regarding Claim 16, NakashimaA in view of Kafeku discloses the semiconductor unit according to claim 1.
NakashimaA does not disclose that the control electrode of each of the plurality of semiconductor chips is disposed at one side of the front surface that extends in the main current direction, and does not disclose that in two of the plurality of semiconductor chips that are adjacent to each other in a direction perpendicular to the main current direction, the control electrodes are disposed at mutually facing sides or at mutually opposite sides of the two semiconductor chips.
Kafeku discloses control electrodes that are disposed on one side of the front surface that extends in the main current direction (see Fig. 7, els. 25a and 26a).
It would have been obvious to one skilled in the art before the effective filing date of the claimed invention to rearrange the control electrodes of Nakashima such that they are on a side of the front surface that extends in the main current direction (as in Kafeku), while placing them to be on mutually facing sides or mutually opposite sides. In addition to the disclosure of Kafeku, such a configuration would be a simple rearrangement of parts (MPEP 2144.04 (VI)(C)).
Claim 23 is rejected under 35 U.S.C. 103 as being unpatentable over NakashimaA-Fig. 24 in view of NakashimaA-Fig. 2.
Regarding Claim 23, NakashimaA-Fig.24 discloses the semiconductor unit according to Claim 1.
NakashimaA-Fig.24 does not disclose that the center of the chip area overlaps a center of the insulating plate in the plan view.
NakshimaA-Fig.2 discloses that the center of the chip area overlaps a center of the insulating plate in the plan view.
It would have been obvious to one skilled in the art before the effective filing date of the claimed invention to place the center of the chip area such that it overlaps a center of the insulating plate in the plan view as in NakashimaA-Fig. 2, as this would constitute one half of the half-bridge circuit.
Claims 24 and 25 are rejected under 35 U.S.C. 103 as being unpatentable over NakashimaA in view of Kakefu.
Regarding Claim 24, NakashimaA in view of Kakefu discloses the semiconductor unit according to Claim 1, wherein the insulated circuit board further includes a gate circuit pattern (NakashimaA, Fig. 24, el. 509, Para. [0129]) formed on the front surface thereof (Fig. 24) and extending in the one direction perpendicular to the main current direction (the main current direction is downwards, and the gate circuit pattern extends from left to right).
NakashimaA in view of Kakefu does not disclose that one of the plurality of input terminal connection areas, the contact area, and another of the plurality of input terminal connection areas are arranged in this order in the one direction in the gate circuit pattern and does not disclose that the contact area is arranged at the center of the gate circuit pattern.
However, it would have been obvious to one skilled in the art before the effective filing date of the claimed invention to place the input terminal areas around the contact area and place the contact area in the center of the gate circuit pattern. This constitutes a change of shape to the design that is obvious absent evidence that the particular configuration is significant (MPEP 2144.04 (VI)(C))).
Regarding Claim 25, NakashimaA in view of Kakefu discloses the semiconductor unit according to Claim 24, wherein the contact area is mechanically and electrically connected to the control electrodes of the semiconductor chips by control wires that extend in the main current direction (NakashimaA, see Fig. 24 which shows wires connecting the contact area to the control electrode of the semiconductor chip).
Claim 26 is rejected under 35 U.S.C. 103 as being unpatentable over NakashimaA in view of Kakefu.
Regarding Claim 26, NakashimaA in view of Kakefu discloses the semiconductor device of claim 24, wherein the plurality of bonding areas of the switching elements (NakashimaA, Fig. 24, els. 516A and 516B) and diodes (517A and 517B) are symmetrical with respect to a line of symmetry that is a center line of the insulating plate perpendicular to the main current direction (see Fig. 24).
NakashimaA in view Kakefu does not disclose wherein the plurality of bonding areas of the switching elements is symmetrical with respect to a line of symmetry that is a center line of the insulating plate perpendicular to the main current direction.
However, it would have been obvious to one skilled in the art before the effective filing date of the claimed invention to arrange the switching elements and the diodes in such a way as to make the switching elements symmetrical about a line perpendicular to the main current direction. This would be a rearrangement of parts (the diodes would have to be rearranged) (MPEP 2144 .04 (VI)(C)).
Claims 17 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over NakashimaA in view of US20200185359A1 (NakashimaB).
Regarding Claim 17, NakashimaA discloses a semiconductor device (Fig. 24, els. 500, Para. [0128]), comprising a first arm portion constituted by the semiconductor unit according to claim 1 (Para. [0128]) and a second arm portion (Para. [0128]).
NakashimaA does not disclose that the second arm portion is constituted by the semiconductor unit according to claim 1, and dos not disclose wherein the insulated circuit board of the first arm portion is different from the insulated circuit board of the second arm portion, and wherein the first arm portion and the second arm portion are arranged such that the main current direction of the semiconductor unit that constitutes the first arm portion is opposite to the main current direction of the semiconductor unit that constitutes the second arm portion.
NakashimaB discloses a semiconductor device (Fig. 20 – see figure below, el. 100, Para. [0138]) which has a first arm portion (Fig. 20, el. 200a, Para. [0142]) and a second arm portion (Fig. 20, el. 200b, Para. [0142]) wherein the insulated circuit board of the first arm portion (Fig. 20, el. 7a) is different from the insulated circuit board of the second arm portion (Fig. 20, el. 7b, Para. [0138]).
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It would have been obvious to one skilled in the art before the effective filing date of the
claimed invention to take the semiconductor unit disclosed by NakashimaA and add another semiconductor unit adjacent to it as disclosed by NakashimaB. As disclosed by NakashimaB, doing so reduces concerns about mounting too many semiconductors on the same insulating substrate, which can increase stress on the circuit board (NakashimaB, Para. [0135]). Further, it would have been obvious to orient the second arm in the opposite direction as the first arm so that the first arm and second arm can be connected in series, instead of in parallel, as is disclosed in NakashimaB.
Regarding Claim 18, NakashimaA discloses the semiconductor device according to claim 17, wherein the fourth side of the first arm portion and the fourth side of the second arm portion are adjacent to and face each other (This is inherent when the second semiconductor unit is rotated 180 degrees and is placed next to the first semiconductor unit).
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over NakashimaA in view of NakashimaB.
Regarding Claim 19, NakashimaA in view of NakashimaB discloses the semiconductor device according to claim 18.
NakashimaA in view of NakashimaB discloses the semiconductor device according to claim 18.
NakashimaA in view of NakashimaB does not disclose wherein the first arm portion is disposed in plurality along a line perpendicular to the main current direction, and wherein the second arm portion is disposed in plurality along a line perpendicular to the main current direction.
However, it would have been obvious to one skilled in the art before the effective filing date of the claimed invention to add a plurality of first arm portions and a plurality of second arm portions in order to boost the current handling capability of the device. This would also be an example of duplication of parts (see MPEP MPEP 2144(VI)(B)).
Allowable Subject Matter
Claims 20-22 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding Claim 20, none of the prior art of record teaches, suggests or renders
obvious, either alone or in combination wherein the first arm portion and the second arm portion are each provided in plurality, the first arm portions being arranged repeatedly and alternating with the second arm portions along a line that is perpendicular to the main current direction.
Regarding Claim 21, none of the prior art of record teaches, suggests or renders
obvious, either alone or in combination wherein the first control circuit pattern of the first arm portion and the second control circuit pattern of the second arm portion are electrically connected to each other, and wherein the second control circuit pattern of the first arm portion and the first control circuit pattern of the second arm portion are electrically connected to each other.
Regarding Claim 22, none of the prior art of record teaches, suggests or renders
obvious, either alone or in combination wherein the first arm portion and the second arm portion are adjacent to each other, such that the first side of the first arm portion and the first side of the second arm portion face each other or such that the second side of the first arm portion and the second side of the second arm portion face each other.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ROHIT PARTHASARATHY whose telephone number is (571)272-2572. The examiner can normally be reached Monday-Friday 8:30a-5p.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dale Page can be reached at 5712707877. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ROHIT PARTHASARATHY/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899