DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment filed on Nov. 3rd, 2025 has been entered. Claims 1-4 and 6-13 remain pending in the application. Applicant’s amendments to the Claims have overcome each and every objection previously set forth in the Non-Final Office Action mailed on Aug. 19th, 2025.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-4, 7-12 are rejected under 35 U.S.C. 103 as being unpatentable over Kanaoka et al. (US 20040111689) in view of Tan et al. (US 20090254209) and Chang et al. (US 20120123717).
Regarding claim 1, Kanaoka teaches a processing method (Abstract) of a processing apparatus (scan path timing optimizing apparatus; para. 0040), the method comprising:
step 1: providing an object (place a cell; para. 0038), the object (cell) having a processed surface (fig. 2, surface of areas 1-4; para. 0038), and dividing the processed surface into a plurality of processed regions (areas 1-4), wherein there is at least one workpiece (arbitrary FFs; para. 0038) on each of the processed regions (each area 1-4), an intersection (overlap intersection) of the processed regions (area 1-4) is an empty set (no overlap);
step 2: performing path computation (path compute to shorten length of interconnection; para. 0039) according to the at least one workpiece (FFs) on each of the processed regions (each area 1-4), and generating a processing path (connection of FF in area) in each of the processed regions (each area 1-4), wherein the processing paths (connection of FF in area) in the processed regions (areas) are different (different because the locations of FF) from each other;
determining the processing path (fig. 4, determining order of connection between FFs in area by intra-area connection order determining unit 103; para. 0043) in one of the processed regions (one area) obtained from step 2; and
determining a next processed region (fig. 4, connection between the placement areas to next area by inter-area connection order determining unit 104; para. 0043) after finishing each of the at least one workpiece (FFs in one area) in the one of the processed regions (one area).
Kanaoka fails to explicitly teach step 3: performing processing operation by the processing apparatus according to the processing path,
step 4: moving the processing apparatus after finishing the processing operation.
However, Tan teaches step 3: performing processing operation (Tan: fig. 2, defect repairing; para. 0003) by the processing apparatus (Tan: repairing device 4 as a part of the whole device; para. 0003) according to the processing path (Tan: path P2 between defect X1~8; para. 0003, 0004, similar to FFs of Kanaoka),
step 4: moving the processing apparatus (Tan: move/scan 4 to next X; para. 0002, 0003) after finishing the processing operation (Tan: defect repairing on one X).
Tan and Kanaoka are considered to be analogous to the claimed invention because they are in the same field of method of path connect.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed method to add steps of processing operation by the processing apparatus and moving the processing apparatus as taught by Tan.
Doing so would realize repairing on the defects to improve the Quality in production processes (Tan: para. 0037).
In addition, Kanaoka in view of Tan fails to explicitly teach the processed surface comprises at least one normal region among adjacent ones of the processed regions, wherein the number of workpieces in the at least one normal region is zero.
However, Chang teaches the processed surface (Chang: fig. 6, the surface to be divided into blocks or boxes 1-28, similar to surface of Kanaoka) comprises at least one normal region (Chang: block S26; para. 0027, 0028) among adjacent ones of the processed regions (Chang: regions include block S25, S27 with selected measurement element; para. 0027, 0028, similar to area with FFs of Kanaoka), wherein the number of workpieces (Chang: selected measurement element; para. 0028, similar to FFs of Kanaoka) in the at least one normal region is zero (Chang: S26 has no selected measurement element).
Chang, Tan and Kanaoka are considered to be analogous to the claimed invention because they are in the same field of method of path connect.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed method to add at least one normal region with the number of workpieces in the at least one normal region is zero as taught by Chang.
Doing so would realize a method optimizing paths to better process blocks with zero elements to optimize the paths (Chang: para. 0002).
Regarding claim 2, Kanaoka in view of Tan and Chang further teaches the processing method according to claim 1, wherein, after step 3 and before step 4, the processing apparatus (Tan: fig. 1, 4) moves between adjacent ones of the processed regions (Kanaoka: fig. 2, between area one and next) in a linking path (Kanaoka: connection of FF between areas), the linking path (Kanaoka: connection of FF between areas) links the processing paths (Kanaoka: connection of FF in area) in the processed regions (Kanaoka: areas), and the linking path (Kanaoka: connection of FF between areas) and the processing paths (Kanaoka: connection of FF in area) of the processed regions form a non-overlapping path (Kanaoka: no overlap).
Regarding claim 3, Kanaoka in view of Tan and Chang further teaches the processing method according to claim 1, wherein the processed surface (Kanaoka: fig. 2, surface of areas 1-4) comprises M x N processed regions (Kanaoka: 2X2 areas), where M + N > 2 (2+2>2) and both M and N are positive integers (2 are positive integers), and the processing apparatus (Tan: fig. 1, 4) sequentially moves in the processed regions (Kanaoka: moves area 1-4).
Regarding claim 4, Kanaoka in view of Tan and Chang further teaches the processing method according to claim 1, wherein an area ratio of each of the processed regions (Kanaoka: fig. 2, area ratio of area 1-4) to the processed surface (Kanaoka: surface of areas 1-4) falls within a range from 0.04 to 0.25 (Kanaoka: 0.25).
Regarding claim 6, Kanaoka in view of Tan and Chang further teaches the processing method according to claim 1, wherein, the processing apparatus (Tan: 4) scans over the at least one normal region (Chang: fig. 6, S26) without processing (Chang: no elements to process) when the processing apparatus is moved to the next processed region (Chang: S27), wherein the one of the processed regions (Chang: S25) in step 3 and the next processed region (Chang: S27) in step 4 are adjacent to two sides (Chang: left and right sides) of the at least one normal region (Chang: S25).
Regarding claim 7, Kanaoka in view of Tan and Chang further teaches the processing method according to claim 1, wherein the at least one workpiece (Kanaoka: fig. 2, FFs in areas) comprises a plurality of workpieces (Kanaoka: FFs), and the processing path (Kanaoka: connection of FF in area) is a connection path of the workpieces (Kanaoka: FFs) minimizing a time (Kanaoka: minimize the data transfer time by shortest interconnection; para. 0008) of the processing operation (Tan: fig. 1, defect repairing) performed by the processing apparatus (Tan: 4) in the processed region (Kanaoka: areas).
Regarding claim 8, Kanaoka in view of Tan and Chang further teaches the processing method according to claim 7, wherein the processing path (Kanaoka: fig. 2, connection of FF in area) is a path (Kanaoka: path connection) connected between the workpieces (Kanaoka: FFs) with a minimum distance (Kanaoka: shortest interconnection; para. 0008), and the processing path is not crossed (Kanaoka: no cross).
Regarding claim 9, Kanaoka in view of Tan and Chang further teaches the processing method according to claim 1, further comprising:
before step 1, detecting the processed surface (Kanaoka: fig. 2, surface of areas 1-4) to obtain a position (Kanaoka: placement information; para. 0039) of the at least one workpiece (Kanaoka: FFs) on the processed surface (Kanaoka: surface of areas 1-4).
Regarding claim 10, Kanaoka in view of Tan and Chang further teaches the processing method according to claim 9, further comprising:
dividing the processed surface (Kanaoka: fig. 2, surface of areas 1-4) into a plurality of detection regions (Kanaoka: area 1-4), and detecting each of the detection regions (Kanaoka: area 1-4) to obtain the position (Kanaoka: considering placement information; para. 0039) of the at least one workpiece (Kanaoka: FFs) on the processed surface (Kanaoka: surface of areas 1-4).
Regarding claim 11, Kanaoka in view of Tan and Chang further teaches the processing method according to claim 10, wherein the detection regions (Kanaoka: fig. 2, areas 1-4) respectively overlap the processed regions (Kanaoka: overlaps areas 1-4) on the processed surface (Kanaoka: surface of areas 1-4).
Regarding claim 12, Kanaoka in view of Tan and Chang further teaches the processing method according to claim 1, wherein the processing apparatus (Tan: fig. 1, 4) comprises a laser apparatus (Tan: laser; para. 0041), and the processing operation (Tan: defect repairing) comprises component removal (Tan: remove the redundant materials and foreign particles; para. 0041).
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Kanaoka in view of Tan and Chang as applied to claims 1 above, and further in view of Nishimura et al. (JP 2004253005, machine translation provided).
Regarding claim 13, Kanaoka in view of Tan and Chang teaches the processing method according to claim 1, the processing method further comprising sequentially performing path computation (Kanaoka: path compute to shorten length of interconnection) on the generic region (Kanaoka: fig. 2, area); wherein the first workpiece (Kanaoka: FF3 for area 1 for example) on the generic region (Kanaoka: area) is set to a first workpiece (Kanaoka: FF3) to be processed on the processing path (Kanaoka: connection of FF in area) when performing the path computation (Kanaoka: path compute to shorten length of interconnection), and the processing path (Kanaoka: connection of FF in area) of the processing apparatus (Tan: fig. 1, 4) performing the processing operation (Tan: defect repairing) on the at least one workpiece (Kanaoka: FFs) on the processed region (Kanaoka: area) is generated.
Kanaoka in view of Tan and Chang fails to explicitly teach each of the processed regions comprises m xn sub-regions, where m + n > 2 and m and n are positive integers, the generic region is the m x n sub-regions.
However, Nishimura teaches each of the processed regions (Nishimura: fig. 48, panel 2, areas; para. 0159, similar to areas of Kanaoka) comprises m x n sub-regions (Nishimura: 3X2 units; para. 0159), where m + n > 2 (3+2>2) and m and n are positive integers (3, 2 are positive integers), the generic region is the m x n sub-regions (Nishimura: 3X2 units as an area).
Nishimura, Chang, Tan and Kanaoka are considered to be analogous to the claimed invention because they are in the same field of method of path connect.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed method to add each of the processed regions comprises m xn sub-regions as taught by Nishimura.
Doing so would realize a method optimizing paths to reduce the total stage movement time (Nishimura: para. 0163).
Response to Arguments
Applicant's arguments filed on Nov. 3rd, 2025 have been fully considered but they are not persuasive.
With respect to pages 6- of applicant’s response of claim 1 is rejected under 35 U.S.C.103.
Applicant submits "The minimum bounding box is the smallest box that can enclose all of the measurement elements. Therefore, the minimum box in Fig. 6 of Chang should be interpreted as the claimed the processed regions. The minimum box in Fig. 6 of Chang can enclose all of the measurement elements (be interpreted as the claimed workpieces). Chang fails to teach or suggest the technical feature of "normal region".
The examiner respectfully disagrees.
The "normal region" is not a special term of art. As cited in Specification para. 0025 and fig. 4 of the application, the normal region 250 (in #10 and also marked as 210) can within or have an equal area as the processed region 210. The "normal region" has been interpreted as a region in (of) a processed region and just have 0 workpieces 220. As shown in fig. 6 of Chang, the minimum bounding box surface is divided into blocks or boxes 1-28 for several processed regions and normal regions. Chang teaches the processed surface (the surface to be divided similar to surface of Kanaoka) comprises at least one normal region (for example, region of block or box 26, which have no measurement element and no need to be processed) among adjacent ones of the processed regions (regions include block or box 25 and 27, which with ten and nine measurement elements, similar to processed regions with FFs of Kanaoka and need to be processed), wherein the number of workpieces (measurement element) in the at least one normal region is zero (26 has no measurement element). Generally, Chang teaches there likely have regions of zero measurement element in a block by a M X N kind method to divide a plane and how to better process that. As result, given a broadest reasonable interpretation, Kanaoka in view of Tan and Chang teaches all limitations of claims 1. Details of rejections are discussed above.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ZHIJUN XU whose telephone number is (571)270-3447. The examiner can normally be reached Monday-Thursday 9am-5pm ET.
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/ZHIJUN XU/Examiner, Art Unit 2818
/BRIAN TURNER/Examiner, Art Unit 2818