DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This office Action is in response to Applicant’s amendment filed on June 08, 2026. Claims 1, 3-17 have been amended. New claims 21-23 have been added. Claims 18-20 have been canceled. Currently claims 1-17 and 21-23 are pending.
Response to Arguments
Applicant’s arguments with respect to claims 1, 3-17 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5, 7-14, 16-17 and 21-23 are rejected under 35 U.S.C. 103 as being unpatentable over BAEK, Jaejik (US 20230343823 A1) “BAEK et al.” in view of HE, MING (US 20230178440 A1) “HE et al.” further in view of Chanemougame, Daniel (US 10090193 B1) “Chanemougame et al.”.
Regarding Independent Claim 1, BAEK et al. Fig. 1-11 discloses a semiconductor structure (“a multi-stack semiconductor device” ¶ [0026]) comprising:
a first nanosheet stack (“a nanosheet stack 10 may include a lower channel structure 10L,” ¶ [0028]) including a plurality of first semiconductor layers (“each of these stacks includes a plurality of semiconductor nanosheet layers (hereafter “nanosheet layers”) that include a plurality of sacrificial layers, channel layers, sacrificial isolation layers and channel isolation layers as described below” ¶ [0028]);
a second nanosheet stack formed over (“a nanosheet stack 10 may include …. upper channel structure 10U in this order on a substrate 105” ¶ [0028]) first nanosheet stack and including a plurality of second semiconductor layers (“each of these stacks includes a plurality of semiconductor nanosheet layers (hereafter “nanosheet layers”) that include a plurality of sacrificial layers, channel layers, sacrificial isolation layers and channel isolation layers as described below” ¶ [0028]), wherein the second nanosheet stack has a stepped nanosheet formation with respect the first nanosheet stack (Fig. 1B shows the stepped nanosheet);
a first epitaxial growth formed adjacent to the plurality of second semiconductor layers (“the lower source/drain region 170S may be epitaxially grown from the lower channel layers 110C” ¶ [0068]); and
a second epitaxial growth formed adjacent to the plurality of second semiconductor layers (“upper source/drain region 180S may be epitaxially grown from the upper channel layers 120C” ¶ [0068]),
However, BAEK et al. does not disclose, the second epitaxial growth has a stepped formation with respect to the first epitaxial growth and a nitride cap disposed over the second epitaxial growth, wherein, at the stepped formation of the second epitaxial growth, a first sidewall of the nitride cap and a second sidewall of the second epitaxial growth terminate along a common step edge.
In the similar field of endeavor of structures or layer of semiconductor devices including a nanosheet transistor HE et al. Figs. discloses, wherein the second epitaxial growth (“upper source/drain regions 42_U” ¶ [0039]) has a stepped formation (Fig. 16A shows stepped formation of 42_U and 42_L) with respect to the first epitaxial growth (“lower source/drain regions 42_L may be formed” ¶ [0030]).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify epitaxial growth of BAEK et al. with the stepped epitaxial growth of HE et al. in order to manufacture an integrated circuit device including stacked transistors, such as a complementary field effect transistor (CFET) stack, was introduced to reduce an area thereof to close to one-half of the area of a corresponding non-stacked device (HE et al. ¶ [0003]).
However, HE et al. does not disclose, a nitride cap disposed over the second epitaxial growth, wherein, at the stepped formation of the second epitaxial growth, a first sidewall of the nitride cap and a second sidewall of the second epitaxial growth terminate along a common step edge.
PNG
media_image1.png
671
636
media_image1.png
Greyscale
Annotated Fig. 17B
In the similar field of endeavor of stacked FET devices, Chanemougame et al. Figs. 2E, 14D, 17B discloses a nitride cap 105 disposed over the second epitaxial growth 122a-122b, 142a-142b (“conformal dielectric layer 105 of the first dielectric material (e.g., silicon nitride) covers the second source/drain regions 122a-122b, 142a-142b” Column 9, Lines 1-3), wherein, at the stepped formation of the second epitaxial growth 122a-122b, 142a-142b, a first sidewall (right side nitride layer 105) of the nitride cap 105 and a second sidewall (right side of 122b, 142a) of the second epitaxial growth 122a-122b, 142a-142b terminate along a common step edge (Annotated Fig. 17B shows a first sidewall (right side nitride layer 105) of the nitride cap 105 and a second sidewall (right side of 122b, 142a) of the second epitaxial growth terminate along a common step edge).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify epitaxial growth of BAEK et al. as modified by HE et al. with the nitride cap over second epitaxial growth of Chanemougame et al. in order to cover the partially completed structure and, particularly, the second source/drain regions (Chanemougame et al. Column 17, Lines 29-20).
Regarding Claim 2, BAEK et al. as modified by HE et al. and Chanemougame et al. discloses the limitations of claim 1. BAEK et al. Fig. 6, further discloses, wherein the second epitaxial growth (180S, 180D) has a volume greater (Fig. 6 shows 180S, 180D has greater volume than 170S, 170D) than a volume of the first epitaxial growth (170S, 170D).
Regarding Claim 3, BAEK et al. as modified by HE et al. and Chanemougame et al. discloses the limitations of claim 1. However, BAEK et al. does not discloses, wherein the first epitaxial growth is isolated from the second epitaxial growth by an oxide layer and a further nitride cap disposed between the first epitaxial growth and the second epitaxial growth.
In the similar field of endeavor of structures or layer of semiconductor devices including a nanosheet transistor HE et al. Figs. 1-18 discloses, wherein the first epitaxial growth 42_L is isolated from the second epitaxial growth 42_U by an oxide layer (“preliminary capping layers 43 may each be a silicon layer, and the silicon layer may be converted to a silicon oxide layer by an oxidation process” ¶ [0035]; “The capping layers 44 may be formed by converting the preliminary capping layers 43 to the capping layers 44. The preliminary capping layers 43 may be converted by an oxidation process and/or a nitridation process performed on the preliminary capping layers 43. The oxidation process and/or the nitridation process may include, for example, a plasma oxidation and/or a plasma nitridation using a gas comprising oxygen, nitrogen and/or ammonia.” ¶ [0034]).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify epitaxial growth of BAEK et al. with the stepped epitaxial growth of HE et al. in order to manufacture an integrated circuit device including stacked transistors, such as a complementary field effect transistor (CFET) stack, was introduced to reduce an area thereof to close to one-half of the area of a corresponding non-stacked device (HE et al. ¶ [0003]).
However, HE et al. does not disclose a further nitride cap disposed between the first epitaxial growth and the second epitaxial growth.
In the similar field of endeavor of stacked FET devices, Chanemougame et al. Figs. 2E, 14D, 17B discloses a further nitride cap 104 disposed between (“another conformal dielectric layer 104 of the first dielectric material (e.g., silicon nitride) can be deposited over the partially completed structure and, particularly, over the first source/drain regions,” Column 16, Lines 53-55) the first epitaxial growth 112a-112b, 132a-132b (“first source/drain regions 112a-112b, 132a-132b can be made of an epitaxial semiconductor material” Column 7, Lines 4-5) and the second epitaxial growth 122a-122b, 142a-142b (“second source/drain regions 122a-122b, 142a-142b can be made of an epitaxial semiconductor material,” Column 7, Lines 46-47).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify epitaxial growth of BAEK et al. as modified by HE et al. with a second dielectric layer between the first and second epitaxial growth of Chanemougame et al. so that the second source/drain regions will be on opposing sides of the sacrificial gates, above and electrically isolated from the first source/drain regions by the conformal dielectric layers (Chanemougame et al. Column 17, Lines 29-20).
Regarding Claim 4, BAEK et al. as modified by HE et al. and Chanemougame et al. discloses the limitations of claim 1. BAEK et al. Figs. 1-11, further discloses, wherein a first work function metal surrounds the plurality of first semiconductor layers and the plurality of second semiconductor layers (“Each of the lower and upper gate metal patterns 220L, 220U may include a work-function metal layer and a conductor layer” ¶ [0088]; Fig. 10B shows work function metal surrounds the plurality of first semiconductor layers and the plurality of second semiconductor layers).
Regarding Claim 5, BAEK et al. as modified by HE et al. and Chanemougame et al. discloses the limitations of claim 4. BAEK et al. Figs. 1-11, further discloses, wherein a second work function metal is disposed over the first work function metal (“Each of the lower and upper gate metal patterns may include a work-function metal layer and a conductor layer. The work-function metal layer may be formed of Ti, Ta or their compound such as TiN, TiAl, TiAlN, TaN, TiC, TaC, TiAlC, TaCN, TaSiN, and/or a combination thereof, not being limited thereto. The conductor layer may be formed of Cu, Al, W, Mo, Ru or their compound, not being limited thereto.” ¶ [0119]).
However, BAEK et al. does not disclose, a second work function metal is in direct contact with the first work function metal.
In the similar field of endeavor of stacked FET devices, Chanemougame et al. Figs. 2E, 14D, 17B discloses a second work function metal is in direct contact with the first work function metal (“the shared gate 151, 156 can further include a conformal second work function metal layer, which is different from the first work function metal layer, which is immediately adjacent to the portion of the gate dielectric layer on the second channel region(s), and which is preselected for optimal performance of a second-type FET” Column 9, Lines 38-43).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify work function metal of BAEK et al. as modified by HE et al. with a first and second work function metal of Chanemougame et al. for optimal performance (Chanemougame et al. Column 9, Lines 42-43).
Regarding Claim 7, BAEK et al. as modified by HE et al. discloses the limitations of claim 4. BAEK et al. Figs. 1-11, further discloses, wherein one or more first inner spacers are disposed directly between the first work function metal and the first epitaxial growth (“these source/drain regions are isolated from the sacrificial layers 110S and 120S by the inner spacers 165” ¶ [0071]).
Regarding Claim 8, BAEK et al. as modified by HE et al. discloses the limitations of claim 4. BAEK et al. Figs. 1-11, further discloses, wherein one or more second inner spacers are disposed directly between the first work function metal and the second epitaxial growth (“these source/drain regions are isolated from the sacrificial layers 110S and 120S by the inner spacers 165” ¶ [0071]).
Regarding Claim 9, BAEK et al. as modified by HE et al. discloses the limitations of claim 1. However, BAEK et al. does not disclose, wherein one or more first inner spacers disposed adjacent to the first epitaxial growth are vertically offset from one or more second inner spacers disposed adjacent to the second epitaxial growth.
In the similar field of endeavor of structures or layer of semiconductor devices including a nanosheet transistor HE et al. Figs. 1-18 discloses, wherein inner spacers 24_L disposed adjacent to the first epitaxial growth 42_L are vertically offset (Fig. 16A shows inner spacers 24_L are vertically offset from inner spacers 24_U) from one or more second inner spacers 24_U disposed adjacent to the second epitaxial growth 42_U.
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify inner spacer of BAEK et al. with the inner spacer of HE et al. in order to manufacture an integrated circuit device including stacked transistors, such as a complementary field effect transistor (CFET) stack, was introduced to reduce an area thereof to close to one-half of the area of a corresponding non-stacked device (HE et al. ¶ [0003]).
Regarding Independent Claim 10, BAEK et al. Fig. 1-11 discloses a semiconductor structure (“a multi-stack semiconductor device” ¶ [0026]) comprising:
a first field effect transistor (FET) (“a nanosheet stack 10 may include a lower channel structure 10L,” ¶ [0028]; “nanosheet transistor is also referred to with various different names such as multi-bridge channel FET (MBCFET)” ¶ [0003])
a second FET stacked over the first FET (“a nanosheet stack 10 may include …. upper channel structure 10U in this order on a substrate 105” ¶ [0028]), wherein the second FET is disposed in a stepped configuration with respect to the first FET (Fig. 1B shows the second FET is disposed in a stepped configuration with respect to the first FET);
a first epitaxial growth formed adjacent to the first FET (“the lower source/drain region 170S may be epitaxially grown from the lower channel layers 110C” ¶ [0068]); and occupying a first space (Space occupied by 170S);
a second epitaxial growth formed adjacent to the second FET (“upper source/drain region 180S may be epitaxially grown from the upper channel layers 120C” ¶ [0068]).
and occupying a second space (Space occupied by 180S), wherein the second space is greater than the first space (Fig. 11A shows 180S and 180D occupies a space greater than 170S and 170D),
However, BAEK et al. does not disclose, the second epitaxial growth has a stepped formation with respect to the first epitaxial growth and a nitride cap disposed over the second epitaxial growth, wherein, at the stepped formation of the second epitaxial growth, a first sidewall of the nitride cap and a second sidewall of the second epitaxial growth terminate along a common step edge.
In the similar field of endeavor of structures or layer of semiconductor devices including a nanosheet transistor HE et al. Figs. discloses, wherein the second epitaxial growth (“upper source/drain regions 42_U” ¶ [0039]) has a stepped formation (Fig. 16A shows stepped formation of 42_U and 42_L) with respect to the first epitaxial growth (“lower source/drain regions 42_L may be formed” ¶ [0030]).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify epitaxial growth of BAEK et al. with the stepped epitaxial growth of HE et al. in order to manufacture an integrated circuit device including stacked transistors, such as a complementary field effect transistor (CFET) stack, was introduced to reduce an area thereof to close to one-half of the area of a corresponding non-stacked device (HE et al. ¶ [0003]).
However, HE et al. does not disclose, a nitride cap disposed over the second epitaxial growth, wherein, at the stepped formation of the second epitaxial growth, a first sidewall of the nitride cap and a second sidewall of the second epitaxial growth terminate along a common step edge.
In the similar field of endeavor of stacked FET devices, Chanemougame et al. Figs. 2E, 14D, 17B discloses a nitride cap 105 disposed over the second epitaxial growth 122a-122b, 142a-142b (“conformal dielectric layer 105 of the first dielectric material (e.g., silicon nitride) covers the second source/drain regions 122a-122b, 142a-142b” Column 9, Lines 1-3), wherein, at the stepped formation of the second epitaxial growth 122a-122b, 142a-142b, a first sidewall (right side nitride layer 105) of the nitride cap 105 and a second sidewall (right side of 122b, 142a) of the second epitaxial growth 122a-122b, 142a-142b terminate along a common step edge (Annotated Fig. 17B shows a first sidewall (right side nitride layer 105) of the nitride cap 105 and a second sidewall (right side of 122b, 142a) of the second epitaxial growth terminate along a common step edge).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify epitaxial growth of BAEK et al. as modified by HE et al. with the nitride cap over second epitaxial growth of Chanemougame et al. in order to cover the partially completed structure and, particularly, the second source/drain regions (Chanemougame et al. Column 17, Lines 29-20).
Regarding Claim 11, BAEK et al. HE et al. and Chanemougame et al. discloses the limitations of claim 10. BAEK et al. Figs. 1B and 2B further disclose, the first FET (“a lower nanosheet transistor to be formed from the lower channel structure 10L.” ¶ [0032]; “the nanosheet transistor is also referred to with various different names such as multi-bridge channel FET (MBCFET)” ¶ [0003]) is laterally wider (Fig. 1B and 2B show lower transistor (FET) is wider than the upper transistor (FET)) than the second FET (“an upper-stack nanosheet transistor to be formed from the upper channel structure 10U.” ¶ [0032]) to define a ledge (Fig. 1B and 2B show the ledge).
Regarding Claim 12, BAEK et al. HE et al. and Chanemougame et al. discloses the limitations of claim 10. However, BAEK et al. does not discloses, wherein the first epitaxial growth is isolated from the second epitaxial growth by an oxide layer and a further nitride cap disposed between the first epitaxial growth and the second epitaxial growth.
In the similar field of endeavor of structures or layer of semiconductor devices including a nanosheet transistor HE et al. Figs. 1-18 discloses, wherein the first epitaxial growth 42_L is isolated from the second epitaxial growth 42_U by an oxide layer (“preliminary capping layers 43 may each be a silicon layer, and the silicon layer may be converted to a silicon oxide layer by an oxidation process” ¶ [0035]; “The capping layers 44 may be formed by converting the preliminary capping layers 43 to the capping layers 44. The preliminary capping layers 43 may be converted by an oxidation process and/or a nitridation process performed on the preliminary capping layers 43. The oxidation process and/or the nitridation process may include, for example, a plasma oxidation and/or a plasma nitridation using a gas comprising oxygen, nitrogen and/or ammonia.” ¶ [0034]).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify epitaxial growth of BAEK et al. with the stepped epitaxial growth of HE et al. in order to manufacture an integrated circuit device including stacked transistors, such as a complementary field effect transistor (CFET) stack, was introduced to reduce an area thereof to close to one-half of the area of a corresponding non-stacked device (HE et al. ¶ [0003]).
However, HE et al. does not disclose a further nitride cap disposed between the first epitaxial growth and the second epitaxial growth.
In the similar field of endeavor of stacked FET devices, Chanemougame et al. Figs. 2E, 14D, 17B discloses a further nitride cap 104 disposed between (“another conformal dielectric layer 104 of the first dielectric material (e.g., silicon nitride) can be deposited over the partially completed structure and, particularly, over the first source/drain regions,” Column 16, Lines 53-55) the first epitaxial growth 112a-112b, 132a-132b (“first source/drain regions 112a-112b, 132a-132b can be made of an epitaxial semiconductor material” Column 7, Lines 4-5) and the second epitaxial growth 122a-122b, 142a-142b (“second source/drain regions 122a-122b, 142a-142b can be made of an epitaxial semiconductor material,” Column 7, Lines 46-47).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify epitaxial growth of BAEK et al. as modified by HE et al. with a second dielectric layer between the first and second epitaxial growth of Chanemougame et al. so that the second source/drain regions will be on opposing sides of the sacrificial gates, above and electrically isolated from the first source/drain regions by the conformal dielectric layers (Chanemougame et al. Column 17, Lines 29-20).
Regarding Claim 13, BAEK et al. as modified by HE et al. and Chanemougame et al. discloses the limitations of claim 10. BAEK et al. Figs. 1-11, further discloses, wherein a first work function metal surrounds a plurality of first semiconductor layers and the plurality of second semiconductor layers (“Each of the lower and upper gate metal patterns 220L, 220U may include a work-function metal layer and a conductor layer” ¶ [0088]; Fig. 10B shows work function metal surrounds the plurality of first semiconductor layers and the plurality of second semiconductor layers).
Regarding Claim 14, BAEK et al. as modified by HE et al. and Chanemougame et al. discloses the limitations of claim 13. BAEK et al. Figs. 1-11, further discloses, wherein a second work function metal is disposed over the first work function metal (“Each of the lower and upper gate metal patterns may include a work-function metal layer and a conductor layer. The work-function metal layer may be formed of Ti, Ta or their compound such as TiN, TiAl, TiAlN, TaN, TiC, TaC, TiAlC, TaCN, TaSiN, and/or a combination thereof, not being limited thereto. The conductor layer may be formed of Cu, Al, W, Mo, Ru or their compound, not being limited thereto.” ¶ [0119]).
However, BAEK et al. does not disclose, a second work function metal is in direct contact with the first work function metal.
In the similar field of endeavor of stacked FET devices, Chanemougame et al. Figs. 2E, 14D, 17B discloses a second work function metal is in direct contact with the first work function metal (“the shared gate 151, 156 can further include a conformal second work function metal layer, which is different from the first work function metal layer, which is immediately adjacent to the portion of the gate dielectric layer on the second channel region(s), and which is preselected for optimal performance of a second-type FET” Column 9, Lines 38-43).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify work function metal of BAEK et al. as modified by HE et al. with a first and second work function metal of Chanemougame et al. for optimal performance (Chanemougame et al. Column 9, Lines 42-43).
Regarding Claim 16, BAEK et al. as modified by HE et al. and Chanemougame et al. discloses the limitations of claim 4. BAEK et al. Figs. 1-11, further discloses, BAEK et al. Figs. 1-11, further discloses, wherein one or more first inner spacers are disposed directly between the first work function metal and the first epitaxial growth (“at least one lower inner spacer isolating the lower source/drain regions from the lower gate structure” ¶ [0010]; “these source/drain regions are isolated from the sacrificial layers 110S and 120S by the inner spacers 165” ¶ [0071]),
and wherein one or more second inner spacers are disposed directly between the first work function metal and the second epitaxial growth (“at least one upper inner spacer isolating the upper source/drain regions from the upper gate structure” ¶ [0010]; “these source/drain regions are isolated from the sacrificial layers 110S and 120S by the inner spacers 165” ¶ [0071]).
Regarding Claim 17, BAEK et al. as modified by HE et al. and Chanemougame et al. discloses the limitations of claim 10. However, BAEK et al. does not disclose, wherein one or more first inner spacers disposed adjacent to the first epitaxial growth are vertically offset from one or more second inner spacers disposed adjacent to the second epitaxial growth.
In the similar field of endeavor of structures or layer of semiconductor devices including a nanosheet transistor HE et al. Figs. 1-18 discloses, wherein inner spacers 24_L disposed adjacent to the first epitaxial growth 42_L are vertically offset (Fig. 16A shows inner spacers 24_L are vertically offset from inner spacers 24_U) from one or more second inner spacers 24_U disposed adjacent to the second epitaxial growth 42_U.
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify inner spacer of BAEK et al. with the inner spacer of HE et al. in order to manufacture an integrated circuit device including stacked transistors, such as a complementary field effect transistor (CFET) stack, was introduced to reduce an area thereof to close to one-half of the area of a corresponding non-stacked device (HE et al. ¶ [0003]).
Regarding Claim 21, BAEK et al. HE et al. and Chanemougame et al. discloses the limitations of claim 1. BAEK et al. Figs. 1B and 2B further disclose, the first nanosheet stack (“a lower nanosheet transistor to be formed from the lower channel structure 10L.” ¶ [0032]) is laterally wider (Fig. 1B and 2B show lower transistor (FET) is wider than the upper transistor (FET)) than the second nanosheet stack (“an upper-stack nanosheet transistor to be formed from the upper channel structure 10U.” ¶ [0032]) to define a ledge (Fig. 1B and 2B show the ledge).
Regarding Claim 22, BAEK et al. as modified by HE et al. and Chanemougame et al. discloses the limitations of claim 1. However, BAEK et al. does not discloses, an oxide layer disposed over the first epitaxial growth; and a further nitride cap disposed between the first epitaxial growth and the second epitaxial growth, wherein the second epitaxial growth is disposed over the further nitride cap.
In the similar field of endeavor of structures or layer of semiconductor devices including a nanosheet transistor HE et al. Figs. 1-18 discloses, an oxide layer (“preliminary capping layers 43 may each be a silicon layer, and the silicon layer may be converted to a silicon oxide layer by an oxidation process” ¶ [0035]; “The capping layers 44 may be formed by converting the preliminary capping layers 43 to the capping layers 44. The preliminary capping layers 43 may be converted by an oxidation process and/or a nitridation process performed on the preliminary capping layers 43. The oxidation process and/or the nitridation process may include, for example, a plasma oxidation and/or a plasma nitridation using a gas comprising oxygen, nitrogen and/or ammonia.” ¶ [0034]) disposed over the first epitaxial growth 42_L (“Referring to FIGS. 1, 13A and 13B, preliminary capping layers 43 may be formed on the lower source/drain regions 42_L, respectively” ¶ [0031]).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify epitaxial growth of BAEK et al. with the stepped epitaxial growth of HE et al. in order to manufacture an integrated circuit device including stacked transistors, such as a complementary field effect transistor (CFET) stack, was introduced to reduce an area thereof to close to one-half of the area of a corresponding non-stacked device (HE et al. ¶ [0003]).
However, HE et al. does not disclose a further nitride cap disposed between the first epitaxial growth and the second epitaxial growth, wherein the second epitaxial growth is disposed over the further nitride cap.
In the similar field of endeavor of stacked FET devices, Chanemougame et al. Figs. 2E, 14D, 17B discloses a further nitride cap 104 disposed between (“another conformal dielectric layer 104 of the first dielectric material (e.g., silicon nitride) can be deposited over the partially completed structure and, particularly, over the first source/drain regions,” Column 16, Lines 53-55) the first epitaxial growth 112a-112b, 132a-132b (“first source/drain regions 112a-112b, 132a-132b can be made of an epitaxial semiconductor material” Column 7, Lines 4-5) and the second epitaxial growth 122a-122b, 142a-142b (“second source/drain regions 122a-122b, 142a-142b can be made of an epitaxial semiconductor material,” Column 7, Lines 46-47).
wherein the second epitaxial growth 122a-122b, 142a-142b is disposed over (Figs. 2E, 14D, 17B shows second epitaxial growth is disposed over the further nitride cap 104) the further nitride cap 104.
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify epitaxial growth of BAEK et al. as modified by HE et al. with a second dielectric layer between the first and second epitaxial growth of Chanemougame et al. so that the second source/drain regions will be on opposing sides of the sacrificial gates, above and electrically isolated from the first source/drain regions by the conformal dielectric layers (Chanemougame et al. Column 17, Lines 29-20).
Regarding Claim 23, BAEK et al. as modified by HE et al. and Chanemougame et al. discloses the limitations of claim 10. BAEK et al. Figs. 11A-11B further discloses, further comprising a first metal contact contacting the second epitaxial growth (“upper source/drain region contact structures 180SC and 180DC are connected to the upper source/drain regions 180S and 180D” ¶ [0093]) and a second metal contact contacting the first epitaxial growth (“a lower source/drain region contact structure 170SC is connected to the lower source/drain region 170S” ¶ [0093]).
Claims 6 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over BAEK, Jaejik (US 20230343823 A1) “BAEK et al.” in view of HE, MING (US 20230178440 A1) “HE et al.” further in view of Chanemougame, Daniel (US 10090193 B1) “Chanemougame et al.” further in view of YUN, Seungchan (US 20230343824 A1) “YUN et al.”.
Regarding Claim 6, BAEK et al. as modified by HE et al. and Chanemougame et al. discloses the limitations of claim 4. However, BAEK et al. does not disclose, wherein the first work function metal is horizontally aligned with the first epitaxial growth and the second epitaxial growth.
In the similar field of endeavor of structures or layer of semiconductor devices including a nanosheet transistor YUN et al. Figs. 1A-1D discloses, wherein the first work function metal 115F is horizontally aligned (“an initial work-function metal layer 115F′ and an initial gate electrode pattern 115P′. The gate dielectric layer 115D′ with the initial work-function metal layer 115F′ thereon may surround both the lower channel layers 110C of the lower channel structure 110 and the upper channel layers 120C of the upper channel structure 120. The initial gate electrode pattern 115P′ may be patterned to be formed on the initial work-function metal layer 115F′” ¶ [0065]) with the first epitaxial growth 112 and second epitaxial growth 122 (“the upper source/drain regions 122 grown from the upper channel structure 120 may have a smaller width than the lower source/drain regions 112 grown from the lower channel structure 110 (as shown in FIGS. 1A-1D).” ¶ [0064]).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify work function metal of BAEK et al. with the work function metal of YUN et al. in order to form a lower gate electrode for the lower nanosheet transistor for the purposes of cost-effectiveness, manufacturing simplicity and protection of a lower work-function metal layer (YUN et al. ¶ [0119]).
Regarding Claim 15, BAEK et al. as modified by HE et al. and Chanemougame et al. discloses the limitations of claim 13. However, BAEK et al. does not disclose, wherein the first work function metal is horizontally aligned with the first epitaxial growth and the second epitaxial growth.
In the similar field of endeavor of structures or layer of semiconductor devices including a nanosheet transistor YUN et al. Figs. 1A-1D discloses, wherein the first work function metal 115F is horizontally aligned (“an initial work-function metal layer 115F′ and an initial gate electrode pattern 115P′. The gate dielectric layer 115D′ with the initial work-function metal layer 115F′ thereon may surround both the lower channel layers 110C of the lower channel structure 110 and the upper channel layers 120C of the upper channel structure 120. The initial gate electrode pattern 115P′ may be patterned to be formed on the initial work-function metal layer 115F′” ¶ [0065]) with the first epitaxial growth 112 and second epitaxial growth 122 (“the upper source/drain regions 122 grown from the upper channel structure 120 may have a smaller width than the lower source/drain regions 112 grown from the lower channel structure 110 (as shown in FIGS. 1A-1D).” ¶ [0064]).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify work function metal of BAEK et al. with the work function metal of YUN et al. in order to form a lower gate electrode for the lower nanosheet transistor for the purposes of cost-effectiveness, manufacturing simplicity and protection of a lower work-function metal layer (YUN et al. ¶ [0119]).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AKHEE SARKER-NAG whose telephone number is (703)756-4655. The examiner can normally be reached Monday -Friday 7:15 AM to 5:30 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, YARA J. GREEN can be reached on (571) 270-3035. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/AKHEE SARKER-NAG/Examiner, Art Unit 2893
/YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893
Prosecution Insights