DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I drawn to claims 1-17 in the reply filed on 01/23/2026 is acknowledged. Claims 18-20 directed to the non-elected group, are thereby withdrawn. Currently claims 1-20 are pending.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 11/28/2022 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner and made of record.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 10 is rejected under 35 U.S.C. 102(a)(2) as being anticipated by BAEK, Jaejik (US 20230343823 A1) “BAEK et al.”.
Regarding Independent Claim 10, BAEK et al. Fig. 1-11 discloses a semiconductor structure (“a multi-stack semiconductor device” ¶ [0026]) comprising:
a first field effect transistor (FET) (“a nanosheet stack 10 may include a lower channel structure 10L,” ¶ [0028]; “nanosheet transistor is also referred to with various different names such as multi-bridge channel FET (MBCFET)” ¶ [0003]) stacked over a second FET (“a nanosheet stack 10 may include …. upper channel structure 10U in this order on a substrate 105” ¶ [0028]), where the first FET is disposed in a stepped formation with respect to the second FET (Fig. 1B shows the stepped nanosheet);
a first epitaxial growth formed adjacent the first FET (“the lower source/drain region 170S may be epitaxially grown from the lower channel layers 110C” ¶ [0068]); and
a second epitaxial growth formed adjacent the FET (“upper source/drain region 180S may be epitaxially grown from the upper channel layers 120C” ¶ [0068]).
such that the second epitaxial growth 180S and 180D occupies a space greater (Fig. 11A shows 180S and 180D occupies a space greater than 170S and 170D) than a space of the first epitaxial growth 170S and 170 D.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5, 7-9, 11-14 and 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over BAEK, Jaejik (US 20230343823 A1) “BAEK et al.” in view of HE, MING (US 20230178440 A1) “HE et al.”.
Regarding Independent Claim 1, BAEK et al. Fig. 1-11 discloses a semiconductor structure (“a multi-stack semiconductor device” ¶ [0026]) comprising:
semiconductor layers of a first nanosheet stack (“a nanosheet stack 10 may include a lower channel structure 10L,” ¶ [0028]);
semiconductor layers of a second nanosheet stack formed over (“a nanosheet stack 10 may include …. upper channel structure 10U in this order on a substrate 105” ¶ [0028]) and having a stepped nanosheet formation with respect to the semiconductor layers of the first nanosheet stack (Fig. 1B shows the stepped nanosheet);
a first epitaxial growth formed adjacent the semiconductor layers of the first nanosheet stack (“the lower source/drain region 170S may be epitaxially grown from the lower channel layers 110C” ¶ [0068]); and
a second epitaxial growth formed adjacent the semiconductor layers of the second nanosheet stack (“upper source/drain region 180S may be epitaxially grown from the upper channel layers 120C” ¶ [0068]).
In the similar field of endeavor of structures or layer of semiconductor devices including a nanosheet transistor HE et al. Figs. discloses, wherein the second epitaxial growth (“upper source/drain regions 42_U” ¶ [0039]) has a stepped formation (Fig. 16A shows stepped formation of 42_U and 42_L) with respect to the first epitaxial growth (“lower source/drain regions 42_L may be formed” ¶ [0030]).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify epitaxial growth of BAEK et al. with the stepped epitaxial growth of HE et al. in order to manufacture an integrated circuit device including stacked transistors, such as a complementary field effect transistor (CFET) stack, was introduced to reduce an area thereof to close to one-half of the area of a corresponding non-stacked device (HE et al. ¶ [0003]).
Regarding Claim 2, BAEK et al. as modified by HE et al. discloses the limitations of claim 1. BAEK et al. Fig. 6, further discloses, wherein the second epitaxial growth (180S, 180D) has a volume greater (Fig. 6 shows 180S, 180D has greater volume than 170S, 170D) than a volume of the first epitaxial growth (170S, 170D).
Regarding Claim 3, BAEK et al. as modified by HE et al. discloses the limitations of claim 1. However, BAEK et al. does not discloses, wherein the first epitaxial growth is isolated from the second epitaxial growth by an oxide layer and a nitride cap.
In the similar field of endeavor of structures or layer of semiconductor devices including a nanosheet transistor HE et al. Figs. 1-18 discloses, wherein the first epitaxial growth 42_L is isolated from the second epitaxial growth 42_U by an oxide layer (“preliminary capping layers 43 may each be a silicon layer, and the silicon layer may be converted to a silicon oxide layer by an oxidation process” ¶ [0035]) and a nitride cap (“capping layers 44 may include a silicon oxide layer, a silicon oxynitride layer, a silicon nitride layer, a silicon germanium nitride layer or a germanium nitride layer” ¶ [0033]).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify epitaxial growth of BAEK et al. with the stepped epitaxial growth of HE et al. in order to manufacture an integrated circuit device including stacked transistors, such as a complementary field effect transistor (CFET) stack, was introduced to reduce an area thereof to close to one-half of the area of a corresponding non-stacked device (HE et al. ¶ [0003]).
Regarding Claim 4, BAEK et al. as modified by HE et al. discloses the limitations of claim 1. BAEK et al. Figs. 1-11, further discloses, wherein a first work function metal (WFM) surrounds the semiconductor layers of the first nanosheet stack and the semiconductor layers of the second nanosheet stack (“Each of the lower and upper gate metal patterns 220L, 220U may include a work-function metal layer and a conductor layer” ¶ [0088]).
Regarding Claim 5, BAEK et al. as modified by HE et al. discloses the limitations of claim 4. BAEK et al. Figs. 1-11, further discloses, wherein a second WFM is placed over and in direct contact with the first WFM (“Each of the lower and upper gate metal patterns may include a work-function metal layer and a conductor layer. The work-function metal layer may be formed of Ti, Ta or their compound such as TiN, TiAl, TiAlN, TaN, TiC, TaC, TiAlC, TaCN, TaSiN, and/or a combination thereof, not being limited thereto. The conductor layer may be formed of Cu, Al, W, Mo, Ru or their compound, not being limited thereto.” ¶ [0119]).
Regarding Claim 7, BAEK et al. as modified by HE et al. discloses the limitations of claim 4. BAEK et al. Figs. 1-11, further discloses, wherein inner spacers are disposed directly between the first WFM and the first epitaxial growth (“these source/drain regions are isolated from the sacrificial layers 110S and 120S by the inner spacers 165” ¶ [0071]).
Regarding Claim 8, BAEK et al. as modified by HE et al. discloses the limitations of claim 4. BAEK et al. Figs. 1-11, further discloses, wherein inner spacers are disposed directly between the first WFM and the second epitaxial growth (“these source/drain regions are isolated from the sacrificial layers 110S and 120S by the inner spacers 165” ¶ [0071]).
Regarding Claim 9, BAEK et al. as modified by HE et al. discloses the limitations of claim 1. However, BAEK et al. does not disclose, wherein inner spacers of the first epitaxial growth are vertically offset from inner spacers of the second epitaxial growth.
In the similar field of endeavor of structures or layer of semiconductor devices including a nanosheet transistor HE et al. Figs. 1-18 discloses, wherein inner spacers 24_L of the first epitaxial growth 42_L are vertically offset (Fig. 16A shows inner spacers 24_L are vertically offset from inner spacers 24_U) from inner spacers 24_U of the second epitaxial growth 42_U.
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify inner spacer of BAEK et al. with the inner spacer of HE et al. in order to manufacture an integrated circuit device including stacked transistors, such as a complementary field effect transistor (CFET) stack, was introduced to reduce an area thereof to close to one-half of the area of a corresponding non-stacked device (HE et al. ¶ [0003]).
Regarding Claim 11, BAEK et al. discloses the limitations of claim 10. However, BAEK et al. does not disclose, wherein the second epitaxial growth has a stepped formation with respect to the first epitaxial growth.
In the similar field of endeavor of structures or layer of semiconductor devices including a nanosheet transistor HE et al. Figs. discloses, wherein the second epitaxial growth (“upper source/drain regions 42_U” ¶ [0039]) has a stepped formation (Fig. 16A shows stepped formation of 42_U and 42_L) with respect to the first epitaxial growth (“lower source/drain regions 42_L may be formed” ¶ [0030]).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify epitaxial growth of BAEK et al. with the stepped epitaxial growth of HE et al. in order to manufacture an integrated circuit device including stacked transistors, such as a complementary field effect transistor (CFET) stack, was introduced to reduce an area thereof to close to one-half of the area of a corresponding non-stacked device (HE et al. ¶ [0003]).
Regarding Claim 12, BAEK et al. discloses the limitations of claim 10. However, BAEK et al. does not discloses, wherein the first epitaxial growth is isolated from the second epitaxial growth by an oxide layer and a nitride cap.
In the similar field of endeavor of structures or layer of semiconductor devices including a nanosheet transistor HE et al. Figs. 1-18 discloses, wherein the first epitaxial growth 42_L is isolated from the second epitaxial growth 42_U by an oxide layer (“preliminary capping layers 43 may each be a silicon layer, and the silicon layer may be converted to a silicon oxide layer by an oxidation process” ¶ [0035]) and a nitride cap (“capping layers 44 may include a silicon oxide layer, a silicon oxynitride layer, a silicon nitride layer, a silicon germanium nitride layer or a germanium nitride layer” ¶ [0033]).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify epitaxial growth of BAEK et al. with the stepped epitaxial growth of HE et al. in order to manufacture an integrated circuit device including stacked transistors, such as a complementary field effect transistor (CFET) stack, was introduced to reduce an area thereof to close to one-half of the area of a corresponding non-stacked device (HE et al. ¶ [0003]).
Regarding Claim 13, BAEK et al. discloses the limitations of claim 10. BAEK et al. Figs. 1-11, further discloses, a first work function metal (WFM) surrounds semiconductor layers of the first and second FETs (“Each of the lower and upper gate metal patterns 220L, 220U may include a work-function metal layer and a conductor layer” ¶ [0088]).
Regarding Claim 14, BAEK et al. as modified by HE et al. discloses the limitations of claim 13. BAEK et al. Figs. 1-11, further discloses, wherein a second WFM is placed over and in direct contact with the first WFM (“Each of the lower and upper gate metal patterns may include a work-function metal layer and a conductor layer. The work-function metal layer may be formed of Ti, Ta or their compound such as TiN, TiAl, TiAlN, TaN, TiC, TaC, TiAlC, TaCN, TaSiN, and/or a combination thereof, not being limited thereto. The conductor layer may be formed of Cu, Al, W, Mo, Ru or their compound, not being limited thereto.” ¶ [0119]).
Regarding Claim 16, BAEK et al. as modified by HE et al. discloses the limitations of claim 4. BAEK et al. Figs. 1-11, further discloses, wherein inner spacers are disposed directly between the first WFM and the first epitaxial growth, and between the first WFM and the second epitaxial growth (“these source/drain regions are isolated from the sacrificial layers 110S and 120S by the inner spacers 165” ¶ [0071]).
Regarding Claim 17, BAEK et al. discloses the limitations of claim 10. However, BAEK et al. does not disclose, wherein inner spacers of the first epitaxial growth are vertically offset from inner spacers of the second epitaxial growth.
In the similar field of endeavor of structures or layer of semiconductor devices including a nanosheet transistor HE et al. Figs. 1-18 discloses, wherein inner spacers 24_L of the first epitaxial growth 42_L are vertically offset (Fig. 16A shows inner spacers 24_L are vertically offset from inner spacers 24_U) from inner spacers 24_U of the second epitaxial growth 42_U.
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify inner spacer of BAEK et al. with the inner spacer of HE et al. in order to manufacture an integrated circuit device including stacked transistors, such as a complementary field effect transistor (CFET) stack, was introduced to reduce an area thereof to close to one-half of the area of a corresponding non-stacked device (HE et al. ¶ [0003]).
Claims 6 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over BAEK, Jaejik (US 20230343823 A1) “BAEK et al.” in view of HE, MING (US 20230178440 A1) “HE et al.” further in view of YUN, Seungchan (US 20230343824 A1) “YUN et al.”.
Regarding Claim 6, BAEK et al. as modified by HE et al. discloses the limitations of claim 4. However, BAEK et al. does not disclose, wherein the first WFM is horizontally aligned with the first and second epitaxial growths.
In the similar field of endeavor of structures or layer of semiconductor devices including a nanosheet transistor YUN et al. Figs. 1A-1D discloses, wherein the first WFM 115F is horizontally aligned (“an initial work-function metal layer 115F′ and an initial gate electrode pattern 115P′. The gate dielectric layer 115D′ with the initial work-function metal layer 115F′ thereon may surround both the lower channel layers 110C of the lower channel structure 110 and the upper channel layers 120C of the upper channel structure 120. The initial gate electrode pattern 115P′ may be patterned to be formed on the initial work-function metal layer 115F′” ¶ [0065]) with the first 112 and second epitaxial growths 122 (“the upper source/drain regions 122 grown from the upper channel structure 120 may have a smaller width than the lower source/drain regions 112 grown from the lower channel structure 110 (as shown in FIGS. 1A-1D).” ¶ [0064]).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify work function metal of BAEK et al. with the work function metal of YUN et al. in order to form a lower gate electrode for the lower nanosheet transistor for the purposes of cost-effectiveness, manufacturing simplicity and protection of a lower work-function metal layer (YUN et al. ¶ [0119]).
Regarding Claim 15, BAEK et al. as modified by HE et al. discloses the limitations of claim 13. However, BAEK et al. does not disclose, wherein the first WFM is horizontally aligned with the first and second epitaxial growths.
In the similar field of endeavor of structures or layer of semiconductor devices including a nanosheet transistor YUN et al. Figs. 1A-1D discloses, wherein the first WFM 115F is horizontally aligned (“an initial work-function metal layer 115F′ and an initial gate electrode pattern 115P′. The gate dielectric layer 115D′ with the initial work-function metal layer 115F′ thereon may surround both the lower channel layers 110C of the lower channel structure 110 and the upper channel layers 120C of the upper channel structure 120. The initial gate electrode pattern 115P′ may be patterned to be formed on the initial work-function metal layer 115F′” ¶ [0065]) with the first 112 and second epitaxial growths 122 (“the upper source/drain regions 122 grown from the upper channel structure 120 may have a smaller width than the lower source/drain regions 112 grown from the lower channel structure 110 (as shown in FIGS. 1A-1D).” ¶ [0064]).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify work function metal of BAEK et al. with the work function metal of YUN et al. in order to form a lower gate electrode for the lower nanosheet transistor for the purposes of cost-effectiveness, manufacturing simplicity and protection of a lower work-function metal layer (YUN et al. ¶ [0119]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AKHEE SARKER-NAG whose telephone number is (703)756-4655. The examiner can normally be reached Monday -Friday 7:15 AM to 5:30 PM.
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/AKHEE SARKER-NAG/Examiner, Art Unit 2893
/YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893