DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 12/2/2025 has been entered.
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed in Finnish Patent Application No. 20205316, filed on 03/30/2020.
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Response to Amendment
Applicant's amendments on 11/5/2025 have been reviewed and entered. Claims 1-3, 6, 15-16, and 19-20 have been amended by the Applicant. Claims 1-20 remain for examination.
Claim Objections
Claims 1 and 15-16 are objected to because of the following informalities:
Regarding claim 1, it is recited on lines 13-14 that “… the semiconductor layer is implemented as a silicon layer, … “. The term “implemented” makes this limitation unclear. Therefore, this phrase should be changed to “… the semiconductor layer is a silicon layer, …“.
Regarding claim 15 (Examiner notes that even though claim 15 is written as an apparatus claim, claim 15 mainly describes a semiconductor structure and passivation of the semiconductor structure, rather than an apparatus.),
on line 7, “the oxide layer to be refined” should be changes to “the oxide layer is refined”.
it is recited on lines 14-15 that “… the semiconductor layer is implemented as a silicon layer, … “. The term “implemented” makes this limitation unclear. Therefore, this phrase should be changed to “… the semiconductor layer is a silicon layer, …“.
Regarding claim 16,
on line 10, the phrase “wherein the structure is to passivated“ is grammatically incorrect and seems to be misplaced. It is recommended that this phrase is changed to “wherein the sample will be passivated” and placed in line 5 after “… holding a sample in the vacuum chamber”.
it is recited on lines 22-24 that “… the semiconductor layer is implemented as a silicon layer, … “. The term “implemented” makes this limitation unclear. Therefore, this phrase should be changed to “… the semiconductor layer is a silicon layer, …“.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Regarding claim 1, on lines 9-10 it is recited that “… the temperature range, ΔT, extending from 20 degrees Celsius (°C) to 480° C; …”. The disclosure does not support this temperature range, as the ranges provided in the Specification document only includes ranges from 20° C to 800° C, 50° C to 750° C, or from 80° C to 700° C, or from 100° C to 650° C, or from 130° C to 600° C, or from 160° C to 550° C, or from 180° C to 520° C, or from 200° C to 500° C, or from 220° C to 480° C, or from 240° C to 460°C, or from 260° C to 440° C, or from 280° C to 420° C, or from 300° C to 400° C, or from 320° C to 380° C ([0026]). Therefore, the range extending from 20° C to 480° C presents a new subject matter not described in the Specification. For the purpose of examination, the temperature range is interpreted to be “from 20 degrees Celsius (°C) to 480° C” as phrased in the claim.
Regarding claims 2-14, these claims are also rejected because each of these claims, directly or indirectly, depends on claim 1.
Regarding claim 15, on lines 10-11 it is recited that “… the temperature range, ΔT, extending from 20 degrees Celsius (°C) to 480° C …”. The disclosure does not support this claimed temperature range, as the ranges provided in the Specification document only includes ranges from 20° C to 800° C, 50° C to 750° C, or from 80° C to 700° C, or from 100° C to 650° C, or from 130° C to 600° C, or from 160° C to 550° C, or from 180° C to 520° C, or from 200° C to 500° C, or from 220° C to 480° C, or from 240° C to 460°C, or from 260° C to 440° C, or from 280° C to 420° C, or from 300° C to 400° C, or from 320° C to 380° C ([0026]). Therefore, the range extending from 20° C to 480° C presents a new subject matter not described in the Specification. For the purpose of examination, the temperature range is interpreted to be “from 20 degrees Celsius (°C) to 480° C” as phrased in the claim.
Regarding claims 19-20, claims 19-20 are also rejected because these depend on claim 15.
Regarding claim 16, on lines 17-18 it is recited that “… passivation temperature range, ΔT, extending from 20 degrees Celsius (°C) to 480° C …”. The disclosure does not support this passivation temperature range, as the ranges provided in the Specification document only includes ranges from 20° C to 800° C, 50° C to 750° C, or from 80° C to 700° C, or from 100° C to 650° C, or from 130° C to 600° C, or from 160° C to 550° C, or from 180° C to 520° C, or from 200° C to 500° C, or from 220° C to 480° C, or from 240° C to 460°C, or from 260° C to 440° C, or from 280° C to 420° C, or from 300° C to 400° C, or from 320° C to 380° C ([0026]). Therefore, the range extending from 20° C to 480° C presents a new subject matter not described in the Specification. For the purpose of examination, the passivation temperature range is interpreted to be “from 20 degrees Celsius (°C) to 480° C” as phrased in the claim.
Regarding claims 17-18, these claims are also rejected because each of these claims depend on claim 16.
Claims 3 and 20 are further rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 3, which is dependent on claim 1, some of the temperature ranges extend beyond the temperature range disclosed in claim 1 (“20 degrees Celsius (°C) to 480° C”). Therefore, it is unclear what is intended with the ranges extended beyond. For the purpose of examination, the claim 3 is interpreted as “… temperature range, ΔT, extends from at least one of
220 °C to 480 °C,
240 °C to 460 °C,
260 °C to 440 °C,
280 °C to 420 °C,
300°C to 400 °C, and
320 °C to 380 °C.”
Regarding claim 20, which is dependent on claim 15, some of the temperature ranges extend beyond the temperature range disclosed in claim 15 (“20 degrees Celsius (°C) to 480° C”). Therefore, it is unclear what is intended with the ranges extended beyond. For the purpose of examination, the claim 20 is interpreted as “… temperature range, ΔT, extends from at least one of
220 °C to 480 °C,
240 °C to 460 °C,
260 °C to 440 °C,
280 °C to 420 °C,
300°C to 400 °C, and
320 °C to 380 °C.”
Allowable Subject Matter
Claims 1-20 are rejected under 35 U.S.C. 112 and claims 1 and 15-16 are further objected due to minor informalities as detailed above. Claim 1-20 would be otherwise allowable if rewritten to overcome all 35 U.S.C. 112 rejections and claim objections.
Regarding claims 1-14, independent claim 1, now disclosing the limitation that “the passivation involves the formation of one or more protective oxide layers, whereby a surface of semiconductor layer is rendered more inert and a density of defect states at an interface between the semiconductor layer and the oxide layer is lowered.” overcomes the 35 U.S.C. 102 rejection based on Tokuhara (US 2019/0081131 A1). In terms of closest prior art, ss detailed in the Final Office action, Tokuhara teaches all the limitations of claim 1 except the limitation recited above. Further prior art search identified another prior art Laukkanen (WO 2018234620 A1, [0029]: annealing operation 350 on a semiconductor structure comprising an oxide layer on a semiconductor layer (Figs. 2-3)), which also teaches all the limitations of claim 1, except the limitation recited above. Accordingly, independent claim 1 and claims 2-14 which depend on claim 1 would be allowable if the claim objections and 35 U.S.C 112 rejections are overcome.
Regarding claims 15 and 19-20, independent claim 15, now also disclosing the limitation that “the passivation involves the formation of one or more protective oxide layers, whereby a surface of semiconductor layer is rendered more inert and a density of defect states at an interface between the semiconductor layer and the oxide layer is lowered.” overcomes the 35 U.S.C. 102 rejection based on Tokuhara (US 2019/0081131 A1). In terms of closest prior art, as detailed in the Final Office action, Tokuhara teaches all the limitations of claim 1 except the limitation recited above. Further prior art search identified another prior art Laukkanen (WO 2018234620 A1, [0029]: annealing operation 350 on a semiconductor structure comprising an oxide layer on a semiconductor layer (Figs. 2-3)) which also teaches all the limitations of claim 15, except the limitation recited above. Accordingly, independent claim 15 and claims 19-20 which depend on claim 15 would be allowable if the claim objections and 35 U.S.C 112 rejections are overcome.
Regarding claims 16-18, independent claim 16, now also disclosing the limitation that “the passivation involves the formation of one or more protective oxide layers, whereby a surface of semiconductor layer is rendered more inert and a density of defect states at an interface between the semiconductor layer and the oxide layer is lowered.” overcomes the 35 U.S.C. 102 rejection based on Tsun (US 2014/0273533 A1) in view of Tokuhara (US 2019/0081131 A1). In terms of closest prior art, as detailed in the Final Office action, Tsun and Tokuhara teach all the limitations of claim 1 except the limitation recited above. Further prior art search identified another prior art Laukkanen (WO 2018234620 A1, [0029]: annealing operation 350 on a semiconductor structure comprising an oxide layer on a semiconductor layer (Figs. 2-3)) which can also be combined with Tsun to teach all the limitations of claim 16, except the limitation recited above. Accordingly, independent claim 16 and claims 17-18 which depend on claim 16 would be allowable if the claim objections and 35 U.S.C 112 rejections are overcome.
Response to Arguments
It has been acknowledged that the applicant amended claims 1-3, 6, 15-16, and 19-20 per response dated on 12/2/2025. Applicant's arguments with respect to claims have been fully considered. The Examiner agrees with the Applicant on that the amendments to independent claims 1, 15 and 16 overcame all claim rejections made previously based on the prior art Tokuhara (US 2019/0081131 A1) for claims 1 and 15 and Tsun (US 2014/0273533 A1) and Tokuhara for claim 16. However, claims 1, 15 and 16 are now rejected under 35 U.S.C. 112(a) as detailed in the office action above. Therefore, all claims remain rejected in the current application. Claims 3 and 20 are further rejected under 35 U.S.C. 112 (b) as again detailed above in the office action. There are also objections to independent claims 1, 15, and 16 due to phrasing issues.
For the purpose of compact prosecution, the Examiner recommends thoroughly reviewing the claim language, particularly in claims 15 and 16, and amending the claims to overcome the objections and 35 U.S.C. 112 rejections.
The Examiner is available for an interview at Applicant’s convenience if the Applicant would like to discuss the application.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ILKER OZDEN whose telephone number is (703)756-5775. The examiner can normally be reached Monday - Friday 8:30am-5:30pm.
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/ILKER NMN OZDEN/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812