DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Status of the application
This office Action is in response to Applicant's Application filled on 10/27/2025. Claims 1-20 are pending for this examination.
Priority
Acknowledgment is made of applicant's claim for foreign priority under 35 U.S.C. 119(a)-(d). The certified copy has been filed on 10/14/2022.
Oath/Declaration
The oath or declaration filed on 10/14/2022 is acceptable.
Election/Restrictions
Applicant’s election, with traverse, group I, Species V: claims 1-5, 11-12 and 17-18, in the “Response to Election / Restriction Filed” filed on 10/27/2025 is acknowledged. The traversal is on the ground(s) that, Kim does not disclose “wherein the first active layer is in contact with the second active layer through a first via hole structure” the special technical feature. Examiner like to note that, first active layer is in electrical contact with the second active layer through a first via hole structure. Therefore, this technical feature is not a special technical feature. In addition, KO (US 2023/0061581 A1; hereafter KO) discloses the first active layer (Fig [6], first active layer 620, Para [0141]) is in contact with the second active layer (Fig [6], second active layer 650, Para [ 0163]) through a first via hole structure (Fig [6], first hole H1, Para [ 0182]). Therefore, restriction requirement is still deemed proper and is therefore made FINAL.
This office action considers claims 1-20 are thus pending for prosecution, of which, claims 6-10, 13-16 and 19-20 are withdrawn, and claims 1-5, 11-12 and 17-18 are examined on their merits.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2 and 12 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by KO (US 2023/0061581 A1; hereafter KO).
PNG
media_image1.png
594
740
media_image1.png
Greyscale
Regarding claim 1. KO discloses a thin film transistor (Fig [6]), comprising:
a base substrate (Fig [6], substrate 600, Para [ 0134]); and
a first active layer (Fig [6], first active layer 620, Para [0141]),
a first insulating layer (Fig [6], first insulating film 640, Para [ 0160]) and a second active layer (Fig [6], second active layer 650, Para [ 0163]), which are sequentially arranged on the base substrate (Fig [6], substrate 600, Para [ 0134]);
wherein the first active layer (Fig [6], first active layer 620, Para [0141]) is in contact with the second active layer (Fig [6], second active layer 650, Para [ 0163]) through a first via hole structure (Fig [6], first hole H1, Para [ 0182]) located in the first insulating layer (Fig [6], first insulating film 640, Para [ 0160]), and non-contacted portions of the first active layer ( Fig [6], first active layer 620, Para [0141]) and the second active layer (Fig [6], second active layer 650, Para [ 0163]) are separated by the first insulating layer ( Fig [6], first insulating film 640, Para [ 0160]).
Regarding claim 2. KO discloses the thin film transistor according to claim 1, KO further discloses further comprising a source-drain electrode layer (electrode 680/690, para [ 0186]), wherein the source-drain electrode layer (electrode 680/690, para [ 0186]) is electrically connected with the first active layer (Fig [6], first active layer 620, Para [0141]) and the second active layer (Fig [6], second active layer 650, Para [ 0163]).
Regarding claim 12. KO discloses an array substrate, KO further discloses comprising the thin film transistor according to claim 1 (Para [ 0307]).
Claim Rejection- 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 11 and 17-18 are rejected under 35 U.S.C. 103 as being unpatentable over KO (US 2023/0061581 A1; hereafter KO) as applied claims above and further in view of LOU et al (US 2019/0165004 A1; hereafter LOU).
Regarding claim 11. KO discloses the thin film transistor according to claim 1, But, KO does not disclose explicitly wherein the first active layer comprises a first sub-active layer and a second sub-active layer which are stacked, and/or the second active layer comprises a third sub-active layer and a fourth sub-active layer which are stacked.
In a similar field of endeavor, LOU discloses wherein the first active layer comprises a first sub-active layer and a second sub-active layer which are stacked (Fig 19, stacked active layer [ 301/302], Para [ 0068]), and/or the second active layer comprises a third sub-active layer and a fourth sub-active layer which are stacked (Fig 19, stacked active layer [ 301/302], Para [ 0068]).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine KO in light of LOU teaching “wherein the first active layer comprises a first sub-active layer and a second sub-active layer which are stacked (Fig 19, stacked active layer [ 301/302], Para [ 0068]), and/or the second active layer comprises a third sub-active layer and a fourth sub-active layer which are stacked (Fig 19, stacked active layer [ 301/302], Para [ 0068])” for further advantage such as to provide high carrier mobility, low preparation temperature and high uniformity of large area.
Regarding claim 17. KO discloses the thin film transistor according to claim 2, But, KO does not disclose explicitly wherein the first active layer comprises a first sub-active layer and a second sub-active layer which are stacked, and/or the second active layer comprises a third sub-active layer and a fourth sub-active layer which are stacked.
In a similar field of endeavor, LOU discloses wherein the first active layer comprises a first sub-active layer and a second sub-active layer which are stacked (Fig 19, stacked active layer [ 301/302], Para [ 0068]), and/or the second active layer comprises a third sub-active layer and a fourth sub-active layer which are stacked (Fig 19, stacked active layer [ 301/302], Para [ 0068]).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine KO in light of LOU teaching “wherein the first active layer comprises a first sub-active layer and a second sub-active layer which are stacked (Fig 19, stacked active layer [ 301/302], Para [ 0068]), and/or the second active layer comprises a third sub-active layer and a fourth sub-active layer which are stacked (Fig 19, stacked active layer [ 301/302], Para [ 0068])” for further advantage such as to provide high carrier mobility, low preparation temperature and high uniformity of large area.
Regarding claim 18. KO discloses the thin film transistor according to claim 3, But, KO does not disclose explicitly wherein the first active layer comprises a first sub-active layer and a second sub-active layer which are stacked, and/or the second active layer comprises a third sub-active layer and a fourth sub-active layer which are stacked.
In a similar field of endeavor, LOU discloses wherein the first active layer comprises a first sub-active layer and a second sub-active layer which are stacked (Fig 19, stacked active layer [ 301/302], Para [ 0068]), and/or the second active layer comprises a third sub-active layer and a fourth sub-active layer which are stacked (Fig 19, stacked active layer [ 301/302], Para [ 0068]).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine KO in light of LOU teaching “wherein the first active layer comprises a first sub-active layer and a second sub-active layer which are stacked (Fig 19, stacked active layer [ 301/302], Para [ 0068]), and/or the second active layer comprises a third sub-active layer and a fourth sub-active layer which are stacked (Fig 19, stacked active layer [ 301/302], Para [ 0068])” for further advantage such as to provide high carrier mobility, low preparation temperature and high uniformity of large area.
Allowable Subject Matter
Claims 3-5 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is the Examiner's Reasons for Allowance:
The prior art fails to disclose and would not have rendered obvious:
Regarding claim 3. wherein the source-drain electrode layer is electrically connected with the second active layer through a second via hole structure, an orthographic projection of the first via hole structure on the base substrate and an orthographic projection of the second via hole structure on the base substrate are at least partially overlapped, and at least a part of the source-drain electrode layer extends into the first via hole structure.
Claims 4-5 is objected based on the dependency of claim 3.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOIN M RAHMAN whose telephone number is (571)272-5002. The examiner can normally be reached 8:30-5:00pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at 571-272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/MOIN M RAHMAN/Primary Examiner, Art Unit 2898