DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 12/30/2025 has been entered.
Information Disclosure Statement
The Information Disclosure Statement (IDS) submitted on 12/03/2025 is in compliance with provisions of 37 CFR 1.97. Accordingly, the information disclosure is being considered by the Examiner.
Response to Amendment
The amendment with respect to claim 1 filed on 12/30/2025 has been fully considered for examination based on its merits. The previously presented claims 2-12 have been considered. The new claims 13 and 14 have been considered based their merits.
Response to Arguments
Applicant’s arguments, see Remarks, page 6-7, filed 12/30/2025, with respect to the rejection(s) of claim(s) 1 under 35 U.S.C. 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of SUNG.
Regarding independent claim 1. Applicant argues that YONEDA as modified by TOMURA fails to disclose or suggest the amended limitation, “the receiving portion being recessed upward and including metal powder of the electrode and the metal pattern generated during bonding of the electrode and the metal pattern.” Examiner agrees that the arguments are persuasive and therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made as mentioned in the above paragraph. For instance, the prior-art of SUNG teaches a semiconductor device (Fig1. 1, 12, CMP pad dresser, [0014-0016]) comprising: the receiving portion being recessed upward (Fig. 1, 14, indicator substrate) and including metal powder (Fig. 1, 16, aggressive superabrasive particles) of the electrode (Fig. 1, 12, CMP pad dresser, [0046]) and the metal pattern (Fig. 2, first marking pattern identifies a plurality of working superabrasive particles, [0044]) generated during bonding of the electrode and the metal pattern (Fig. 1, a CMP pad dresser, 12 is pressed into an indicator substrate, 14 with a fixed load, [0046]).
Regarding claim(s) 2-14. The dependent claims 2-14 follow similar arguments as claim 1, upon further consideration, a new-grounds of rejection is made based on the prior-art mentioned above.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yutaka Yoneda et al, (hereinafter YONEDA), US 20180151533 A1, in view of Chien-Min Sung, (hereinafter SUNG), US 20150072595 A1.
Regarding Claim 1, YONEDA teaches in Figures 2(A-C), a semiconductor device (100, power semiconductor device) comprising:
an insulating substrate (5, ceramic board) including an insulating layer (52, ceramic base member) and a metal pattern (52a/52b, conductive patterns) disposed on the insulating layer (52, ceramic base member); and
an electrode (3, electrode terminal) bonded on the metal pattern (52a, conductive patterns), wherein
the electrode (3, electrode terminal) includes a receiving portion (annotated Figure 8A) in a portion inward of a peripheral portion of a bonded surface (Fig. 3A, 3j, surface) being a surface of the electrode (3, electrode terminal) bonded on the metal pattern (52a, conductive patterns), and
the peripheral portion of the bonded surface (Fig. 3A, 3j, surface) of the electrode (3, electrode terminal) is bonded on the metal pattern (52a, conductive patterns).
YONEDA does not explicitly disclose a semiconductor device comprising:
the receiving portion being recessed upward and including metal powder of the electrode and the metal pattern generated during bonding of the electrode and the metal pattern.
SUNG teaches disclose a semiconductor device (Fig1. 1, 12, CMP pad dresser, [0014-0016]) comprising:
the receiving portion being recessed upward (Fig. 1, 14, indicator substrate) and including metal powder (Fig. 1, 16, aggressive superabrasive particles) of the electrode (Fig. 1, 12, CMP pad dresser, [0046]) and the metal pattern (Fig. 2, first marking pattern identifies a plurality of working superabrasive particles, [0044]) generated during bonding of the electrode and the metal pattern (Fig. 1, a CMP pad dresser, 12 is pressed into an indicator substrate, 14 with a fixed load, [0046]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified YONEDA to incorporate the teachings of SUNG, such that a semiconductor device comprising: the receiving portion being recessed upward and including metal powder of the electrode and the metal pattern generated during bonding of the electrode and the metal pattern, so that a marking pattern cut into the indicator substrate by the portion of the plurality of superabrasive particles, where the marking pattern identifies a plurality of working superabrasive particles from among the plurality of superabrasive particles, thus from a marking pattern profile, the cutting effectiveness of a CMP pad dresser can be determined (SUNG, [0011]).
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Regarding Claim 2, YONEDA as modified by SUNG teaches the semiconductor device according to claim 1.
YONEDA further teaches in Figures 2(A-C), the semiconductor device (100, power semiconductor device) according to claim 1, wherein
the receiving portion (annotated Figure 8A) is a recess (Fig. 8A, 3a, recess) formed in a central portion (Fig. 8A, 52c, protrusion) of the bonded surface (Fig. 3A, 3j, surface) of the electrode (3, electrode terminal).
Regarding Claim 3, YONEDA as modified by SUNG teaches the semiconductor device according to claim 1.
YONEDA further teaches in Figures 2(A-C), the semiconductor device (100, power semiconductor device), wherein
the receiving portion (annotated Figure 8A) is a groove (annotated Figure 8A) formed along the peripheral portion of the bonded surface (Fig. 3A, 3j, surface) of the electrode (3, electrode terminal).
Regarding Claim 4, YONEDA as modified by SUNG teaches the semiconductor device according to claim 1.
YONEDA further teaches in Figures 2(A-C), the semiconductor device (100, power semiconductor device) according to claim l, wherein
the metal pattern (52a, conductive patterns) includes, in a portion (annotated Figure 8A) opposing the bonded surface (Fig. 3A, 3j, surface) of the electrode (3, electrode terminal), a depression recessed downward (annotated Figure 8A).
Regarding Claim 5, YONEDA as modified by SUNG teaches the semiconductor device according to claim 4.
YONEDA further teaches in Figures 2(A-C), the semiconductor device (100, power semiconductor device), wherein
the metal pattern (52a, conductive patterns) includes, in the depression (annotated Figure 8A) thereof, a projection protruding upward (Fig. 8A, 52c, protrusion) and received in the receiving portion (annotated Figure 8A) of the electrode (3, electrode terminal).
Regarding Claim 6, YONEDA as modified by SUNG teaches the semiconductor device according to claim 1.
YONEDA further teaches in Figures 2(A-C), the semiconductor device (100, power semiconductor device), wherein
the metal pattern (52a, conductive patterns) includes a capture portion (annotated Figure 8A) thereof in a portion opposing the peripheral portion of the bonded surface (Fig. 3A, 3j, surface) of the electrode (3, electrode terminal), the capture portion (annotated Figure 8A) thereof being made of a different material ([0025]) from the metal pattern (52a, conductive patterns) and capable of capturing the metal powder (crystal grains, [0031], [0035]).
Regarding Claim 7, YONEDA as modified by SUNG teaches the semiconductor device according to claim 1.
YONEDA further teaches in Figures 12A-12B, the semiconductor device (101, power semiconductor device), further comprising:
a semiconductor element (1, power semiconductors element) bonded on the metal pattern (2, surface electrode), wherein
the semiconductor element (1, power semiconductors element) comprises a wide bandgap semiconductor ([0049]).
Regarding Claim 8, YONEDA as modified by SUNG teaches a power converter according to claim 1.
YONEDA further teaches in Figures 12A-12B, a power converter Fig. 12A, power semiconductor element, 1, a converter, [0049]) comprising:
a main conversion circuit (circuit-face side, [0023]) to convert input power for output, the main conversion circuit (circuit-face side, [0023]) including the semiconductor device (100, power semiconductor device);
a drive circuit (external circuit, [0024]) to output, to the semiconductor device (100, power semiconductor device),
a drive signal (electrically connected, [0024]) to drive the semiconductor device (100, power semiconductor device); and a control circuit (another circuit, [0024]) to output, to the drive circuit (external circuit, [0024]), a control signal (electrically connected, [0024], [0034]) to control the drive circuit (external circuit, [0024]).
Regarding Claim 9, YONEDA as modified by SUNG teaches a moving vehicle according to claim 8.
YONEDA further teaches in Figures 12A-12B, a moving vehicle (power semiconductor element for allowable current to flow, [0024], [0034-0036], [0051]) comprising the power converter (Fig. 12A, power semiconductor element, 1, a converter, [0049]) mounted thereon.
Regarding Claim 10, YONEDA as modified by SUNG teaches a semiconductor device manufacturing method according to claim 1.
YONEDA further teaches in Figures 2(A-C), the semiconductor device (100, power semiconductor device) manufacturing method ([0028]) of manufacturing the semiconductor device (100, power semiconductor device), the semiconductor device (100, power semiconductor device) manufacturing method comprising:
(a) preparing the insulating substrate (5, ceramic board) and the electrode (3, electrode terminal); and
(b) bringing the peripheral portion of the bonded surface (Fig. 3A, 3j, surface) of the electrode (3, electrode terminal) into contact with the metal pattern (52a, conductive patterns), and ultrasonically bonding (Fig. 2A, 50, ultrasonic horn) the peripheral portion of the bonded surface (Fig. 3A, 3j, surface) of the electrode (3, electrode terminal) on the metal pattern (52a, conductive patterns) while applying a load (pressure and the vibration, [0030]) using an ultrasonic bonding tool (Fig. 2A, 50, ultrasonic horn).
Regarding Claim 11, YONEDA as modified by SUNG teaches the semiconductor device manufacturing method according to claim 10.
YONEDA further teaches in Figures 2(A-C), the semiconductor device (100, power semiconductor device) manufacturing method ([0028]), wherein
in step (a), the receiving portion (annotated Figure 8A) is a groove (annotated Figure 8A) formed along the peripheral portion of the bonded surface (Fig. 3A, 3j, surface) of the electrode (3, electrode terminal), and the electrode (3, electrode terminal) includes, in a portion inward of the groove (annotated Figure 8A), a protrusion protruding downward (Fig. 8A, 52c, protrusion).
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over YONEDA, in view of SUNG, and further in view of Yoshihiro Tomura et al, (hereinafter TOMURA), US 5545589 A.
Regarding Claim 12, YONEDA as modified by SUNG teaches the semiconductor device according to claim 1.
YONEDA as modified by SUNG does not explicitly disclose the semiconductor device, wherein
the receiving portion from the bonded surface by way of the metal powder.
TOMURA teaches in Figures 3A-5B, the semiconductor device ([Col. 3, Lines 55-65]), wherein
the receiving portion (Figs. 3B/5A, 4, rugged side, [Col. 4, Lines 45-55]) is spaced (annotated Figure 5A) from the bonded surface (Fig 5A, 8, top surface of the terminal electrode) by way of the metal powder (Fig. 5A, conductive particles included in the anisotropic conductive material, 10, [Col. 9, Lines 25-35]).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have YONEDA as modified by SUNG to incorporate the teachings of TOMURA, such that the semiconductor device, wherein the receiving portion from the bonded surface by way of the metal powder, so that the anisotropic conductive material 10, are pressed against the bump 3, to be bonded with each other, and are forcedly entered into the surface of the terminal electrode 8, thereby achieving electrical connection between the bump 3, and the terminal electrode 8 (TOMURA, [Col. 9, Lines 25-35]).
Claim(s) 13-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over YONEDA, in view of SUNG, and further in view of Tetsuya Takahashi et al, (hereinafter TAKAHASHI), US 20130255878 A1.
Regarding Claim 13, YONEDA as modified by SUNG teaches the semiconductor device according to claim 1.
YONEDA as modified by SUNG does not explicitly disclose the semiconductor device, wherein the receiving portion is a groove that surrounds a central portion of the electrode.
TAKAHASHI teaches the semiconductor device (Fig. 1A, 12, printed circuit board), wherein
the receiving portion (Fig. 5D, 46, cavity) is a groove (Fig. 5D, 46D, groove formed in a square frame shape, [0065]) that surrounds a central portion (Fig. 5D, 46F, groove surrounding the central flat face, 46F, [0065]) of the electrode (Fig. 5D, 14, mounting stage is made from ceramic set, [0080]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have YONEDA as modified by SUNG to incorporate the teachings of TAKAHASHI, such that the semiconductor device, wherein the receiving portion is a groove that surrounds a central portion of the electrode, so that the groove, 46D acts as a portion into which the remaining material that generated during the processing enters (TAKAHASHI, [0065-0066]).
Regarding Claim 14, YONEDA as modified by SUNG teaches the semiconductor device according to claim 1.
YONEDA as modified by SUNG does not explicitly disclose the semiconductor device, wherein the receiving portion is a groove that completely surrounds a central portion of the electrode.
TAKAHASHI teaches the semiconductor device (Fig. 1A, 12, printed circuit board), wherein
the receiving portion (Fig. 5D, 46, cavity) is a groove (Fig. 5D, 46D, groove formed in a square frame shape, [0065]) that completely surrounds a central portion (Fig. 5D, 46F, groove surrounding the central flat face, 46F, [0065]) of the electrode (Fig. 5D, 14, mounting stage is made from ceramic set, [0080]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have YONEDA as modified by SUNG to incorporate the teachings of TAKAHASHI, such that the semiconductor device, wherein the receiving portion is a groove that completely surrounds a central portion of the electrode, so that the groove, 46D acts as a portion into which the remaining material that generated during the processing enters (TAKAHASHI, [0065-0066]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 2001007780 A1 – Figures 17(a) and 17(b)
STATEMENT OF RELEVANCE – A closed-loop groove is preferable formed in the lower surface of the die pad at the peripheral portion that surrounds the central portion, [0027].
US 2020194197 A1 – Figures 3A and 3B
STATEMENT OF RELEVANCE – The powder, P1 may be scraped from case, 2 if excessive force is applied to movable component 3, [0042].
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/SESHA SAIRAMAN SRINIVASAN/ Examiner, Art Unit 2812
/CHRISTINE S. KIM/ Supervisory Patent Examiner, Art Unit 2812