Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Amendment filed on 3/18/2026 has been entered. Claims 1, 11 are amended. Claims 1 – 20 are pending in the present application.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1 – 2, 5 – 9, 11 – 12, 15 – 20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Jeong ( Pub. No. US 20070040175 A1 ), hereinafter Jeong.
PNG
media_image1.png
888
1430
media_image1.png
Greyscale
Regarding Independent Claim 1 (Currently Amended), Jeong teaches a thin film transistor, comprising:
a crystalline active pattern ( Jeong, FIG. 4, 43, [0059], polysilicon layer 43 ), wherein the crystalline active pattern ( Jeong, FIG. 4, 43, [0059], polysilicon layer 43 ) comprises:
a channel ( Jeong, FIG. 4, 43; [0059], polysilicon layer 43 );
two contact portions ( Jeong, FIG. 4, left part and right part of 43, where contacts with 48a and 48b; [0059], polysilicon layer 43; [0061], Source electrode 48a and drain electrode 48b ), the two contact portions ( Jeong, FIG. 4, left part and right part of 43, where contacts with 48a and 48b; [0059], polysilicon layer 43; [0061], Source electrode 48a and drain electrode 48b ) being connected to opposite two sides of the channel ( Jeong, FIG. 4, 43; [0059], polysilicon layer 43 ) in a direction intersecting a thickness direction of the crystalline active pattern ( Jeong, FIG. 4, 43, [0059], polysilicon layer 43 ); and
at least one groove ( Jeong, FIG. 1, 14, or the contact between 12 and 18a / 18b; [0007], polysilicon layer 12 having protrusions 14 formed at grain boundaries; [0008], source and drain electrodes 18a and 18b ) formed in at least one of the two contact portions ( Jeong, FIG. 4, left part and right part of 43, where contacts with 48a and 48b; [0059], polysilicon layer 43; [0061], Source electrode 48a and drain electrode 48b ) by extending through ( Jeong, FIG. 1, protrusions 14; [0004], To form the polysilicon layer, intrinsic amorphous silicon may be deposited on an insulating substrate to a thickness of 40 nm to 200 nm by a predetermined method, i.e., a plasma chemical vapor deposition or a low pressure CVD (LPCVD) method, and then crystallized to form the polysilicon layer; [0010], The protrusions 14 may have a height of about 40 nm to about 200 nm, which may be almost equal to a height of the amorphous silicon layer ) the at least one of the two contact portions ( Jeong, FIG. 4, left part and right part of 43, where contacts with 48a and 48b ) along the thickness direction of the crystalline active pattern ( Jeong, FIG. 4, 43, [0059], polysilicon layer 43 ) to expose a surface of a layer in contact with and below the contact portion ( Jeong, [0010], “ The protrusions 14 may have a height of about 40 nm to about 200 nm, which may be almost equal to a height of the amorphous silicon layer. ”. Therefore, when the height of protrusions 14 is equal to a height of the amorphous silicon layer ( which is then crystallized to form the polysilicon layer ), the layer in contact with and below the contact portion is exposed its surface. );
a source electrode and a drain electrode ( Jeong, FIG. 4, 48a, 48b; [0061], Source electrode 48a and drain electrode 48b ) connected to the two contact portions ( Jeong, FIG. 4, left part and right part of 43, where contacts with 48a and 48b; [0059], polysilicon layer 43; [0061], Source electrode 48a and drain electrode 48b ), respectively; and
a heat-retaining layer ( Jeong, FIG. 4, 44; [0059], heat retaining layer 44 ), the heat-retaining layer ( Jeong, FIG. 4, 44; [0059], heat retaining layer 44 ) being in contact with the channel ( Jeong, FIG. 4, 43; [0059], polysilicon layer 43 );
wherein a depth of the groove ( Jeong, FIG. 1, 14, or the contact between 12 and 18a / 18b; [0007], polysilicon layer 12 having protrusions 14 formed at grain boundaries; [0008], source and drain electrodes 18a and 18b; [0010], The protrusions 14 may have a height of about 40 nm to about 200 nm, which may be almost equal to a height of the amorphous silicon layer ) is equal to a thickness of the crystalline active pattern ( Jeong, FIG. 5, 52, 53, 52 thicker than 53; [0063], polysilicon layer 52, SiO2 layer 53 may have a thickness of about 50 nm to 500 nm ); and
wherein at least one of the source electrode and the drain electrode ( Jeong, FIG. 4, 48a, 48b ) is configured to extend along the at least one groove onto the exposed surface ( Jeong, FIG. 1, 14, or the contact between 12 and 18a / 18b ).
Regarding Claim 2 (Original), Jeong teaches the thin film transistor as claimed in claim 1, on which this claim is dependent, Jeong further teaches:
wherein the crystalline active pattern ( Jeong, FIG. 4, 43, [0059], polysilicon layer 43 ) further comprises two transition portions ( Jeong, [0041], The semiconductor layer may include a lightly doped drain (LDD) layer (not shown) between an active channel region (not shown) and source and drain regions (not shown). The semiconductor layer may be a polysilicon layer 23 ), one of the transition portions ( Jeong, [0041], The semiconductor layer may include a lightly doped drain (LDD) layer (not shown) between an active channel region (not shown) and source and drain regions (not shown). The semiconductor layer may be a polysilicon layer 23 ) is connected between one of the contact portions ( Jeong, FIG. 4, left part and right part of 43, where contacts with 48a and 48b; [0059], polysilicon layer 43; [0061], Source electrode 48a and drain electrode 48b ) and the channel ( Jeong, FIG. 4, 43; [0059], polysilicon layer 43 ), and the heat-retaining layer ( Jeong, FIG. 4, 44; [0059], heat retaining layer 44 ) is further in contact with the two transition portions ( Jeong, [0041], The semiconductor layer may include a lightly doped drain (LDD) layer (not shown) between an active channel region (not shown) and source and drain regions (not shown). The semiconductor layer may be a polysilicon layer 23 ).
Regarding Claim 5 (Previously Presented), Jeong teaches the thin film transistor as claimed in claim 1, on which this claim is dependent, Jeong further teaches:
wherein a thickness of the heat-retaining layer ( Jeong, FIG. 4, 44; [0059], heat retaining layer 44 ) is greater than or equal to 100 Å and is less than or equal to 1000 Å ( Jeong, [0020], The heat retaining layer may have a thickness of about 0.1 µm to about 1 µm );
wherein the heat-retaining layer ( Jeong, [0059], A heat retaining layer 44 may be sequentially formed on the polysilicon layer 43. In the exemplary embodiment illustrated in FIG. 4, after the ELA process, the heat retaining layer 44 is maintained and not removed. The heat retaining layer 44 may be used as an insulating layer; FIG. 2; [0023], The method may further include removing the heat retaining layer before forming the first insulating layer. The heat retaining layer may be removed by wet etching or dry etching ) is not in contact with the two contact portions ( Jeong, [0061], Source electrode 48a and drain electrode 48b may be electrically connected to the polysilicon layer 43 through the contact holes formed in the second insulating layer 47 ).
Regarding Claim 6 (Previously Presented), Jeong teaches the thin film transistor as claimed in claim 1, on which this claim is dependent, Jeong further teaches:
wherein the groove ( Jeong, FIG. 1, 14, or the contact between 12 and 18a / 18b; [0007], polysilicon layer 12 having protrusions 14 formed at grain boundaries; [0008], source and drain electrodes 18a and 18b ) is located at a position of at least one of the contact portions ( Jeong, FIG. 4, left part and right part of 43, where contacts with 48a and 48b; [0059], polysilicon layer 43; [0061], Source electrode 48a and drain electrode 48b ) adjacent to the channel ( Jeong, FIG. 4, 43; [0059], polysilicon layer 43 ).
Regarding Claim 7 (Previously Presented), Jeong teaches the thin film transistor as claimed in claim 1, on which this claim is dependent, Jeong further teaches:
wherein one groove ( Jeong, FIG. 1, 14, or the contact between 12 and 18a / 18b; [0007], polysilicon layer 12 having protrusions 14 formed at grain boundaries; [0008], source and drain electrodes 18a and 18b ) located on one of the contact portions ( Jeong, FIG. 4, left part and right part of 43, where contacts with 48a and 48b; [0059], polysilicon layer 43; [0061], Source electrode 48a and drain electrode 48b ) completely overlaps the one of the contact portions ( Jeong, FIG. 4, left part and right part of 43, where contacts with 48a and 48b; [0059], polysilicon layer 43; [0061], Source electrode 48a and drain electrode 48b ).
Regarding Claim 8 (Original), Jeong teaches the thin film transistor as claimed in claim 1, on which this claim is dependent, Jeong further teaches:
wherein the thin film transistor further comprises:
a gate electrode ( Jeong, FIG. 4, 46; [0060], gate electrode 46 ) disposed corresponding to the channel ( Jeong, FIG. 4, 43; [0059], polysilicon layer 43 );
a gate insulating layer ( Jeong, FIG. 4, 45; [0060], first insulating layer 45 ) located between the gate electrode ( Jeong, FIG. 4, 46; [0060], gate electrode 46 ) and the crystalline active pattern ( Jeong, FIG. 4, 43, [0059], polysilicon layer 43 );
an interlayer insulating layer ( Jeong, FIG. 4, 47; [0061], second insulating layer 47 ) located between the crystalline active pattern ( Jeong, FIG. 4, 43, [0059], polysilicon layer 43 ) and the source electrode ( Jeong, FIG. 4, 48a, 48b; [0061], Source electrode 48a and drain electrode 48b ) and between the crystalline active pattern ( Jeong, FIG. 4, 43, [0059], polysilicon layer 43 ) and the drain electrode ( Jeong, FIG. 4, 48a, 48b; [0061], Source electrode 48a and drain electrode 48b ); and
two contact holes ( Jeong, FIG. 4, contact holes filled by 48a and 48b; [0061], Source electrode 48a and drain electrode 48b ) at least penetrating the interlayer insulating layer ( Jeong, FIG. 4, 47; [0061], second insulating layer 47 ), and the source electrode and the drain electrode ( Jeong, FIG. 4, 48a, 48b; [0061], Source electrode 48a and drain electrode 48b ) being connected to the two contact portions ( Jeong, FIG. 4, left part and right part of 43, where contacts with 48a and 48b; [0059], polysilicon layer 43; [0061], Source electrode 48a and drain electrode 48b ) through the two contact holes ( Jeong, FIG. 4, contact holes filled by 48a and 48b; [0061], Source electrode 48a and drain electrode 48b ), respectively.
Regarding Claim 9 (Original), Jeong teaches the thin film transistor as claimed in claim 1, on which this claim is dependent, Jeong further teaches:
wherein the gate electrode ( Jeong, FIG. 4, 46; [0060], gate electrode 46 ) is located between the crystalline active pattern ( Jeong, FIG. 4, 43, [0059], polysilicon layer 43 ) and the source electrode ( Jeong, FIG. 4, 48a, 48b; [0061], Source electrode 48a and drain electrode 48b ) and between the crystalline active pattern ( Jeong, FIG. 4, 43, [0059], polysilicon layer 43 ) and the drain electrode, and the interlayer insulating layer ( Jeong, FIG. 4, 47; [0061], second insulating layer 47 ) is located between the gate electrode ( Jeong, FIG. 4, 46; [0060], gate electrode 46 ) and the source electrode ( Jeong, FIG. 4, 48a, 48b; [0061], Source electrode 48a and drain electrode 48b ) and between the gate electrode ( Jeong, FIG. 4, 46; [0060], gate electrode 46 ) and the drain electrode ( Jeong, FIG. 4, 48a, 48b; [0061], Source electrode 48a and drain electrode 48b ); and
the two contact holes ( Jeong, FIG. 4, contact holes filled by 48a and 48b; [0061], Source electrode 48a and drain electrode 48b ) further penetrate the gate insulating layer ( Jeong, FIG. 4, 45; [0060], first insulating layer 45 ), at least one of the two contact holes ( Jeong, FIG. 4, contact holes filled by 48a and 48b; [0061], Source electrode 48a and drain electrode 48b ) overlaps the groove ( Jeong, FIG. 1, 14, or the contact between 12 and 18a / 18b; [0007], polysilicon layer 12 having protrusions 14 formed at grain boundaries; [0008], source and drain electrodes 18a and 18b ), and an aperture of each of the contact holes is greater than an opening size of the groove ( Jeong, FIG. 1, 14, or the contact between 12 and 18a / 18b; [0007], polysilicon layer 12 having protrusions 14 formed at grain boundaries; [0008], source and drain electrodes 18a and 18b ).
Regarding Independent Claim 11 (Currently Amended), Jeong teaches an electronic device, wherein the electronic device comprises a thin film transistor, and the thin film transistor comprises:
a crystalline active pattern ( Jeong, FIG. 4, 43, [0059], polysilicon layer 43 ), wherein the crystalline active pattern ( Jeong, FIG. 4, 43, [0059], polysilicon layer 43 ) comprises:
a channel ( Jeong, FIG. 4, 43; [0059], polysilicon layer 43 );
two contact portions ( Jeong, FIG. 4, left part and right part of 43, where contacts with 48a and 48b; [0059], polysilicon layer 43; [0061], Source electrode 48a and drain electrode 48b ), the two contact portions ( Jeong, FIG. 4, left part and right part of 43, where contacts with 48a and 48b; [0059], polysilicon layer 43; [0061], Source electrode 48a and drain electrode 48b ) connected to opposite two sides of the channel ( Jeong, FIG. 4, 43; [0059], polysilicon layer 43 ) in a direction intersecting a thickness direction of the crystalline active pattern ( Jeong, FIG. 4, 43, [0059], polysilicon layer 43 ); and
at least one groove ( Jeong, FIG. 1, 14, or the contact between 12 and 18a / 18b; [0007], polysilicon layer 12 having protrusions 14 formed at grain boundaries; [0008], source and drain electrodes 18a and 18b ) formed in at least one of the two contact portions ( Jeong, FIG. 4, left part and right part of 43, where contacts with 48a and 48b; [0059], polysilicon layer 43; [0061], Source electrode 48a and drain electrode 48b ) by extending through ( Jeong, FIG. 1, protrusions 14; [0004], To form the polysilicon layer, intrinsic amorphous silicon may be deposited on an insulating substrate to a thickness of 40 nm to 200 nm by a predetermined method, i.e., a plasma chemical vapor deposition or a low pressure CVD (LPCVD) method, and then crystallized to form the polysilicon layer; [0010], The protrusions 14 may have a height of about 40 nm to about 200 nm, which may be almost equal to a height of the amorphous silicon layer ) at least one of the two contact portions ( Jeong, FIG. 4, left part and right part of 43, where contacts with 48a and 48b ) along the thickness direction of the crystalline active pattern ( Jeong, FIG. 4, 43, [0059], polysilicon layer 43 ) to expose a surface of a layer in contact with and below the contact portion ( Jeong, [0010], “ The protrusions 14 may have a height of about 40 nm to about 200 nm, which may be almost equal to a height of the amorphous silicon layer. ”. Therefore, when the height of protrusions 14 is equal to a height of the amorphous silicon layer ( which is then crystallized to form the polysilicon layer ), the layer in contact with and below the contact portion is exposed its surface. );
a source electrode and a drain electrode ( Jeong, FIG. 4, 48a, 48b; [0061], Source electrode 48a and drain electrode 48b ) connected to the two contact portions ( Jeong, FIG. 4, left part and right part of 43, where contacts with 48a and 48b; [0059], polysilicon layer 43; [0061], Source electrode 48a and drain electrode 48b ), respectively; and
a heat-retaining layer ( Jeong, FIG. 4, 44; [0059], heat retaining layer 44 ), the heat-retaining layer ( Jeong, FIG. 4, 44; [0059], heat retaining layer 44 ) being in contact with the channel ( Jeong, FIG. 4, 43; [0059], polysilicon layer 43 );
wherein a depth of the groove ( Jeong, FIG. 1, 14, or the contact between 12 and 18a / 18b; [0007], polysilicon layer 12 having protrusions 14 formed at grain boundaries; [0008], source and drain electrodes 18a and 18b; [0010], The protrusions 14 may have a height of about 40 nm to about 200 nm, which may be almost equal to a height of the amorphous silicon layer ) is equal to a thickness of the crystalline active pattern ( Jeong, FIG. 5, 52, 53, 52 thicker than 53; [0063], polysilicon layer 52, SiO2 layer 53 may have a thickness of about 50 nm to 500 nm ;
at least one of the source electrode and the drain electrode ( Jeong, FIG. 4, 48a, 48b ) is configured to extend along the at least one groove onto the exposed surface ( Jeong, FIG. 1, 14, or the contact between 12 and 18a / 18b ).
Regarding Claim 12 (Original), Jeong teaches the electronic device as claimed in claim 11, on which this claim is dependent on, Jeong further teaches:
wherein the crystalline active pattern ( Jeong, FIG. 4, 43, [0059], polysilicon layer 43 ) further comprises two transition portions ( Jeong, [0041], The semiconductor layer may include a lightly doped drain (LDD) layer (not shown) between an active channel region (not shown) and source and drain regions (not shown). The semiconductor layer may be a polysilicon layer 23 ), one of the transition portions ( Jeong, [0041], The semiconductor layer may include a lightly doped drain (LDD) layer (not shown) between an active channel region (not shown) and source and drain regions (not shown). The semiconductor layer may be a polysilicon layer 23 ) is connected between one of the contact portions ( Jeong, FIG. 4, left part and right part of 43, where contacts with 48a and 48b; [0059], polysilicon layer 43; [0061], Source electrode 48a and drain electrode 48b ) and the channel ( Jeong, FIG. 4, 43; [0059], polysilicon layer 43 ), and the heat-retaining layer ( Jeong, FIG. 4, 44; [0059], heat retaining layer 44 ) is further in contact with the two transition portions ( Jeong, [0041], The semiconductor layer may include a lightly doped drain (LDD) layer (not shown) between an active channel region (not shown) and source and drain regions (not shown). The semiconductor layer may be a polysilicon layer 23 ).
Regarding Claim 15 (Original), Jeong teaches the electronic device as claimed in claim 11, on which this claim is dependent on, Jeong further teaches:
wherein a thickness of the heat-retaining layer ( Jeong, FIG. 4, 44; [0059], heat retaining layer 44 ) is greater than or equal to 100 Å and is less than or equal to 1000 Å ( Jeong, [0020], The heat retaining layer may have a thickness of about 0.1 µm to about 1 µm ).
Regarding Claim 16 (Previously Presented), Jeong teaches the electronic device as claimed in claim 11, on which this claim is dependent on, Jeong further teaches:
wherein the groove ( Jeong, FIG. 1, 14, or the contact between 12 and 18a / 18b; [0007], polysilicon layer 12 having protrusions 14 formed at grain boundaries; [0008], source and drain electrodes 18a and 18b ) is located at a position of at least one of the contact portions ( Jeong, FIG. 4, left part and right part of 43, where contacts with 48a and 48b; [0059], polysilicon layer 43; [0061], Source electrode 48a and drain electrode 48b ) adjacent to the channel ( Jeong, FIG. 4, 43; [0059], polysilicon layer 43 ).
Regarding Claim 17 (Previously Presented), Jeong teaches the electronic device as claimed in claim 11, on which this claim is dependent on, Jeong further teaches:
wherein one groove ( Jeong, FIG. 1, 14, or the contact between 12 and 18a / 18b; [0007], polysilicon layer 12 having protrusions 14 formed at grain boundaries; [0008], source and drain electrodes 18a and 18b ) located on one of the contact portions ( Jeong, FIG. 4, left part and right part of 43, where contacts with 48a and 48b; [0059], polysilicon layer 43; [0061], Source electrode 48a and drain electrode 48b ) completely overlaps the one of the contact portions ( Jeong, FIG. 4, left part and right part of 43, where contacts with 48a and 48b; [0059], polysilicon layer 43; [0061], Source electrode 48a and drain electrode 48b ).
Regarding Claim 18 (Original), Jeong teaches the electronic device as claimed in claim 11, on which this claim is dependent on, Jeong further teaches:
wherein the thin film transistor further comprises:
a gate electrode ( Jeong, FIG. 4, 46; [0060], gate electrode 46 ) disposed corresponding to the channel ( Jeong, FIG. 4, 43; [0059], polysilicon layer 43 );
a gate insulating layer ( Jeong, FIG. 4, 45; [0060], first insulating layer 45 ) located between the gate electrode ( Jeong, FIG. 4, 46; [0060], gate electrode 46 ) and the crystalline active pattern ( Jeong, FIG. 4, 43, [0059], polysilicon layer 43 );
an interlayer insulating layer ( Jeong, FIG. 4, 47; [0061], second insulating layer 47 ) located between the crystalline active pattern ( Jeong, FIG. 4, 43, [0059], polysilicon layer 43 ) and the source electrode ( Jeong, FIG. 4, 48a, 48b; [0061], Source electrode 48a and drain electrode 48b ) and between the crystalline active pattern ( Jeong, FIG. 4, 43, [0059], polysilicon layer 43 ) and the drain electrode ( Jeong, FIG. 4, 48a, 48b; [0061], Source electrode 48a and drain electrode 48b ); and
two contact holes ( Jeong, FIG. 4, contact holes filled by 48a and 48b; [0061], Source electrode 48a and drain electrode 48b ) at least penetrating the interlayer insulating layer ( Jeong, FIG. 4, 47; [0061], second insulating layer 47 ), and the source electrode and the drain electrode ( Jeong, FIG. 4, 48a, 48b; [0061], Source electrode 48a and drain electrode 48b ) being connected to the two contact portions ( Jeong, FIG. 4, left part and right part of 43, where contacts with 48a and 48b; [0059], polysilicon layer 43; [0061], Source electrode 48a and drain electrode 48b ) through the two contact holes ( Jeong, FIG. 4, contact holes filled by 48a and 48b; [0061], Source electrode 48a and drain electrode 48b ), respectively.
Regarding Claim 19 (Original), Jeong teaches the electronic device as claimed in claim 18, on which this claim is dependent on, Jeong further teaches:
wherein the gate electrode ( Jeong, FIG. 4, 46; [0060], gate electrode 46 ) is located between the crystalline active pattern ( Jeong, FIG. 4, 43, [0059], polysilicon layer 43 ) and the source electrode ( Jeong, FIG. 4, 48a, 48b; [0061], Source electrode 48a and drain electrode 48b ) and between the crystalline active pattern ( Jeong, FIG. 4, 43, [0059], polysilicon layer 43 ) and the drain electrode ( Jeong, FIG. 4, 48a, 48b; [0061], Source electrode 48a and drain electrode 48b ), and the interlayer insulating layer ( Jeong, FIG. 4, 47; [0061], second insulating layer 47 ) is located between the gate electrode ( Jeong, FIG. 4, 46; [0060], gate electrode 46 ) and the source electrode ( Jeong, FIG. 4, 48a, 48b; [0061], Source electrode 48a and drain electrode 48b ) and between the gate electrode ( Jeong, FIG. 4, 46; [0060], gate electrode 46 ) and the drain electrode ( Jeong, FIG. 4, 48a, 48b; [0061], Source electrode 48a and drain electrode 48b ); and
the two contact holes ( Jeong, FIG. 4, contact holes filled by 48a and 48b; [0061], Source electrode 48a and drain electrode 48b ) further penetrate the gate insulating layer ( Jeong, FIG. 4, 45; [0060], first insulating layer 45 ), at least one of the two contact holes ( Jeong, FIG. 4, contact holes filled by 48a and 48b; [0061], Source electrode 48a and drain electrode 48b ) overlaps the groove ( Jeong, FIG. 1, 14, or the contact between 12 and 18a / 18b; [0007], polysilicon layer 12 having protrusions 14 formed at grain boundaries; [0008], source and drain electrodes 18a and 18b ), and an aperture of each of the contact holes is greater than an opening size of the groove ( Jeong, FIG. 1, 14, or the contact between 12 and 18a / 18b; [0007], polysilicon layer 12 having protrusions 14 formed at grain boundaries; [0008], source and drain electrodes 18a and 18b ).
Regarding Claim 20 (Original), Jeong teaches the electronic device as claimed in claim 11, on which this claim is dependent on, Jeong further teaches:
wherein the crystalline active pattern ( Jeong, FIG. 4, 43, [0059], polysilicon layer 43 ) is a low-temperature polysilicon active pattern ( Jeong, [0002], the invention relates to polysilicon TFTs and methods of fabricating TFTs employing a heat retaining layer to prevent and/or decrease a reduction in a melt duration time of an amorphous silicon layer when the amorphous silicon layer is exposed to light during, e.g., a crystallization process ).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 10 is rejected under 35 U.S.C. 103 as being unpatentable over Jeong, in view of Jeong.
Regarding Claim 10 (Previously Presented), Jeong teaches the thin film transistor as claimed in claim 1, on which this claim is dependent, Jeong further teaches:
wherein the crystalline active pattern ( Jeong, FIG. 4, 43, [0059], polysilicon layer 43 ) is a low-temperature polysilicon active pattern ( Jeong, [0002], the invention relates to polysilicon TFTs and methods of fabricating TFTs employing a heat retaining layer to prevent and/or decrease a reduction in a melt duration time of an amorphous silicon layer when the amorphous silicon layer is exposed to light during, e.g., a crystallization process );
wherein a cross-sectional shape of the groove ( Jeong, FIG. 1, 14, or the contact between 12 and 18a / 18b; [0007], polysilicon layer 12 having protrusions 14 formed at grain boundaries; [0008], source and drain electrodes 18a and 18b ).
Jeong did not explicitly disclose that wherein a cross-sectional shape of the groove along the thickness direction of the crystalline active pattern is trapezoidal, and a cross-sectional shape of the groove along a direction perpendicular to the thickness of the crystalline active pattern is rectangular or circular.
However, Jeong disclosed that [0007] “ The semiconductor layer may include a polysilicon layer 12 having protrusions 14 formed at grain boundaries ”; [0010], “ Therefore, the grain boundaries where the crystals meet generally protrude in the form of a peak or mountain, thereby forming protrusions 14. The protrusions 14 may have a height of about 40 nm to about 200 nm, which may be almost equal to a height of the amorphous silicon layer ”.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to use the disclosure of Jeong ( FIG. 1, protrusions 14, which means the groove shape of the contact of source and drain electrodes 18a and 18b ), and implement that wherein a cross-sectional shape of the groove along the thickness direction of the crystalline active pattern is trapezoidal, and a cross-sectional shape of the groove along a direction perpendicular to the thickness of the crystalline active pattern is rectangular or circular, since this is within the skill level of one in the art. Besides, In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966); see MPEP § 2144.04 IV. B. Changes in Shape.
Claims 3, 13 are rejected under 35 U.S.C. 103 as being unpatentable over Jeong, in view of Bai ( Pub. No. WO 2015192558 A1 ), hereinafter Bai.
Regarding Claim 3 (Original), Jeong teaches the thin film transistor as claimed in claim 1, on which this claim is dependent, Jeong further teaches:
wherein the crystalline active pattern ( Jeong, FIG. 4, 43, [0059], polysilicon layer 43 ) comprises crystalline grains.
Jeong fails to teach:
crystalline grains having a size greater than or equal to 300 nm.
However, Bai teaches:
crystalline grains having a size greater than or equal to 300 nm ( Bai, page 8, line 25, a crystal grain having an average particle diameter of about 2 μm is obtained ).
Jeong and Bai are both considered to be analogous to the claimed invention because they are thin film transistor comprising a crystalline active pattern made by excimer laser. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Jeong ( crystalline active pattern made by excimer laser ), to implement the teaching of Bai ( a crystal grain having an average particle diameter of about 2 μm is obtained ), to achieve the crystalline grains having a size greater than or equal to 300 nm. Doing so would provide a larger dimension of the crystalline grains, which can improve the mobility of electrons ( i.e. speed ) of thin film transistor.
Regarding Claim 13 (Original), Jeong teaches the electronic device as claimed in claim 11, on which this claim is dependent on, Jeong further teaches:
wherein the crystalline active pattern ( Jeong, FIG. 4, 43, [0059], polysilicon layer 43 ) comprises crystalline grains.
Jeong fails to teach:
crystalline grains having a size greater than or equal to 300 nm.
However, Bai teaches:
crystalline grains having a size greater than or equal to 300 nm ( Bai, page 8, line 25, a crystal grain having an average particle diameter of about 2 μm is obtained ).
Jeong and Bai are both considered to be analogous to the claimed invention because they are thin film transistor comprising a crystalline active pattern made by excimer laser. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Jeong ( crystalline active pattern made by excimer laser ), to implement the teaching of Bai ( a crystal grain having an average particle diameter of about 2 μm is obtained ), to achieve the crystalline grains having a size greater than or equal to 300 nm. Doing so would provide a larger dimension of the crystalline grains, which can improve the mobility of electrons ( i.e. speed ) of thin film transistor.
Claims 4, 14 are rejected under 35 U.S.C. 103 as being unpatentable over Jeong, in view of Hiramatsu ( Pub. No. US 20050012228 A1 ), hereinafter Hiramatsu.
Regarding Claim 4 (Original), Jeong teaches the thin film transistor as claimed in claim 1, on which this claim is dependent, Jeong further teaches:
wherein a refractive index of the heat-retaining layer ( Jeong, FIG. 4, 44; [0059], heat retaining layer 44 ) is defined as n, a thickness of the heat-retaining layer ( Jeong, FIG. 4, 44; [0059], heat retaining layer 44 ) is defined as d, and the n, the d, and a wavelength λ of laser light satisfy a following formula:
2d×n=k×λ, wherein the k is an integer greater than or equal to 1 ( Jeong, [0002], heat retaining layer to prevent and/or decrease a reduction in a melt duration time of an amorphous silicon layer when the amorphous silicon layer is exposed to light during, e.g., a crystallization process. The heat retaining layer may be formed on the amorphous silicon layer, and may be capable of absorbing heat and/or blocking heat so as to help maintain and/or increase a melt duration time of the amorphous silicon layer during a crystallization process for forming a polysilicon layer; therefore, interference formula is used to calculate the thickness of heat retaining layer; [0048], heat retaining layer 34 may have high thermal conductivity and may be formed to have a thickness of about 0.1 µm to about 1 µm; [0049], laser light may be radiated on a portion of the conductive substrate where the buffer layer 31, the amorphous silicon layer 32 and the heat retaining layer 34 are formed. Laser light may be radiated by an excimer laser annealing (ELA) method ).
Jeong fails to teach:
the wavelength λ of the laser light is greater than or equal to 180 nm and is less than or equal to 420 nm;
However, Hiramatsu teaches:
the wavelength λ of the laser light is greater than or equal to 180 nm and is less than or equal to 420 nm ( Hiramatsu, [0190], KrF excimer laser beam ( λ = 248 nm ) is used as an energy beam. Alternatively, for instance, XeCl ( λ = 308 nm ), XeF ( λ = 351 nm ), or ArF ( λ = 193 nm ) is usable );
Jeong and Hiramatsu are both considered to be analogous to the claimed invention because they are thin film transistor comprising a crystalline active pattern made by excimer laser. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Jeong ( crystalline active pattern made by excimer laser ), to implement the teaching of Hiramatsu ( excimer laser beam wavelength λ = 248 or 308 or 351 or 193 nm ), to achieve the wavelength λ of the laser light is greater than or equal to 180 nm and is less than or equal to 420 nm. Doing so would provide suitable wavelengths of excimer laser which can work with the heat retaining layer to slow down the heat dissipation, and therefore to form large size crystalline grain in the channel.
Regarding Claim 14 (Original), Jeong teaches the electronic device as claimed in claim 11, on which this claim is dependent on, Jeong further teaches:
wherein a refractive index of the heat-retaining layer ( Jeong, FIG. 4, 44; [0059], heat retaining layer 44 ) is defined as n, a thickness of the heat-retaining layer ( Jeong, FIG. 4, 44; [0059], heat retaining layer 44 ) is defined as d, and the n, the d, and a wavelength λ of laser light satisfy a following formula:
2d×n=k×λ, wherein the k is an integer greater than or equal to 1 ( Jeong, [0002], heat retaining layer to prevent and/or decrease a reduction in a melt duration time of an amorphous silicon layer when the amorphous silicon layer is exposed to light during, e.g., a crystallization process. The heat retaining layer may be formed on the amorphous silicon layer, and may be capable of absorbing heat and/or blocking heat so as to help maintain and/or increase a melt duration time of the amorphous silicon layer during a crystallization process for forming a polysilicon layer; therefore, interference formula is used to calculate the thickness of heat retaining layer; [0048], heat retaining layer 34 may have high thermal conductivity and may be formed to have a thickness of about 0.1 µm to about 1 µm; [0049], laser light may be radiated on a portion of the conductive substrate where the buffer layer 31, the amorphous silicon layer 32 and the heat retaining layer 34 are formed. Laser light may be radiated by an excimer laser annealing (ELA) method ).
Jeong fails to teach:
the wavelength λ of the laser light is greater than or equal to 180 nm and is less than or equal to 420 nm;
However, Hiramatsu teaches:
the wavelength λ of the laser light is greater than or equal to 180 nm and is less than or equal to 420 nm ( Hiramatsu, [0190], KrF excimer laser beam ( λ = 248 nm ) is used as an energy beam. Alternatively, for instance, XeCl ( λ = 308 nm ), XeF ( λ = 351 nm ), or ArF ( λ = 193 nm ) is usable );
Jeong and Hiramatsu are both considered to be analogous to the claimed invention because they are thin film transistor comprising a crystalline active pattern made by excimer laser. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Jeong ( crystalline active pattern made by excimer laser ), to implement the teaching of Hiramatsu ( excimer laser beam wavelength λ = 248 or 308 or 351 or 193 nm ), to achieve the wavelength λ of the laser light is greater than or equal to 180 nm and is less than or equal to 420 nm. Doing so would provide suitable wavelengths of excimer laser which can work with the heat retaining layer to slow down the heat dissipation, and therefore to form large size crystalline grain in the channel.
Response to Arguments
Applicant’s argument for claims 1 and 11 ( Currently Amended ): page 7, line 5 from bottom, cited “ According to FIG. 1 of Jeong, a person having ordinary skill in the art would understand that the height of the protrusions 14 refers to the elevation of the top of the protrusions 14, rather than the depth of the groove formed by the protrusions 14 (i.e., the distance between the bottom and top of the wave portion of the polysilicon layer 12), see the annotated FIG. 1 above for reference. If a skilled person considers the height of the protrusion 14 as the depth of the groove formed by the protrusion 14, the surface of the groove shown in FIG. 1 shall be extended downward to contact the upper surface of the buffer layer 11 to conform to the description in paragraph 0010 that "The protrusions 14 may have a height of about 40 nm to about 200 nm, which may be almost equal to a height of the amorphous silicon layer". However, FIG. 1 does not show that the surface of the groove extends downward to contact with the upper surface of the buffer layer 11. Therefore, based on the teaching of FIG. 1 and paragraph 0010, the height of the protrusions 14 shall not be considered as the depth of the groove, but shall be considered as the distance between the top of the protrusions 14 to the bottom of the amorphous silicon layer (resulting in the polysilicon layer 12). ”.
Examiner’s response: Jeong [0010], cited “ The protrusions 14 may have a height of about 40 nm to about 200 nm, which may be almost equal to a height of the amorphous silicon layer ” already teaches the amended claim 1 “ at least one groove formed … by extending through … along the thickness direction of the crystalline active pattern to expose a surface of a layer in contact with and below the contact portion ”, because the height of protrusions 14 may be almost equal to a height of the amorphous silicon layer; based on Jeong’s teaching, it is obvious for a skilled person in the field to consider variations for the shape and dimension of protrusions 14, including the amended claim 1 “ at least one groove formed … by extending through … along the thickness direction of the crystalline active pattern to expose a surface of a layer in contact with and below the contact portion ” and the example of wave protrusions 14 illustrated in Jeong FIG. 1.
Applicant’s argument for claim 5 ( Currently Amended ): page 8, line 6 from bottom, cited “ However, the teaching of paragraph 0059 and FIG. 4 suggests that the heat retaining layer 44 is in contact with both the channel (i.e., the central portion of the polysilicon layer 43) and the two contact portions (i.e., left and right portions of the polysilicon layer 43). The teaching of paragraph 0023 and FIG. 2 suggest that the retaining layer 44 is completely removed from the upper surface of the polysilicon layer 43 so that the heat retaining layer 44 is not in contact with both the channel (i.e., the central portion of the polysilicon layer 43) and the two contact portions (i.e., left and right portions of the polysilicon layer 43). It fails to teach or suggest that the retaining layer 44 is remained to be in contact with the channel (of the polysilicon layer 43) but not in contact with the two contact portions (of the polysilicon layer 43), as defined in claim 5. ”.
Examiner’s response: Jeong teaches the possibilities of removing and not removing the heat retaining layer 44, specifically, Jeong, [0059], cited “ A heat retaining layer 44 may be sequentially formed on the polysilicon layer 43. In the exemplary embodiment illustrated in FIG. 4, after the ELA process, the heat retaining layer 44 is maintained and not removed. The heat retaining layer 44 may be used as an insulating layer ”; and specifically Jeong, FIG. 2 and [0023], cited “ The method may further include removing the heat retaining layer before forming the first insulating layer. The heat retaining layer may be removed by wet etching or dry etching ”; therefore, it is obvious for a skilled person in the field to partially remove the heat retaining layer 44 to be not in contact with the two contact portions, and partially not remove the heat retaining layer 44 to be in contact with the channel, because it is just an example based on the teaching from Jeong.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Da-Wei Lee whose telephone number is 703-756-1792. The examiner can normally be reached M -̶ F 8:00 am -̶ 6:00 pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Marlon Fletcher can be reached at 571-272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/DA-WEI LEE/Examiner, Art Unit 2817
/MARLON T FLETCHER/Supervisory Primary Examiner, Art Unit 2817
Prosecution Insights