DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 5 is objected to because of the following informalities: The claim depends from cancelled claim 3, it is assumed to be dependent from claim 1 for examination purposes. Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 2, and 4 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Tsukamoto (US 2021/0013218).
The applied reference has a common applicant with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2). This rejection under 35 U.S.C. 102(a)(2) might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C. 102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B) if the same invention is not being claimed; or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed in the reference and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement.
Regarding claim 1, Tsukamoto teaches a semiconductor storage device (10), comprising:
a semiconductor substrate (100);
a field-effect transistor (21) provided on the semiconductor substrate (100);
an interlayer insulation film (planarization film 200 with interlayer insulating film 300) on the semiconductor substrate (100);
a source contact (210) that runs through the interlayer insulation film (200) and is electrically coupled to a source of the field-effect transistor (contact 210 electrically connects with the other one of source/drain region 151 and is formed by opening the planarization film 200 and filling it with Ti/TiN/W);
an opening portion that is in a region of the interlayer insulation film, wherein and allows the source contact is projected in the opening portion (capacitor is formed in an opening penetrating the planarization film 200, and the contact 210 is formed through the planarization film 200 to the source/drain region 151); and
a capacitor (11) including a lower electrode (111), a ferroelectric film (113), and an upper electrode (115),
wherein the lower electrode (111) is along an inside shape of the opening portion (electrode 111 is formed along the internal shape of the opening; it is recessed from the opening surface),
the ferroelectric film (113) is on the lower electrode (111),
the upper electrode (115) is on the ferroelectric film (113) to fill the opening portion, and
the ferroelectric film (113) and the upper electrode (115) are further on the interlayer insulation film (ferroelectric film 113 and electrode 115 are formed in the opening and over the planarization film surface; excess material on the film surface is removed).
Regarding claim 2, Tsukamoto the semiconductor storage device according to claim 1, wherein the capacitor (11) is inside the opening portion (inside the opening in the planarization film 200), and
a surface position of the upper electrode (115) coincides with a surface position of the interlayer insulation film (electrode 115 is formed to fill the opening and then excess material is removed from the surface by CMP/etch-back; suggests a flush or co-planar top surface).
Regarding claim 4, Tsukamoto discloses the semiconductor storage device according to claim 1, wherein the lower electrode (111), the ferroelectric film (113), and the upper electrode (115) are further on the interlayer insulation film (200, 300).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 5-9 are rejected under 35 U.S.C. 103 as being obvious over Tsukamoto.
The applied reference has a common assignee with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2).
This rejection under 35 U.S.C. 103 might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C.102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B); or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement. See generally MPEP § 717.02.
Tsukamoto discloses the semiconductor storage device according to claim 1, further comprising:
a memory cell array in which multiple memory cells are arranged (“A large number of semiconductor storage devices 10 are arranged in a matrix on the semiconductor substrate 100 to form a semiconductor memory capable of storing a large amount of information.” ¶ [0080]), each memory cell of the multiple memory cells including the field-effect transistor and the capacitor (Each semiconductor storage device 10 includes capacitor 11 and transistor 21. See ¶¶ [0068]-[0074], [0081]-[0082], [0099]), wherein
the upper electrode is shared between a first memory cell of the multiple memory cells and a second memory cell of the multiple memory cells (“one of the electrodes of the capacitor 11 is shared as one of electrodes by the capacitor of the adjacent memory cell” ¶ [0070] where the shared electrode corresponds to the claimed upper electrode; Also “an electrode embedded in a recessed portion provided in a semiconductor substrate is shared by adjacent memory cells” ¶ [0075]), and the first memory cell is adjacent to the second memory cell (“adjacent memory cell” appears in ¶¶ [0070], [0075], and [0123]).
It would have been obvious to a person of ordinary skill in the art at the time of the invention to arrange the memory cells of Tsukamoto in an array such that the electrode of one memory cell is shared with an adjacent memory cell, as expressly taught by Tsukamoto, in order to reduce cell area and improve miniaturization and integration density. Applying this known shared-electrode arrangement to the memory cell structure of Tsukamoto would have predictably yielded the claimed memory cell array in which the upper electrode is shared between adjacent first and second memory cells. The resulting structure would satisfy claim 5, which requires a semiconductor storage device including a memory cell array, multiple memory cells each including a field-effect transistor and a capacitor, and a shared upper electrode between adjacent memory cells.
Regarding claim 6, Tsukamoto discloses a semiconductor storage device according to claim 1, wherein
the interlayer insulation film includes a stopper layer of a specific material (states that a linear layer may be provided over the semiconductor substrate, side wall insulating film, and conductive layer, and that it can provide high etching selectivity between the planarization film and the linear layer; similar to a “stopper layer” ¶ [0089]) , and
the opening portion exposes the stopper layer (forming an opening in the planarization film).
However, Tsukamoto does not expressly state that the opening exposes a stopper layer. The “linear layer” functions as an etch-selective layer, but the precise “exposes the stopper layer” language is not explicit.
It would have been obvious to include a stopper layer in the interlayer insulating film, or to expose such a stopper layer during opening formation, because Tsukamoto expressly teaches the use of a linear layer/stopping layer concept to improve etch controllability and selectivity. The claimed stopper-layer feature would therefore have been an obvious design variation of the layer stack and opening-formation process.
Regarding claim 7, Tsukamoto discloses the semiconductor storage device according to claim 1, wherein
a gate electrode of the field-effect transistor extends in a first direction in a plane of the semiconductor substrate (gate electrode 130 extends in a first direction across the active region, ¶¶ [0068], [0079], [0080], Fig.2), and
a plan shape of the opening portion is a rectangular shape (formation of an opening in the planarization film and interlayer insulating film, ¶¶ [0121]-[0123], ¶¶ [0138]-[0140]) in which a longitudinal direction is set to the first direction (first direction for the gate electrode and the orthogonal second direction for source/bit lines, ¶¶ [0079], [0099]-[0100], FIG. 2).
Tsukamoto discloses width and depth, but does not expressly say the opening is rectangular. Also it does not expressly correlate the opening’s long axis with the first direction.
It would have been obvious to shape the opening portion in a rectangular layout aligned with the gate direction in order to facilitate repeated memory-cell patterning, improve layout regularity, and fit the orthogonal line architecture already taught by Tsukamoto. The claimed plan-shape limitation is therefore an obvious geometric optimization of the structure disclosed in Tsukamoto.
Regarding claim 8, Tsukamoto discloses the semiconductor storage device according to claim 1, wherein the opening portion (an opening formed in the planarization film / interlayer insulating film ¶¶ [0121]-[0123], ¶¶ [0138]-[0140]) is in a tapered shape in which an opening diameter of the opening portion decreases in a direction toward the semiconductor substrate.
Regarding claim 9, Tsukamoto discloses the semiconductor storage device according to claim 1, wherein
the upper electrode is electrically coupled to a plate line (ne electrode of the capacitor 11 is electrically connected to the source line SL, ¶¶ [0050], [0066], [0099]), and
a drain of the field-effect transistor is electrically coupled to a bit line (one source/drain region is connected to the bit line BL via the contact 210, ¶¶ [0051], [0068], [0096]-[0100], ¶¶ [0176]-[0177]).
However, Tsukamoto uses source line SL, not necessarily plate line, and the claim’s upper electrode language does not map one-to-one directly.
It would have been obvious to electrically couple the upper electrode to a plate-type line or equivalent common reference line in view of Tsukamoto’s teaching that one capacitor electrode is connected to the source line and the other electrode is driven relative to the bit line. The drain-to-bit-line coupling is directly taught, and the plate-line terminology would have been an obvious naming or circuit-architecture variation.
Response to Arguments
Applicant's arguments filed July 29, 2025 have been fully considered but they are not persuasive.
Applicant argues that Tsukamoto ’218 does not expressly or inherently disclose “the ferroelectric film and the upper electrode are further on the interlayer insulation film.” This argument is not persuasive.
Tsukamoto ’218 discloses that the semiconductor storage device includes a planarization film 200 and an interlayer insulating film 300 formed over the semiconductor substrate, and that the capacitor 11 includes a first capacitor electrode 111, ferroelectric film 113, and second capacitor electrode 115. See Tsukamoto ’218 ¶¶ [0063], [0066], [0098]-[0100]. Tsukamoto ’218 further teaches an embodiment in which the interlayer insulating film 300 is formed over the planarization film 200, and a wiring layer is formed in the interlayer insulating film. See, e.g., ¶¶ [0098]-[0100], [0128]-[0131], [0138]-[0147]. Thus, the reference teaches the claimed layered memory-cell architecture, including a ferroelectric capacitor disposed in the device stack above the semiconductor substrate.
To the extent Applicant contends that Tsukamoto ’218 must expressly recite the exact phrase “further on the interlayer insulation film,” such exact wording is not required for anticipation where the cited reference discloses the claimed structure reasonably and necessarily. Tsukamoto ’218 teaches that the capacitor is formed in the upper portion of the device stack with the interlayer insulating film present beneath the wiring layer arrangement, and the capacitor structure is shown in FIG. 2 in relation to the planarization film and overlying layers. Accordingly, the rejection is maintained.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/SUE A PURVIS/ Supervisory Patent Examiner, Art Unit 2893
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