DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Style
In this action unitalicized bold is used for claim language, while italicized bold is used for emphasis.
Information Disclosure Statement
It is noted that the IDS filed 03/06/2024 includes at least one reference that was already cited in an earlier IDS. If the IDS of 03/06/2024 was filed to disclose art cited in an office action from a foreign patent office, any office action from a foreign patent office having caused Applicant to submit art in an IDS hereby requested to clarify which sections of the cited art are likely to be materiel to patentability.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. Generally, the title of a patent application refers to an invention, and not an entire technological field. While avoiding a limiting characterization of one’s invention may be strategically sound, it is submitted that some characterization may be required to comply with the MPEP’s requirements for titles of inventions. It is submitted that Applicant has invented something narrower than the “quantum computer system and control device.”
Applicant Reply
“The claims may be amended by canceling particular claims, by presenting new claims, or by rewriting particular claims as indicated in 37 CFR 1.121(c). The requirements of 37 CFR 1.111(b) must be complied with by pointing out the specific distinctions believed to render the claims patentable over the references in presenting arguments in support of new claims and amendments. . . . The prompt development of a clear issue requires that the replies of the applicant meet the objections to and rejections of the claims. Applicant should also specifically point out the support for any amendments made to the disclosure. See MPEP § 2163.06. . . . An amendment which does not comply with the provisions of 37 CFR 1.121(b), (c), (d), and (h) may be held not fully responsive. See MPEP § 714.” MPEP § 714.02. Generic statements or listing of numerous paragraphs do not “specifically point out the support for” claim amendments. “With respect to newly added or amended claims, applicant should show support in the original disclosure for the new or amended claims. See, e.g., Hyatt v. Dudas, 492 F.3d 1365, 1370, n.4, 83 USPQ2d 1373, 1376, n.4 (Fed. Cir. 2007) (citing MPEP § 2163.04 which provides that a ‘simple statement such as ‘applicant has not pointed out where the new (or amended) claim is supported, nor does there appear to be a written description of the claim limitation ‘___’ in the application as filed’ may be sufficient where the claim is a new or amended claim, the support for the limitation is not apparent, and applicant has not pointed out where the limitation is supported.’)” MPEP § 2163(II)(A).
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
Unless specifically indicated in this office action, claim limitations are not interpreted as means plus function under § 112(f).
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. “’The standard is whether the words of the claim are understood by persons of ordinary skill in the art to have a sufficiently definite meaning as the name for structure.’” Williamson, 792 F.3d at 1349, 115 USPQ2d at 1111; see also Greenberg v. Ethicon Endo-Surgery, Inc., 91 F.3d 1580, 1583, 39 USPQ2d 1783, 1786 (Fed. Cir. 1996).” MPEP § 2181(I). Such claim limitation(s) is/are: “acquisition unit that acquires” “computation unit(s) . . . to execute computation” “selection unit that selects” and “execution unit that causes . . . to execute computation” in independent claims 1 and 10, and repeated in various independent claims.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-12 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for pre-AIA the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claims 1 and 10, and various independent claims recite the following means interpreted as means plus function language under § 112f: “acquisition unit that acquires” “computation unit(s) . . . to execute computation” “selection unit that selects” and “execution unit that causes . . . to execute computation[.]” No support for any specific structure or any specific algorithm implemented on hardware is found in the Specification for any of these terms. “For a computer-implemented 35 U.S.C. 112(f) claim limitation, the specification must disclose an algorithm for performing the claimed specific computer function, or else the claim is indefinite under 35 U.S.C. 112(b). See Net MoneyIN, Inc. v. Verisign. Inc., 545 F.3d 1359, 1367, 88 USPQ2d 1751, 1757 (Fed. Cir. 2008).” MPEP § 2181. “Thus, the specification must sufficiently disclose an algorithm to transform a general purpose microprocessor to the special purpose computer. See Aristocrat, 521 F.3d at 1338, 86 USPQ2d at 1241. ("Aristocrat was not required to produce a listing of source code or a highly detailed description of the algorithm to be used to achieve the claimed functions in order to satisfy 35 U.S.C. § 112 ¶ 6. It was required, however, to at least disclose the algorithm that transforms the general purpose microprocessor to a ‘special purpose computer programmed to perform the disclosed algorithm.’" (quoting WMS Gaming, 184 F.3d at 1349, 51 USPQ2d at 1391.)) An algorithm is defined, for example, as "a finite sequence of steps for solving a logical or mathematical problem or performing a task." Microsoft Computer Dictionary, Microsoft Press, 5th edition, 2002.” MPEP § 2181. “When a claim containing a computer-implemented 35 U.S.C. 112(f) claim limitation is found to be indefinite under 35 U.S.C. 112(b) for failure to disclose sufficient corresponding structure (e.g., the computer and the algorithm) in the specification that performs the entire claimed function, it will also lack written description under 35 U.S.C. 112(a).” MPEP §2181.
All dependent claims are rejected as containing the limitations of the claims from which they depend.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-12 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claims 1 and 10, and various independent claims recite the following means interpreted as means plus function language under § 112f: “acquisition unit that acquires” “computation unit(s) . . . to execute computation” “selection unit that selects” and “execution unit that causes . . . to execute computation[.]” No support for any specific structure or any specific algorithm implemented on hardware is found in the Specification for any of these terms. “For a computer-implemented 35 U.S.C. 112(f) claim limitation, the specification must disclose an algorithm for performing the claimed specific computer function, or else the claim is indefinite under 35 U.S.C. 112(b). See Net MoneyIN, Inc. v. Verisign. Inc., 545 F.3d 1359, 1367, 88 USPQ2d 1751, 1757 (Fed. Cir. 2008).” MPEP § 2181. “Thus, the specification must sufficiently disclose an algorithm to transform a general purpose microprocessor to the special purpose computer. See Aristocrat, 521 F.3d at 1338, 86 USPQ2d at 1241. ("Aristocrat was not required to produce a listing of source code or a highly detailed description of the algorithm to be used to achieve the claimed functions in order to satisfy 35 U.S.C. § 112 ¶6. It was required, however, to at least disclose the algorithm that transforms the general purpose microprocessor to a ‘special purpose computer programmed to perform the disclosed algorithm.’" (quoting WMS Gaming, 184 F.3d at 1349, 51 USPQ2d at 1391.)) An algorithm is defined, for example, as "a finite sequence of steps for solving a logical or mathematical problem or performing a task." Microsoft Computer Dictionary, Microsoft Press, 5th edition, 2002.” MPEP § 2181. “When a claim containing a computer-implemented 35 U.S.C. 112(f) claim limitation is found to be indefinite under 35 U.S.C. 112(b) for failure to disclose sufficient corresponding structure (e.g., the computer and the algorithm) in the specification that performs the entire claimed function, it will also lack written description under 35 U.S.C. 112(a).” MPEP §2181.
All dependent claims are rejected as containing the limitations of the claims from which they depend.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5, 7-8, and 10-12 are rejected under 35 U.S.C. 103 as being unpatentable over (Bertels Quantum Computer Architecture: Towards Full-Stack Quantum Accelerators) and Bolt (US 2021/0158232).
1. (Original) A computer system comprising: (“Given the recent insights leading to e.g. Noisy Intermediate-Scale Quantum (NISQ) technology as expressed in [2], we are much more inclined to believe that the first industry-based and societal relevant application will be a hybrid combination of a classical computer and a quantum accelerator. It is based on the idea that any end-application contains multiple computational kernels and the properties of these parts are better executed by a particular accelerator which can be, as shown in Figure 1, either field-programmable gate arrays (FPGA), graphics-processing units (GPU), neural processing units (NPU) like Google's tensor processing unit, etc. The formal definition of an accelerator is indeed a co-processor linked to the central processor that is capable of accelerating the execution of specific computational intensive kernels, as to speed up the overall execution according to Amdahl's law. We now add two classes of quantum accelerator as additional co-processors. The first one is based on quantum gates and the second is based on quantum annealing. The classical host processor keeps the control over the total system and delegates the execution of certain parts to the available accelerators.” Bertels P. 1.) an acquisition unit that acquires computation details; (Bertels does not expressly teach acquiring computation details.
Bolt teaches “[0119] For example, a set of interactions exchanged between a customer and a quantum algorithm development kit to design and execute a quantum task/algorithm/circuit may include the interactions shown in 420 through 434. . . . [0120] For example, at 420 customer 418 may select a design paradigm to use to define a quantum object (e.g. quantum task/algorithm/circuit) to be submitted to the quantum computing service for execution on a quantum computer of a quantum hardware provider or a simulator. At 422, customer 418 may provide a definition for the quantum object using the selected design paradigm. For example customer 418 may define the quantum object in the design space 404 using the various tools available for use in the different design paradigms. . . . [0121] At 424, customer 418 may request to simulate the quantum object defined in design space 404 by selecting simulation button 412. At 426, the quantum algorithm development kit 114 may provide customer 418 with simulation results. For example, the simulation results may be displayed in design space 404. Also, at 428 the quantum algorithm development kit 114 may provide customer 418 with a performance/cost estimate and/or a recommendation. For example, in response to the customer 418 selecting cost/performance estimation/recommendation button 414. . . . [0122] At 430, customer 418 may select a quantum hardware provider and/or quantum computer type to be used to execute the quantum object defined by the customer 418.” Bolt ¶¶ 119-122.
It would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teaching of Bolt because acquiring the computation details allows the system to determine which quantum hardware has the least cost for a given quantum task/algorithm/circuit.) a group of computation units including a plurality of computation units each configured to execute computation using quantum effects in a superconducting state or thermal effects in a superconducting state; (The Specification offers quantum annealing as an example of the claimed executing computation using quantum in a superconducting state or thermal effects in a superconducting state. Spec. ¶66. (“The computation unit has a superconducting material, and executes computation using quantum effects or thermal effects in the superconducting state. More specifically, the computation unit can execute computation using quantum annealing or other methods when the temperature of the computation unit is equal to or lower than the superconducting temperature of the superconducting material.”) Bertels teaches “We now add two classes of quantum accelerator as additional co-processors. The first one is based on quantum gates and the second is based on quantum annealing.” Bertels P. 1. See also Fig. 2(a) of Bertels showing four different types of qubits in a quantum accelerator and P. 16 teaching implementation of quantum annealing using superconducting qubits.) a selection unit that selects a computation unit from the group of computation units based on the computation details; and an execution unit that causes the computation unit selected by the selection unit to execute computation. (“The formal definition of an accelerator is indeed a co-processor linked to the central processor that is capable of accelerating the execution of specific computational intensive kernels, as to speed up the overall execution according to Amdahl's law. We now add two classes of quantum accelerator as additional co-processors.” Bertels P. 1.)
2. (Original) The computer system according to claim 1, wherein the group of computation units includes a general-purpose computation unit that is a computation unit for general purposes and a specific computation unit that is a computation unit for a specific purpose, (“The history of computer architecture dates back various decades and has been very evolving. An important extension is the emergence of accelerators [1] as specialised processing units to which the host processor offloads suitable computational tasks.” Bertels P. 1. The “general-purpose computation unit” reads on the host processor. See also Bertels Fig. 1 showing a host CPU connected to various processing units. Alternatively, the “general-purpose computation unit” also reads on the FPGA and GPU in Fig. 1.) and wherein the selection unit selects the general-purpose computation unit if the group of computation units does not include a specific computation unit for a purpose matching the computation details, and selects the specific computation unit if the group of computation units includes a specific computation unit for a purpose matching the computation details. (“Given the recent insights leading to e.g. Noisy Intermediate-Scale Quantum (NISQ) technology as expressed in [2], we are much more inclined to believe that the first industry-based and societal relevant application will be a hybrid combination of a classical computer and a quantum accelerator. It is based on the idea that any end-application contains multiple computational kernels and the properties of these parts are better executed by a particular accelerator which can be, as shown in Figure 1, either field-programmable gate arrays (FPGA), graphics-processing units (GPU), neural processing units (NPU) like Google's tensor processing unit, etc. The formal definition of an accelerator is indeed a co-processor linked to the central processor that is capable of accelerating the execution of specific computational intensive kernels, as to speed up the overall execution according to Amdahl's law. We now add two classes of quantum accelerator as additional co-processors. The first one is based on quantum gates and the second is based on quantum annealing. The classical host processor keeps the control over the total system and delegates the execution of certain parts to the available accelerators.” Bertels P. 1. Note also that figure 2 of Bertels shows multiple types of qbits.)
3. (Original) The computer system according to claim 1, wherein the group of computation units includes a plurality of specific computation units for different purposes, and wherein the selection unit selects a specific computation unit for a purpose matching the computation details. (“We believe that the choice of the quantum accelerator is dependent on the specific energy landscape of the application, as well as the characteristics of the quantum systems (e.g. annealers can process larger problem sizes, whereas gate models allow longer coherence times).” Bertels P. 14.)
4. (Currently Amended) The computer system according to claim 1, wherein the group of computation units includes a plurality of computation units formed on the same board. (See Bertels Fig. 2.)
5. (Currently Amended) The computer system according to claim 1, wherein the group of computation units includes a plurality of computation units formed on different boards. (See Bertels Figure 1 showing a separate quantum annealer and gate-based QC.)
7. (Currently Amended) The computer system according to claim 1, wherein the selection unit selects a plurality of computation units from the group of computation units, and wherein the execution unit causes each of the plurality of computation units selected by the selection unit to execute computation. (See rejection of claim 1.)
8. (Original) The computer system according to claim 7, wherein the execution unit causes each of the plurality of computation units selected by the selection unit to execute computation such that computations executed by the respective plurality of computation units selected by the selection unit become asynchronous to each other. (Bertels teaches “Real and realistic qubits: To accommodate quantum processor development, we look at the experimental algorithms that the physics community are interested in, such as randomised (single and double) qubit gates. This phase would also comprise of hardware assessment and characterisation to meet the timing-precision and signal synchronisation requirements for a specific qubit-technology. Bertels P. 9. Note that qubit technology specific synchronization implies that different qubit technologies would not be synchronized with each other. See e.g. Figs. 1 and 2a showing hardware accelerators including more than one type of qubit technology.)
10. (Original) A control device comprising: an acquisition unit that acquires computation details; and a selection unit that selects, based on the computation details, a computation unit from a group of computation units including a plurality of computation units each configured to execute computation using quantum effects in a superconducting state or thermal effects in a superconducting state. (See rejection of claim 1.)
11. (Currently Amended) The control device according to claim 10, wherein the group of computation units includes a general-purpose computation unit that is a computation unit for general purposes and a specific computation unit that is a computation unit for a specific purpose, and wherein the selection unit selects the general-purpose computation unit if the group of computation units does not include a specific computation unit for a purpose matching the computation details, and selects the specific computation unit if the group of computation units includes a specific computation unit for a purpose matching the computation details. (See rejection of claim 2.)
12. (Original) The control device according to claim 10, wherein the group of computation units includes a plurality of specific computation units for different purposes, and wherein the selection unit selects a specific computation unit for a purpose matching the computation details. (See rejection of claim 3.)
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Bertels, Bolt, and Lechner (EP 3113084, published 2017)
6. (Original) The computer system according to claim 5, wherein the plurality of computation units formed on different boards include a plurality of computation units formed on boards of different temperatures, and wherein each of the plurality of computation units formed on the boards of different temperatures is formed on a board of a temperature appropriate for computation by each computation unit. (See Bertels Fig. 1 showing two types of quantum computation units.
Bertels does not expressly teach that the separate parts of the system of Figure 1 are kept at different temperatures.
Lechner teaches “The ground state of the final Hamiltonian may be a state of the quantum system at zero temperature. Not wishing to be bound by any particular theory, according to considerations in the field of quantum physics, it is considered impossible for a quantum system to reach a temperature of absolute zero. Still, evolving the quantum system from the initial quantum state towards the ground state of the final Hamiltonian, including e.g. cooling the quantum system to an operating temperature T.sub.max, may allow approaching the ground state of the final Hamiltonian. The operating temperature T.sub.max may depend strongly on the type of qubits used in the quantum system. E.g. for superconducting qubits, T.sub.max may be 50 mK or below, preferably 1 mK or below.” Lechner ¶91. “According to embodiments, which can be combined with other embodiments described herein, the quantum system is maintained at an operating temperature of 50 mK or below, in particular 1 mK or below while the quantum annealing is performed.” Lechner ¶104.
In view of Lechner, choosing different, appropriate temperatures for the different quantum computations units would have been obvious to one of ordinary skill in the art before the effective filing date because the extreme temperatures required for operation are dependent upon the type of technologies used to implement the qubits.)
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Bertels, Bolt, and Rivi (Parallel Computing: a brief discussion, 2015).
9. (Original) The computer system according to claim 7, wherein the execution unit causes each of the plurality of computation units selected by the selection unit to synchronize computations executed by the respective plurality of computation units selected by the selection unit. (“To accommodate quantum processor development, we look at the experimental algorithms that the physics community are interested in, such as randomised (single and double) qubit gates. This phase would also comprise of hardware assessment and characterisation to meet the timing-precision and signal synchronisation requirements for a specific qubit-technology.” Bertels P. 9.
Bertels does not expressly teach synchronous computations.
Rivi teaches “Parallel computing is the simultaneous use of multiple compute resources to solve a computational problem: – A problem is broken into discrete parts that can be solved concurrently. – Instructions from each part executed simultaneously on different cores.” Rivi P. 2. “Dependencies [d]ictate the order of operations, imposes limits on parallelism and requires parallel synchronisation.” Rivi P. 10.
It would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teaching of Rivi with the previously cited art because synchronization of computations allows correct parallel processing of dependent data, which reduces the time of some calculations.
Response to Arguments
Applicant's arguments filed 11/18/2025 have been fully considered but they are not persuasive.
Examiner thanks Applicant for the clear, well-written remarks.
Rejections under §§ 112a and 112b of claims found to invoke §112f
Four separate structures are claimed using language interpreted under § 112f. Applicant asserts that all means plus function language is supported by algorithms in the Specification. Applicant cites to various paragraphs in the Specification, but no language describing any algorithm is found in the Remarks.
The limitation “acquisition unit that acquires” does not appear to have been addressed in the Remarks.
Applicant asserts that paragraphs 58-60 provide supporting structure for “computation unit(s) . . . to execute computation.” Given the generic language in these paragraphs and the lack of any specific supporting description convincing enough to include in the Remarks, this is not convincing.
Applicant asserts that the structural support for the claimed “selection unit that selects” is found in the lookup table of paragraphs 42-44. Rem. 7. A lookup table is not an algorithm. No algorithm has been provided which would result in a special purpose machine.
Applicant asserts that structural support for “execution unit that causes . . . to execute computation” is found in the operations of issuing instructions for execution of computation by the computation units. “The specification must explicitly disclose the algorithm for performing the claimed function, and simply reciting the claimed function in the specification will not be a sufficient disclosure for an algorithm which, by definition, must contain a sequence of steps. Blackboard, 574 F.3d at 1384, 91 USPQ2d at 1492 (stating that language that simply describes the function to be performed describes an outcome, not a means for achieving that outcome); Microsoft Computer Dictionary, Microsoft Press, 5th edition, 2002; see also Encyclopaedia Britannica, Inc. v. Alpine Elecs., Inc., 355 Fed. App'x 389, 394-95 (Fed. Cir. 2009) (holding that implicit or inherent disclosure of a class of algorithms for performing the claimed functions is not sufficient, and the purported "one-step" algorithm is not an algorithm at all) (unpublished).” MPEP § 2181.
Rejections under § 112b
All rejections under this section of claims not invoking §112f are withdrawn in response to claim amendments.
Rejections under § 103
Applicant submits that Bolt cannot teach the claimed subject matter because bolt fails to automate selection of specific quantum hardware or computation units from a group. Notably absent from this section of the remarks is any claim language requiring this functionality. The claims recite “aquir[ing] computation details” and “select[ing] a computation unit . . . based on the computation details[.]” It is unclear why a human providing a portion of the computation details would be inconsistent with this claim language, especially given the supporting description in paragraphs 38-40 of the Specification (“Specifically, the display unit 105 displays various kinds of computation details, and displays a screen enabling a user to specify computation details in various forms such as a checkbox, scrolling, and pull-down. [0039] The input unit 110 receives input of various kinds of information according to operation performed by the user. For example, the input unit 110 receives computation details according to operation performed by the user. In this case, the input unit 110 may receive a plurality of computation details. Various kinds of information received by the input unit 110 are transmitted to the processing unit 120. [0040] The processing unit 120 executes various kinds of processing. Specifically, the processing unit 120 can select a computation unit from the group of computation units, and give an instruction to the measurement device 20 such that the selected computation unit executes computation.”)
The Remarks assert that the technical problems addressed in Bolt and Bertels are “significantly different” and concludes that “a person of ordinary skill in the art should not have been simply motivated to apply the teaching of Bolt to modify the architecture of Bertels in the manner assumed in the Office Action.” Rem. 9. It is not clear whether Applicant is arguing against the motivation to combine or arguing that the references are non-analogous art. The Remarks assume “work beyond the disclosures of the references” required to integrate Bolt’s “user-facing selection process . . . into a hardware architecture like that of Bertels[.]” Rem. 9. But the Remarks do not explain why “user-facing” would be inconsistent with “hardware architecture.”
The Remarks asserts that Bertels does not teach computation units becoming asynchronous to each other. See Rem. 10. Admittedly, the rejection partly relies on art cited in the rejection of claims from which claim 8 depends. Figures 1 and 2a both show multiple different qubit technologies implemented as part of an accelerator. (Both figures were cited for this teaching in the rejection of claim 1.) The reference explains “signal synchronisation requirements for a specific qubit-technology.” Bertels P. 9. Note that qubit technology specific synchronization implies that different qubit technologies would not be synchronized with each other. See e.g. Figs. 1 and 2a showing hardware accelerators including more than one type of qubit technology.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PAUL M KNIGHT whose telephone number is (571) 272-8646. The examiner can normally be reached Monday - Friday 9-5 ET.
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PAUL M. KNIGHTExaminerArt Unit 2148
/PAUL M KNIGHT/Examiner, Art Unit 2148