DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Style
In this action unitalicized bold is used for claim language, while italicized bold is used for emphasis.
Specification
The amended title filed 06/08/2026 is entered.
Applicant Reply
“The claims may be amended by canceling particular claims, by presenting new claims, or by rewriting particular claims as indicated in 37 CFR 1.121(c). The requirements of 37 CFR 1.111(b) must be complied with by pointing out the specific distinctions believed to render the claims patentable over the references in presenting arguments in support of new claims and amendments. . . . The prompt development of a clear issue requires that the replies of the applicant meet the objections to and rejections of the claims. Applicant should also specifically point out the support for any amendments made to the disclosure. See MPEP § 2163.06. . . . An amendment which does not comply with the provisions of 37 CFR 1.121(b), (c), (d), and (h) may be held not fully responsive. See MPEP § 714.” MPEP § 714.02. Generic statements or listing of numerous paragraphs do not “specifically point out the support for” claim amendments. “With respect to newly added or amended claims, applicant should show support in the original disclosure for the new or amended claims. See, e.g., Hyatt v. Dudas, 492 F.3d 1365, 1370, n.4, 83 USPQ2d 1373, 1376, n.4 (Fed. Cir. 2007) (citing MPEP § 2163.04 which provides that a ‘simple statement such as ‘applicant has not pointed out where the new (or amended) claim is supported, nor does there appear to be a written description of the claim limitation ‘___’ in the application as filed’ may be sufficient where the claim is a new or amended claim, the support for the limitation is not apparent, and applicant has not pointed out where the limitation is supported.’)” MPEP § 2163(II)(A).
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 7-9 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claim 7 recites “wherein the processor is configured to select two or more computation units from the plurality of computation units, and transmit the instruction that instructs the two or more computation units to execute the computation performed by the two or more computation units.” Claim 7 depends directly from claim 1. The only plausible antecedent basis for “the instruction” in claim 7, is “an instruction that instructs the computation unit to execute the computation performed by the computation unit” in claim 7. As can be seen, “an instruction that instructs the computation unit” is structurally different than “the instruction that instructs the two or more computation units.” It is not clear whether claim 7 recites a new instruction, or if “an instruction” in claim 1 provides antecedent basis. Note that if claim 1 provides antecedent basis, the claim reads on a plurality of instructions associated with the two or more computation units. If the single instruction of claim 1 further instructs an additional, computation unit, this may be expressly claimed.
All dependent claims are rejected as containing the limitations of the claims from which they depend.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5, 7-8, and 10-12 are rejected under 35 U.S.C. 103 as being unpatentable over (Bertels Quantum Computer Architecture: Towards Full-Stack Quantum Accelerators), Bolt (US 2021/0158232), and Sarangi (Faster access to custom data with lookup tables, 2017).
1. (Original) A computer system comprising: (“Given the recent insights leading to e.g. Noisy Intermediate-Scale Quantum (NISQ) technology as expressed in [2], we are much more inclined to believe that the first industry-based and societal relevant application will be a hybrid combination of a classical computer and a quantum accelerator. It is based on the idea that any end-application contains multiple computational kernels and the properties of these parts are better executed by a particular accelerator which can be, as shown in Figure 1, either field-programmable gate arrays (FPGA), graphics-processing units (GPU), neural processing units (NPU) like Google's tensor processing unit, etc. The formal definition of an accelerator is indeed a co-processor linked to the central processor that is capable of accelerating the execution of specific computational intensive kernels, as to speed up the overall execution according to Amdahl's law. We now add two classes of quantum accelerator as additional co-processors. The first one is based on quantum gates and the second is based on quantum annealing. The classical host processor keeps the control over the total system and delegates the execution of certain parts to the available accelerators.” Bertels P. 1.) a quantum computer including a plurality of computation units, each computation unit of the plurality of computation units configured to execute computation using quantum effects in a superconducting state or thermal effects in a superconducting state; and (The Specification offers quantum annealing as an example of the claimed executing computation using quantum in a superconducting state or thermal effects in a superconducting state. Spec. ¶66. (“The computation unit has a superconducting material, and executes computation using quantum effects or thermal effects in the superconducting state. More specifically, the computation unit can execute computation using quantum annealing or other methods when the temperature of the computation unit is equal to or lower than the superconducting temperature of the superconducting material.”) Bertels teaches “We now add two classes of quantum accelerator as additional co-processors. The first one is based on quantum gates and the second is based on quantum annealing.” Bertels P. 1. See also Fig. 2(a) of Bertels showing four different types of qubits in a quantum accelerator and P. 16 teaching implementation of quantum annealing using superconducting qubits.) acquire computation details of a computation to be performed, (Bertels does not expressly teach acquiring computation details.
“The one or more computing devices that implement the quantum computing service are configured to receive, from a customer of the quantum computing service, a definition of a quantum computing object to be executed and select at least one of the first or second quantum hardware providers to execute the quantum computing object.” Bolt ¶35. “[0119] For example, a set of interactions exchanged between a customer and a quantum algorithm development kit to design and execute a quantum task/algorithm/circuit may include the interactions shown in 420 through 434. . . . [0120] For example, at 420 customer 418 may select a design paradigm to use to define a quantum object (e.g. quantum task/algorithm/circuit) to be submitted to the quantum computing service for execution on a quantum computer of a quantum hardware provider or a simulator. At 422, customer 418 may provide a definition for the quantum object using the selected design paradigm. For example customer 418 may define the quantum object in the design space 404 using the various tools available for use in the different design paradigms. . . . [0121] At 424, customer 418 may request to simulate the quantum object defined in design space 404 by selecting simulation button 412. At 426, the quantum algorithm development kit 114 may provide customer 418 with simulation results. For example, the simulation results may be displayed in design space 404. Also, at 428 the quantum algorithm development kit 114 may provide customer 418 with a performance/cost estimate and/or a recommendation. For example, in response to the customer 418 selecting cost/performance estimation/recommendation button 414. . . . [0122] At 430, customer 418 may select a quantum hardware provider and/or quantum computer type to be used to execute the quantum object defined by the customer 418.” Bolt ¶¶ 119-122.
It would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teaching of Bolt because acquiring the computation details allows the system to determine which quantum hardware has the least cost for a given quantum task/algorithm/circuit.) select, by referring to a table stored in a storage unit, the table associating each computation unit of the plurality of computation units with a computation performed by the computation unit, a computation unit from the plurality of computation units for which the computation details of the computation to be performed matches the computation performed by the computation unit, (“The method also includes selecting, by the quantum computing service, at least one of a first quantum hardware provider or a second quantum hardware provider to perform the quantum computing task, wherein the first quantum hardware provider and the second quantum hardware provider are configured to execute quantum computing tasks using quantum computers based on different quantum computing technologies.” Bolt ¶37. “[0145] At 902, the quantum computing service receives a definition of a quantum object to be executed by the quantum computing service using a quantum computer of a quantum hardware provider. For example, the quantum object may be a quantum task defined via a problem-domain paradigm interface, a quantum algorithm defined via a quantum algorithm design interface, a quantum circuit defined via a quantum circuit design interface, etc. [0146] At 904, the quantum computing service provides a recommendation to the customer regarding a recommended quantum hardware provider to use to execute the quantum object. [0147] At 906, the quantum computing service receives a customer selection of a quantum hardware provider to use to execute the quantum object. In some embodiments, the selection may simply accept the recommendation of the quantum computing service, or may specify various details, such as what type of quantum computer technology to use or a particular quantum hardware provider to use to execute the customer's quantum object.” Bolt ¶145-147. See also Bolt ¶¶149-153 and Fig. 9, teaching quantum hardware providers that are associated with specific technologies (e.g. annealing/ion-trap/superconducting type quantum computers.)
Bertels does not teach using a reference table.
Sarangi teaches “Lookup tables are a powerful and useful means of referencing frequently used custom data with no dependency on external apps/databases.” Sarangi p. 1. “By using lookup tables in a recipe you can simplify the integration, ensure data integrity and eliminate the need for complex formulas/code.” Sarangi p. 2. “In the simplest form lookup tables are two-dimensional data structures containing key-value pairs that allow faster access using a known key.” Sarangi p. 3.
It would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teaching of Sarangi as an instance of applying a known technique to a known device (method, or product) ready for improvement to yield predictable results. The prior art contained a "base" device (method, or product) upon which the claimed invention can be seen as an "improvement”. (The use of a lookup table data structure to hold the information associating the quantum task and quantum hardware (of Bertels) allows fast lookup of the information.) The prior art contained a known technique that is applicable to the base device (method, or product) (storing associated data in a lookup table is applicable to the combined teaching of the previously cited art.) One of ordinary skill in the art would have recognized that applying the known technique would have yielded predictable results and resulted in an improved system. (One of ordinary skill in the art would have recognized that applying the known technique of storing associated data in a lookup table would be a fast way to access the information.) See MPEP § 2143(I)(D).) and transmit an instruction that instructs the computation unit to execute the computation performed by the computation unit. (Bolt teaches “[0154] In some embodiments, a quantum computing service may define quantum objects using an intermediate representation and then translate the quantum objects into quantum hardware specific quantum circuit representations before making the quantum circuits available to be transported to an edge computing device at a quantum hardware provider location for execution on a quantum computer of the quantum hardware provider.” Bolt ¶154. One of ordinary skill in the art would understand the sending of a hardware specific quantum circuit representation for execution on a quantum computer as teaching an instruction to execute the hardware specific quantum circuit.)
2. (Original) The computer system according to claim 1, wherein the plurality of computation units includes a general-purpose computation unit that is a computation unit configured to execute general computations and a specific computation unit that is a computation unit configured to execute a specific computation, (“The history of computer architecture dates back various decades and has been very evolving. An important extension is the emergence of accelerators [1] as specialised processing units to which the host processor offloads suitable computational tasks.” Bertels P. 1. The “general-purpose computation unit” reads on the host processor. See also Bertels Fig. 1 showing a host CPU connected to various processing units. Alternatively, the “general-purpose computation unit” also reads on the FPGA and GPU in Fig. 1.) and wherein the processor is configured to select the general-purpose computation unit if the plurality of computation units does not include a specific computation unit configured to execute the computation to be performed, and select the specific computation unit if the plurality of computation units includes the specific computation unit configured to execute the computation to be performed. (“Given the recent insights leading to e.g. Noisy Intermediate-Scale Quantum (NISQ) technology as expressed in [2], we are much more inclined to believe that the first industry-based and societal relevant application will be a hybrid combination of a classical computer and a quantum accelerator. It is based on the idea that any end-application contains multiple computational kernels and the properties of these parts are better executed by a particular accelerator which can be, as shown in Figure 1, either field-programmable gate arrays (FPGA), graphics-processing units (GPU), neural processing units (NPU) like Google's tensor processing unit, etc. The formal definition of an accelerator is indeed a co-processor linked to the central processor that is capable of accelerating the execution of specific computational intensive kernels, as to speed up the overall execution according to Amdahl's law. We now add two classes of quantum accelerator as additional co-processors. The first one is based on quantum gates and the second is based on quantum annealing. The classical host processor keeps the control over the total system and delegates the execution of certain parts to the available accelerators.” Bertels P. 1. Note also that figure 2 of Bertels shows multiple types of qbits.)
3. (Original) The computer system according to claim 1, wherein the plurality of computation units includes a plurality of specific computation units configured to execute different computations, and wherein processor is configured to select selects a specific computation unit details among the plurality of specific computation units configured to execute the computation to be performed. (“We believe that the choice of the quantum accelerator is dependent on the specific energy landscape of the application, as well as the characteristics of the quantum systems (e.g. annealers can process larger problem sizes, whereas gate models allow longer coherence times).” Bertels P. 14.)
4. (Currently Amended) The computer system according to claim 1, wherein the plurality of computation units is formed on a same board. (See Bertels Fig. 2. In addition to being taught in the prior art, placing the computation units on the same or on different boards is obvious as a design choice. As explained in the application, using the same board results in simpler wiring and lower latency while using different boards allows the use of media with different temperature requirements. See Spec. ¶¶101, 111. This describes a routine design trade-off. Further, since both options are separately claimed to the exclusion of the other, it seems unlikely that either is critical to the function of the invention. Neither is described consistent with any novel or unexpected result.)
5. (Currently Amended) The computer system according to claim 1, wherein the plurality of computation units is formed on different boards. (See Bertels Figure 1 showing a separate quantum annealer and gate-based QC. In addition to being taught in the prior art, placing the computation units on the same or on different boards is obvious as a design choice. As explained in the application, using the same board results in simpler wiring and lower latency while using different boards allows the use of media with different temperature requirements. See Spec. ¶¶101, 111. This describes a routine design trade-off. Further, since both options are separately claimed to the exclusion of the other, it seems unlikely that either is critical to the function of the invention. Neither is described consistent with any novel or unexpected result.)
7. (Currently Amended) The computer system according to claim 1, wherein the processor is configured to select two or more computation units from the plurality of computation units, and transmit the instruction that instructs the two or more computation units to execute the computation performed by the two or more computation units. (See rejection of claim 1. Note that both Bertels and Bolt are directed to repeating processes, including selection of various computing units. Further, claim 7 recites “the instruction that instructs the two or more computation units to execute the computation performed by the two or more computation units.” Antecedent basis for “the instruction” appears to be “an instruction that instructs the computation unit to execute the computation performed by the computation unit.” Based on the antecedent language, “the instruction” refers to an instruction that instructs “the computation unit.” As best understood, the claim recites one instruction per computation unit, based on the antecedent form. (Note that there would not be any antecedent basis for “the instruction” if it were interpreted as “instruct . . . two or more computation units” because there is no antecedent basis for an instruction having that structure.)
8. (Original) The computer system according to claim 7, wherein the instruction causes the two or more computation units to execute the computation performed by the two or more computation units asynchronous from each other. (Bertels teaches “Real and realistic qubits: To accommodate quantum processor development, we look at the experimental algorithms that the physics community are interested in, such as randomised (single and double) qubit gates. This phase would also comprise of hardware assessment and characterisation to meet the timing-precision and signal synchronisation requirements for a specific qubit-technology. Bertels P. 9. Note that qubit technology specific synchronization implies that different qubit technologies would not be synchronized with each other. See e.g. Figs. 1 and 2a showing hardware accelerators including more than one type of qubit technology. Further, based on the specification, executing the computation units asynchronously or synchronously does not appear to exhibit any criticality, with respect to the invention. The claim mentions using both, in various locations in the Specification. In each location, the Specification indicates that either asynchronous or synchronous could be used. Notably, the only advantage attributed to asynchronous execution is “freer timing.”. See Spec. ¶¶99-100. No further explanation is offered. See also Spec. ¶¶20-20, 62-63, and 123-124. Further, claims to both alternatives indicate that neither alternative is critical to the invention. See claims 8 and 9. Therefore, in addition to being obvious based on the prior art, both synchronous and asynchronous operations, as claimed, are obvious design choices.)
For claim 10, see rejection of claim 1.
For claim 11, see rejection of claim 2.
For claim 12, see rejection of claim 3.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Bertels, Bolt, Sarangi, and Lechner (EP 3113084, published 2017)
6. (Original) The computer system according to claim 5, wherein on the different include boards of different temperatures, and wherein each computation unit of the plurality of computation units formed on the different boards is formed on a board of a temperature appropriate for the computation performed by each computation unit. (See Bertels Fig. 1 showing two types of quantum computation units.
Bertels does not expressly teach that the separate parts of the system of Figure 1 are kept at different temperatures.
Lechner teaches “The ground state of the final Hamiltonian may be a state of the quantum system at zero temperature. Not wishing to be bound by any particular theory, according to considerations in the field of quantum physics, it is considered impossible for a quantum system to reach a temperature of absolute zero. Still, evolving the quantum system from the initial quantum state towards the ground state of the final Hamiltonian, including e.g. cooling the quantum system to an operating temperature T.sub.max, may allow approaching the ground state of the final Hamiltonian. The operating temperature T.sub.max may depend strongly on the type of qubits used in the quantum system. E.g. for superconducting qubits, T.sub.max may be 50 mK or below, preferably 1 mK or below.” Lechner ¶91. “According to embodiments, which can be combined with other embodiments described herein, the quantum system is maintained at an operating temperature of 50 mK or below, in particular 1 mK or below while the quantum annealing is performed.” Lechner ¶104.
In view of Lechner, choosing different, appropriate temperatures for the different quantum computations units would have been obvious to one of ordinary skill in the art before the effective filing date because the extreme temperatures required for operation are dependent upon the type of technologies used to implement the qubits.)
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Bertels, Bolt, Sarangi, and Rivi (Parallel Computing: a brief discussion, 2015).
9. (Original) The computer system according to claim 7, wherein the instruction causes the two or more computation units to synchronize execution of the computation perfomed by the two or more computations units. (“To accommodate quantum processor development, we look at the experimental algorithms that the physics community are interested in, such as randomised (single and double) qubit gates. This phase would also comprise of hardware assessment and characterisation to meet the timing-precision and signal synchronisation requirements for a specific qubit-technology.” Bertels P. 9.
Bertels does not expressly teach synchronous computations.
Rivi teaches “Parallel computing is the simultaneous use of multiple compute resources to solve a computational problem: – A problem is broken into discrete parts that can be solved concurrently. – Instructions from each part executed simultaneously on different cores.” Rivi P. 2. “Dependencies [d]ictate the order of operations, imposes limits on parallelism and requires parallel synchronisation.” Rivi P. 10.
It would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teaching of Rivi with the previously cited art because synchronization of computations allows correct parallel processing of dependent data, which reduces the time of some calculations.
Further, based on the specification, executing the computation units asynchronously or synchronously does not appear to exhibit any criticality, with respect to the invention. The claim mentions using both, in various locations in the Specification. In each location, the Specification indicates that either asynchronous or synchronous could be used. Notably, the only advantage attributed to asynchronous execution is “freer timing.” See Spec. ¶¶99-100. No further explanation is offered. See also Spec. ¶¶20-20, 62-63, and 123-124. Further, claims to both alternatives indicate that neither alternative is critical to the invention. See claims 8 and 9. Therefore, in addition to being obvious based on the prior art, both synchronous and asynchronous operations, as claimed, are obvious design choices.)
Response to Arguments
Applicant's arguments filed 06/08/2026 have been fully considered but they are not persuasive.
Examiner thanks Applicant for the clear, well-written remarks.
Rejections under §§ 112a and 112b of claims found to invoke §112f
All language invoking interpretation under § 112f has been removed. The rejections based on that interpretation are withdrawn.
Rejections under § 103
Applicant asserts that the art cited in the previous action does not teach the table of the subsequently amended claims. See rejection above.
Applicant distinguishes synchronization requirements that are specific to a particular qubit technology from a system that “purposely causes the computations of selected computation units to be asynchronous with each other[,]” in reference to claim 8. Rem. 12. Applicant also notes “the fact that signal synchronization requirements are specific to a given qubit technology.” Rem. 12. There are several issues here. First, the claims do not recite Applicant’s purposeful causation in relation to asynchronous computations and this limitation is not read into the claims. See Rem. 12. This claim interpretation is bolstered by “the fact that signal synchronization requirements are specific to a given qubit technology.” Rem. 12. By extension, an instruction causing computations using computations units associated with different qubit technologies would cause asynchronous computations based on signal synchronization “specific to a given qubit technology.” Rem. 12. Therefore, the instruction only requires Applicant’s purposeful causation of the asynchronous computations to the extent that asynchronous communication is the natural result of computations carried out on computation units using different technologies. That brings us to the second issue. “[T]he fact that signal synchronization requirements are specific to a given qubit technology” implies that asynchronous communication between computation units is the natural result of carrying out operations using different qubit technologies. That is, a teaching of an instruction used to carry out operations using two different qubit technologies, where signal synchronization requirements are technology specific, naturally results in asynchronous operations being carried out between the different computation units, absent some form of synchronization. Third, one of ordinary skill in the art would also understand operations carried out using different technologies to be asynchronous, in part, because of the fact that synchronization is technology specific. For the second and third reasons, the cited art teaches the technique of claim 8.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PAUL M KNIGHT whose telephone number is (571) 272-8646. The examiner can normally be reached Monday - Friday 9-5 ET.
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PAUL M. KNIGHTPrimary ExaminerArt Unit 2148
/PAUL M KNIGHT/
Primary Examiner, Art Unit 2148
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