Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Acknowledgment
The amendment filed on 08/28/2025 has been entered. The present Office action is made with all the suggested amendments being fully considered.
Claims 1 and 18 have been amended.
New claims 19 and 20 have been added.
Accordingly, pending in this application are claims 1-20.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1 and 18 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Applicant asserts Toda fails to disclose, teach or suggest "wherein the second semiconductor material is selected from the group consisting of germanium (Ge), indium arsenide (InAs), indium gallium arsenide (InGaAs), aluminum gallium arsenide (AlGaAs), cadmium telluride (CdTe) and cadmium sulfur (CdS)" as claimed.
Examiner respectfully disagrees. The amendments added into claims 1 and 18 necessitated an updated search and new interpretation of the closest prior art.
As, described below, based on a new interpretation of fig. 41 of Toda, a stacked portion 13, 16 (¶0119) stacked on a surface on a light incident side of the substrate and including a second semiconductor material (e.g., layer 16 composed of cadmium sulfide (CdS); ¶295. Note: “including” is an open transitional phrase and does not exclude additional, unrecited elements. MPEP §2111.03, Section I: The transitional term "comprising", which is synonymous with "including," "containing," or "characterized by," is inclusive or open-ended and does not exclude additional, unrecited elements or method steps. See, e.g., Mars Inc. v. H.J. Heinz Co., 377 F.3d 1369, 1376, 71 USPQ2d 1837, 1843 (Fed. Cir. 2004).) different from the first semiconductor material (i.e., Si),
wherein the second semiconductor material (i.e., the material of layer 16) is selected from the group consisting of germanium (Ge), indium arsenide (InAs), indium gallium arsenide (InGaAs), aluminum gallium arsenide (AlGaAs), cadmium telluride (CdTe) and cadmium sulfur (CdS) (e.g., layer 16 composed of cadmium sulfide (CdS); ¶295).
Furthermore, Paul et al. (US 20220050184 A1) also discloses in fig. 1, wherein the second semiconductor material (i.e., the material of Germanium absorber layer 2) is selected from the group consisting of germanium (Ge) (¶90), indium arsenide (InAs), indium gallium arsenide (InGaAs), aluminum gallium arsenide (AlGaAs), cadmium telluride (CdTe) and cadmium sulfur (CdS).
Therefore, claims 1-20 stand rejected.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, and 17-18 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Paul et al. (US 20220050184 A1; hereinafter “Paul”).
In re claim 1, Paul discloses in fig. 1, a semiconductor device, comprising:
a plurality of pixels in each of which an avalanche photodiode element that photoelectrically converts incident light is formed (¶81, 45; “Ge-on-Si single-photon avalanche detectors”; “In the SPAD array, it is preferred that the array has at least 2×2 SPAD devices, at least 4×4 SPAD devices, or any other suitable array of SPAD devices”.),
wherein each of the plurality of pixels is provided with:
a substrate 4, 3 including a first semiconductor material (e.g., Silicon) (¶91-92); and
a stacked portion 2 stacked on a surface on a light incident side of the substrate (¶113; “the incident SWIR radiation is absorbed in the Ge absorption region and the signal amplification takes place in the Si multiplication region”. Therefore, stacked portion 2 is stacked on a surface that is light incident side of the substrate) and including a second semiconductor material (e.g., Germanium; ¶90) different from the first semiconductor material (i.e., Silicon),
wherein the second semiconductor material (i.e., the material of Germanium absorber layer 2) is selected from the group consisting of germanium (Ge) (¶90), indium arsenide (InAs), indium gallium arsenide (InGaAs), aluminum gallium arsenide (AlGaAs), cadmium telluride (CdTe) and cadmium sulfur (CdS).
In re claim 17, Paul discloses in fig. 1, wherein the plurality of pixels is provided with an antireflection unit that prevents reflection of the incident light (¶0117).
In re claim 18, Paul discloses in figs. 1, an electronic device (the SPAD device shown in fig. 1 used in automotive and autonomous vehicle LIDAR and a range of future quantum technology applications; ¶81) comprising:
a semiconductor device (fig. 1) provided with:
a plurality of pixels in each of which an avalanche photodiode element that photoelectrically converts incident light is formed (¶81, 45; “Ge-on-Si single-photon avalanche detectors”; “In the SPAD array, it is preferred that the array has at least 2×2 SPAD devices, at least 4×4 SPAD devices, or any other suitable array of SPAD devices”.),
wherein each of the plurality of pixels is provided with:
a substrate 4, 3 including a first semiconductor material (e.g., Silicon) (¶91-92); and
a stacked portion 2 stacked on a surface on a light incident side of the substrate (¶113; “the incident SWIR radiation is absorbed in the Ge absorption region and the signal amplification takes place in the Si multiplication region”. Therefore, stacked portion 2 is stacked on a surface that is light incident side of the substrate) and including a second semiconductor material (e.g., Germanium; ¶90) different from the first semiconductor material (i.e., Silicon),
wherein the second semiconductor material (i.e., the material of Germanium absorber layer 2) is selected from the group consisting of germanium (Ge) (¶90), indium arsenide (InAs), indium gallium arsenide (InGaAs), aluminum gallium arsenide (AlGaAs), cadmium telluride (CdTe) and cadmium sulfur (CdS).
Claim(s) 1-9, 16 and 18 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Toda et al. (US 20100182471 A1’ hereinafter “Toda”).
In re Claim 1, Toda discloses a semiconductor device 74 (fig. 41) comprising:
a plurality of pixels in each of which an avalanche photodiode element that photoelectrically converts incident light is formed,
wherein each of the plurality of pixels provided with:
a substrate (a substrate including layers 11, 12, 13, 16) including a first semiconductor material 11, 12 (e.g., Si) (¶0274); and
a stacked portion 13, 16 (¶0119) stacked on a surface on a light incident side of the substrate and including a second semiconductor material (e.g., layer 16 composed of cadmium sulfide (CdS); ¶295. Note: “including” is an open transitional phrase and does not exclude additional, unrecited elements. MPEP §2111.03, Section I: The transitional term "comprising", which is synonymous with "including," "containing," or "characterized by," is inclusive or open-ended and does not exclude additional, unrecited elements or method steps. See, e.g., Mars Inc. v. H.J. Heinz Co., 377 F.3d 1369, 1376, 71 USPQ2d 1837, 1843 (Fed. Cir. 2004).) different from the first semiconductor material (i.e., Si),
wherein the second semiconductor material (i.e., the material of layer 16) is selected from the group consisting of germanium (Ge), indium arsenide (InAs), indium gallium arsenide (InGaAs), aluminum gallium arsenide (AlGaAs), cadmium telluride (CdTe) and cadmium sulfur (CdS) (e.g., layer 16 composed of cadmium sulfide (CdS); ¶295).
In re claim 2, Toda discloses the semiconductor device according to claim 1 (fig. 41), wherein the substrate is provided with a multiplication unit including
a first electrode region of a first conductivity type 12 (e.g., p-Si electrode region) provided on a surface on a side opposite to the surface on the light incident side of the substrate, and
a second electrode region of a second conductivity type 11 (i.e., n-Si) provided so as to form a pn junction with the first electrode region, in which an avalanche multiplication region is formed on an interface of the pn junction (claims 6-8 of Toda).
In re claim 3, Toda discloses the semiconductor device according to claim 2 (fig. 33), wherein
the stacked portion 13 is a light absorption layer (see figs. 7, 14), and
the multiplication unit is a Geiger multiplication unit that performs avalanche multiplication on a carrier photoelectrically converted by the light absorption layer 13 (fig. 15; ¶0111 and claims 6-8 of Toda).
In re claim 4, Toda discloses the semiconductor device according to claim 2 (fig. 33), wherein the stacked portion 13 is a linear multiplication unit that performs avalanche multiplication on a photoelectrically converted carrier, and the multiplication unit 11, 12 is a Geiger multiplication unit that performs avalanche multiplication on carriers multiplied by the linear multiplication unit (claims 6-8 of Toda).
In re Claim 5, Toda discloses the semiconductor device according to claim 1, wherein
a readout circuit (shown as READOUT CIRCUIT) that reads carriers multiplied by the Geiger multiplication unit is further formed in the substrate.
Regarding the claim limitation “the stacked portion is a Geiger multiplication unit that performs avalanche multiplication on a photoelectrically converted carrier”: claim 5 is directed to an image sensor device, not to a method of operating and/or using the image sensor device. Since Toda discloses all the structural limitations of the image sensor device recited in claim 5, the method of operating and/or using the device of claim 5 does not distinguish it from the image sensor device taught by Toda.
MPEP § 2114-II states that a claim containing a “recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus” if the prior art apparatus teaches all the structural limitations of the claim. Ex parte Masham, 2 USPQ2d 1647 (Bd. Pat. App. & Inter. 1987). While features of an apparatus may be recited either structurally or functionally, claims directed to an apparatus must be distinguished from the prior art in terms of structure rather than function. In re Schreiber, 128 F.3d 1473, 1477-78, 44 USPQ2d 1429, 1431-32 (Fed. Cir. 1997); see also In re Swinehart, 439 F.2d 210, 212-13, 169 USPQ 226, 228-29 (CCPA 1971); In re Danly, 263 F.2d 844, 847, 120 USPQ 528, 531 (CCPA 1959). “[A]pparatus claims cover what a device is, not what a device does.” Hewlett-Packard Co. v. Bausch & Lomb Inc., 909 F.2d 1464, 1469, 15 USPQ2d 1525, 1528 (Fed. Cir. 1990).
In re claim 6, Toda discloses in (fig. 41) all the limitations of the semiconductor device of claim 3 upon which this claim depends. However, “wherein the stacked portion uses a substance crystal growth of which is possible as the second semiconductor material" pertains to be a product-by-process limitation and the process of forming the second semiconductor material does not distinguish the product from the prior art. Referring to MPEP §2113, regarding Product-by-Process Claims:
“[E]ven though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process.” In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985).”
“Once the examiner provides a rationale tending to show that the claimed product appears to be the same or similar to that of the prior art, although produced by a different process, the burden shifts to applicant to come forward with evidence establishing an unobvious difference between the claimed product and the prior art product. In re Marosi, 710 F.2d 798, 802, 218 USPQ 289, 292 (Fed. Cir. 1983)”.
Furthermore, Toda discloses (fig. 41) wherein the stacked portion 13 uses a substance crystal growth of which is possible as the second semiconductor material (¶0119, 0245).
In re claim 7, Toda discloses in (fig. 41) the semiconductor device according to claim 6, wherein the stacked portion 13, 16 has a stacked structure by the crystal growth including a transitional layer 21 (¶284).
In re claim 8, Toda discloses in (fig. 41) wherein the stacked portion 13, 16 has a stacked structure by lattice-matched crystal growth (¶0119, 0245).
Note: “wherein the stacked portion has a stacked structure by lattice-matched crystal growth" pertains to be a product-by-process limitation and the process of forming the stacked structure does not distinguish the product from the prior art. Referring to MPEP §2113, regarding Product-by-Process Claims:
“[E]ven though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process.” In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985).”
“Once the examiner provides a rationale tending to show that the claimed product appears to be the same or similar to that of the prior art, although produced by a different process, the burden shifts to applicant to come forward with evidence establishing an unobvious difference between the claimed product and the prior art product. In re Marosi, 710 F.2d 798, 802, 218 USPQ 289, 292 (Fed. Cir. 1983)”.
In re claim 9, Toda discloses in (fig. 41) the semiconductor device according to claim 8, wherein the stacked structure 13, 16 by the lattice-matched crystal growth is a quantum well type (¶0086, ¶0126; also see the band diagram shown in fig. 23) or quantum dot type stacked structure.
In re claim 16, Toda discloses the semiconductor device according to claim 1, further comprising: an on-chip lens provided on a light incident side of each of the plurality of pixels (¶0190).
In re claim 18, Toda discloses in figs. 45 and 41, an electronic device 201 (fig. 45) (¶314) comprising:
a semiconductor device 74 (fig. 41) (¶292-297) provided with:
a plurality of pixels in each of which an avalanche photodiode element that photoelectrically converts incident light is formed,
wherein each of the plurality of pixels provided with:
a substrate (a substrate including layers 11, 12, 13, 16) including a first semiconductor material 11, 12 (e.g., Si) (¶0274); and
a stacked portion 13, 16 (¶0119) stacked on a surface on a light incident side of the substrate and including a second semiconductor material (e.g., layer 16 composed of cadmium sulfide (CdS); ¶295. Note: “including” is an open transitional phrase and does not exclude additional, unrecited elements. MPEP §2111.03, Section I: The transitional term "comprising", which is synonymous with "including," "containing," or "characterized by," is inclusive or open-ended and does not exclude additional, unrecited elements or method steps. See, e.g., Mars Inc. v. H.J. Heinz Co., 377 F.3d 1369, 1376, 71 USPQ2d 1837, 1843 (Fed. Cir. 2004).) different from the first semiconductor material (i.e., Si),
wherein the second semiconductor material (i.e., the material of layer 16) is selected from the group consisting of germanium (Ge), indium arsenide (InAs), indium gallium arsenide (InGaAs), aluminum gallium arsenide (AlGaAs), cadmium telluride (CdTe) and cadmium sulfur (CdS) (e.g., layer 16 composed of cadmium sulfide (CdS); ¶295).
In re claim 19, Toda discloses the electronic device according to claim 19 (fig. 41), wherein the substrate is provided with a multiplication unit including
a first electrode region of a first conductivity type 12 (e.g., p-Si electrode region) provided on a surface on a side opposite to the surface on the light incident side of the substrate, and
a second electrode region of a second conductivity type 11 (i.e., n-Si) provided so as to form a pn junction with the first electrode region, in which an avalanche multiplication region is formed on an interface of the pn junction (claims 6-8 of Toda).
In re claim 20, Toda discloses the electronic device according to claim 19 (fig. 41), wherein
the stacked portion 13 is a light absorption layer (see figs. 7, 14), and
the multiplication unit is a Geiger multiplication unit that performs avalanche multiplication on a carrier photoelectrically converted by the light absorption layer 13 (fig. 15; ¶0111 and claims 6-8 of Toda).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Toda, as applied to claim 3 above and further in view of Miller et al. (US 20210263155 A1; hereinafter “Miller”)
In re claim 10, Toda discloses the semiconductor device according to claim 3 outlined above.
Toda does not expressly disclose wherein the stacked portion uses a nano crystal as the second semiconductor material.
In the same field of endeavor, Miller discloses a semiconductor device (fig. 3d) wherein the stacked portion 313, 325, 309b uses a nano crystal as the second semiconductor material (¶0107: “the features of the reflective diffractive region comprise one or more of cones, pyramids, pillars, protrusions, micro-lenses, quantum dots, nanoparticles, inverted features and the like.”).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to employ the teachings of Miller into the semiconductor device of Toda to redirect incident electromagnetic radiation (¶0107 of Miller).
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Toda, as applied to claim 3 above and further in view of Kato et al. (US 20190088693 A1; hereinafter “Kato”).
In re claim 11, Toda discloses the semiconductor device according to claim 3 outlined above.
Toda does not expressly disclose
In the same field of endeavor, Kato discloses a semiconductor device (fig. 8) wherein the stacked portion uses an organic film 12 as the second semiconductor material.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to employ the teachings of Kato into the semiconductor device of Toda to utilize a stacking option for different colors and have a reduction in size of the chip area of the solid-state imaging device.
Claim(s) 12-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Toda, as applied to claim 1 above and further in view of Kobayashi et al. (US 20190181177 A1; hereinafter “Kobayashi”).
In re claim 12, Toda discloses the semiconductor device according to claim 1 outlined above.
Toda does not expressly disclose the device further comprising: a pixel isolation unit that insulates and isolates a plurality of adjacent pixels from each other.
In the same field of endeavor, Kobayashi discloses a semiconductor device (figs. 1-2) comprising: a pixel isolation unit 39 that insulates and isolates a plurality of adjacent pixels 21 from each other (¶0115-0118).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to employ the teachings of Kobayashi into the semiconductor device of Toda to independently operate adjacent pixels (¶0116 of Kobayashi).
In re claim 13, Toda, as modified by Kobayashi, discloses the semiconductor device according to claim 12, wherein the pixel isolation unit 39 performs pixel isolation by a full trench formed from the substrate to the stacked portion (Kobayashi: figs. 1-2).
In re claim 14, Toda, as modified by Kobayashi, discloses the semiconductor device according to claim 12, wherein the pixel isolation unit 39 performs pixel isolation by a rear surface trench formed in the stacked portion (Kobayashi: figs. 1-2).
In re claim 15, Toda, as modified by Kobayashi, discloses the semiconductor device according to claim 12, wherein the pixel isolation unit 39 performs pixel isolation by a front surface trench formed in the substrate 22 (Kobayashi: figs. 1-2).
Claim(s) 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Toda, as applied to claim 1 above and further in view of Paul et al. (US 20220050184 A1; hereinafter “Paul”).
In re claim 17, Toda discloses the semiconductor device according to claim 1 outlined above. Toda does not expressly disclose wherein the plurality of pixels is provided with an antireflection unit that prevents reflection of the incident light.
In the same field of endeavor, Paul discloses wherein the plurality of pixels is provided with an antireflection unit that prevents reflection of the incident light (¶0117).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to employ the teachings of Inoue into the semiconductor device of Toda to reduce dark count rates (¶0117 of Paul).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NILUFA RAHIM whose telephone number is (571)272-8926. The examiner can normally be reached M-F 9am-5:30pm EST.
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/NILUFA RAHIM/Primary Examiner, Art Unit 2893