Prosecution Insights
Last updated: October 25, 2026
Application No. 18/001,857

SOLID-STATE IMAGING DEVICE, METHOD OF MANUFACTURING THE SAME, AND ELECTRONIC DEVICE

Final Rejection §102§103
Filed
Dec 14, 2022
Priority
Jun 22, 2020 — JP 2020-106971 +1 more
Examiner
BELOUSOV, ALEXANDER
Art Unit
2818
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Sony Group Corporation
OA Round
2 (Final)
77%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
93%
With Interview

Examiner Intelligence

Grants 77% — above average
77%
Career Allowance Rate
402 granted / 525 resolved
+8.6% vs TC avg
Strong +16% interview lift
Without
With
+16.3%
Interview Lift
resolved cases with interview
Typical timeline
2y 11m
Avg Prosecution
29 currently pending
Career history
559
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
61.9%
+21.9% vs TC avg
§102
25.0%
-15.0% vs TC avg
§112
12.2%
-27.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 525 resolved cases

Office Action

§102 §103
DETAILED ACTION Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. Claims 1-6, 9-11, 13-17, 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by (US-2020/0098808) by Wu et al (“Wu”). Regarding claim 1, Wu discloses in FIG. 2 and related text, e.g., a solid-state imaging device, comprising: a semiconductor substrate (224) including a pixel (par. 25: “photodetectors … for pixel sensor array 208”), wherein the pixel includes a photoelectric conversion section (see par. 25); an on-chip lens (236; it is attached to chip; hence, “on-chip”) on a light incident surface side of the semiconductor substrate (see FIG. 3; it makes clear that light comes from top); a light-transmissive substrate (110; “protection layer”) that protects the on-chip lens (by definition); and a bonding resin (108, “on-wafer lens”; par. 42: “108 may be photoresist”; “resin” is a notoriously well-known material for “photoresist”; as evidence of Examiner’s assertion, see US-3,615,471, col. 3, lines 60-65; also, layer 108 physically bonds layer above (110) to layer below (130); hence, “bonding resin”, by definition; alternatively, if Applicant wishes to argue, forming 108 of a resin is at the very least obvious in light of explicit teachings provided above, in order to simplify the processing steps of making device, by forming the layer in a notoriously well-known way and from notoriously well-known materials) that bonds the light-transmissive substrate to the on-chip lens, wherein the light-transmissive substrate includes: a first surface (top of 110) on a light incident surface side of the light-transmissive substrate, wherein the first surface is flat (see FIG. 2), and a second surface (the bottom, uneven, surface of 110) opposite to the first surface of the light-transmissive substrate, the light-transmissive substrate has: a first thickness in a central region of the light-transmissive substrate (relatively thin in the center), wherein the central region faces a pixel region (directly under 236/234) of the semiconductor substrate, and a second thickness in an outer peripheral region of the light-transmissive substrate (relatively thick thickness near left and right edge of 110), the outer peripheral region is outside the central region (the relatively thick portions are not over 236/234; hence, meeting limitations), and the second thickness is different from the first thickness (see FIG. 2). Regarding claim 2, Wu discloses in FIG. 2 and related text, e.g., wherein the first thickness of the light-transmissive substrate (110) is thinner than the second thickness of the light- transmissive substrate (see FIG. 2). Regarding claim 3, Wu discloses in FIG. 2 and related text, e.g., wherein the bonding resin (108) has: a first thickness in a central region of the bonding resin (see FIG. 2; directly over 236/234), and a second thickness in an outer peripheral region of the bonding resin (area outside 236/234), and the second thickness of the bonding resin is different from the first thickness of the bonding resin (see FIG. 2). Regarding claim 4, Wu discloses in FIG. 2 and related text, e.g., wherein the first thickness of the bonding resin is thicker than the second thickness of the bonding resin (the thickness of 108 is relatively thick, directly above 236/234; the thickness of 108 is relatively thin, in an area where the numeral 236 is physically located on FIG. 2; hence, meeting limitations). Regarding claim 5, Wu discloses in FIG. 2 and related text, e.g., wherein the central region of the light-transmissive substrate (110) expanded outward from the pixel region by a specific width L (> 0) in a plan view of the solid-state imaging device (“central region” of 110 is considered to be every central area where thickness of 110 changes; “peripheral region” are the outer areas, to the left and right, where thickness does not change; thus, meeting limitations, since thus defined “central region” is wider than the 234/236). Regarding claim 6, Wu discloses in FIG. 2 and related text, e.g., wherein the light-transmissive substrate further includes a bottom surface (the bottom surface of 110 stretches from all the way on the left, to all the way on the right of 110), the specific width L is a distance between an end portion of the pixel region (the left and right edges of 236/234 are physical markers of that) and a corner portion of the outer peripheral region of the light-transmissive substrate (basically, what was described above, regarding claim 5), and the corner portion is inside the bottom surface of the light-transmissive substrate (by definition of bottom surface; furthermore, these limitations may merit 112, indefinite rejection; it is unclear how “the corner portion (a 3D object) is inside the bottom surface (a 2D object); this appears to violate physics, since 3D objects do not fit inside 2D objects; the other way make sense [Wingdings font/0xE0] 3D objects do have a whole bunch of 2D surfaces; but, not the way the claim limitations are stated). Regarding claim 9, Wu discloses in FIG. 2 and related text, e.g., wherein a planar shape of the outer peripheral region of the light-transmissive substrate is a rectangular shape (see FIG. 13). Regarding claim 10, Wu discloses in FIG. 2 and related text, e.g., wherein a planar shape of the outer peripheral region of the light-transmissive substrate is a line shape (see FIG. 13; the outer peripheral region shows a shape of 4 lines, 2 vertical and 2 horizontal), and and the line shape is along two sides of a rectangle in one of a left-right direction of the solid-state imaging device or an up-down direction of the solid-state imaging device (as mentioned above, both variants are taught by FIG. 13). Regarding claim 11, Wu discloses in FIG. 2 and related text, e.g., wherein a planar shape of the outer peripheral region of the light-transmissive substrate is a specific shape (see FIG. 13) and in the specific shape, an L shape is at each corner portion of a rectangle (see FIG. 13; all 4 corners have L shape). Regarding claim 13, Wu discloses in FIG. 2 and related text, e.g., further comprising an interlayer insulating film (130, “on-wafer filtering coating”; it is both “interlayer” (see FIG. 2) and “insulating” (see par. 19 for list of materials)) on the on-chip lens (see FIG. 2), wherein the bonding resin further bonds the light-transmissive substrate to the interlayer insulating film (see FIG. 2). Regarding claim 14, Wu discloses in FIG. 2 and related text, e.g., wherein the bonding resin bonds the light-transmissive substrate to the on-chip lens via the interlayer insulating film (see FIG. 2). Regarding claim 15, Wu discloses in FIG. 2 and related text, e.g., wherein the outer peripheral region of the light-transmissive substrate includes an inner peripheral side surface on a side of the central region of the light-transmissive substrate (see FIG. 2 and 110; the surface between the very center area and the very left/right edge area), and the inner peripheral side surface is in a tapered shape (see FIG. 2; from the center of “light-transmissive substrate” to the very edges of the same, the surface is being “tapered”; thus meeting limitations). Regarding claim 16, Wu discloses in FIG. 2 and related text, e.g., wherein the outer peripheral region of the light-transmissive substrate includes an inner peripheral side surface on a side of the central region of the light-transmissive substrate (see claim 15), and an upper portion of the inner peripheral side surface is in an arc shape (see FIG. 2; from the center of “light-transmissive substrate” to the very edges of the same, the two portions of the surface that are between center and edge, the surface is formed of arcs; one can arbitrarily split them into two arcs and they meet limitations). Regarding claim 17, Wu discloses in FIG. 2 and related text, e.g., wherein the outer peripheral region of the light-transmissive substrate includes an inner peripheral side surface on a side of the central region of the light-transmissive substrate (see claim 15), and an upper portion of the inner peripheral side surface and a lower portion of the inner peripheral side surface are formed in arc shapes (see FIG. 2; from the center of “light-transmissive substrate” to the very edges of the same, the two portions of the surface that are between center and edge, the surface is formed of arcs; one can arbitrarily split them into two arcs and they meet limitations). Regarding claim 20, Wu discloses in FIG. 2 and related text, e.g., an electronic device (see FIG. 3) comprising: a solid-state imaging device (see Abstract) including: a semiconductor substrate including a pixel, wherein the pixel includes a photoelectric conversion section (see claim 1); an on-chip lens on a light incident surface side of the semiconductor substrate (see claim 1); a light-transmissive substrate that protects the on-chip lens (see claim 1); and a bonding resin that bonds the light-transmissive substrate to the on-chip lens (see claim 1), wherein the light-transmissive substrate includes: a first surface on a light incident surface side of the light-transmissive substrate (see claim 1), wherein the first surface is flat (see claim 1), and a second surface opposite to the first surface of the light-transmissive substrate (see claim 1), the light-transmissive substrate has: a first thickness in a central region of the light-transmissive substrate, wherein the central region faces a pixel region of the semiconductor substrate (see claim 1), and a second thickness in an outer peripheral region of the light-transmissive substrate (see claim 1), the outer peripheral region is outside the central region (see claim 1), and the second thickness is different from the first thickness (see claim 1). Examiner’s Note: claim 20 appears to be identical to claim 1. That is against the rules of claim drafting. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over (US-9999999) by Wu et al (“Wu”). Regarding claim 7, Wu discloses in FIG. 2 and related text, e.g., substantially the entire claim structure, as recited in above claims, including wherein in a case where a difference between the first thickness of the light-transmissive substrate and the second thickness of the light-transmissive substrate is denoted by D, and a thickness of the bonding resin in a central region of the bonding resin is denoted by A (all by definition, since these only define features that were already discussed above). Wu does not explicitly state “a minimum value of the specific width L is L= Sqrt(2AD – D^2)”. To elaborate on the above, Wu most probably already meets the limitations, but just does not explicitly state that. To see it clearly, look at how the formula defines the “minimum L”: FIG. 1 shows Applicant’s “L” is just about 1.5 pixels wide, judging by the width of “on-chip lens 33” in the FIG. 1. Now compare to the equivalent “minimum L” in FIG. 2 of Wu; his “minimum L” is way more than 1.5 pixels wide; it appears to be 4 or 5 pixels wide. Hence, Wu most likely already meets the limitations. It would have been obvious to one of ordinary skill in the art at the time of the invention to modify the device of Wu with “a minimum value of the specific width L is L= Sqrt(2AD – D^2)”, (1) in order to use the imaging device of Wu of FIG. 2, in a situation, where the “supporting logic circuit” 210 is especially large (see FIG. 2 of Wu; it shows relatively narrow area 210; that is because this particular chip happens to have very little supporting logic; in a device that had, say, twice as much supporting logic 210, the 210 area would be twice as wide, an the overall “light-transmissive substrate 110 would be much wider; hence, the resultant “minimum L” would also be much wider; hence, inherently meeting the limitations of the formula, OR (2) in order to simply keep up with the march of technology; as is notoriously well-known to any reasonably informed member of the public, semiconductor industry is constantly shrinking the sizes of its devices, from arbitrarily larger sizes to arbitrarily smaller ones, over a period of 12-18 months (colloquially known as “Moore’s Law”, and it is often enough publicly discussed in popular media, such as CNN; hence, “any reasonably informed member of the public”); therefore, as feature sizes of devices shrink, from arbitrarily large numbers to arbitrarily small numbers, skilled artisan would be drawn to the wide ranging feature sizes for “light-transmissive substrate” and its “D” and “bonding resin” and its “A”, resulting in some of the devices inherently meeting the resultant “minimum L”, simply as a matter of march of technology, with no further consideration needed (to put it in another way, a trivial mathematical exercise is to put in realistic values for A and D, which will result in a tiny “minimum L”, resulting in a product that is already on the market automatically violating the above claimed formula). Also, noting that claim language states “wherein in a case where”, so simply if the difference did not meet the stated difference, the rest of the claim is not required, which would be the case in some instances of Wu. Examiner’s Note: certain patent claims present an existential threat to the semiconductor industry. This specific claim is one such claim. Various semiconductor companies have been meeting the limitations of the above formula for decades - as was explained above; as a matter of march of technology, from, say, 1980’s to the effective filing date - huge number of products undoubtedly met the above limitations, simply by choosing appropriate feature sizes, based on the usual design considerations. Now, the Applicant is trying to cover all such feature sizes with a formula. Thus, this particular patent claim creates an existential threat to the industry and a whole host of existing and future products. Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over (US-2020/0098808) by Wu et al (“Wu”) in view of (US-2015/0123227) by Ootsuka et al (“Ootsuka”). Regarding claim 8, Wu discloses in cited figures and related text, e.g., substantially the entire claim structure, as recited in above claims, except wherein the pixel region includes an effective pixel region and an OPB region. Ootsuka discloses in FIG. 33 and related text, e.g., “wherein the pixel region includes an effective pixel region (591) and an OPB region (592)”. It would have been obvious to one of ordinary skill in the art at the time of the invention to modify the device of Wu with “wherein the pixel region includes an effective pixel region and an OPB region” as taught by Ootsuka, in order to be used as a margin for reducing variations in process (par. 281). Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over (US-2020/0098808) by Wu et al (“Wu”) in view of (WO-2020/1717191) by Ooka et al (“Ooka”; for Applicant’s convenience, the rejection is written in terms of US-2022/0115427). Regarding claim 12, Wu discloses in FIG. 2 and related text, e.g., substantially the entire claim structure, as recited in above claims, including wherein the outer peripheral region of the light-transmissive substrate has a rectangular shape (see FIG. 13; having the “light-transmissive substrate” have rectangular shape, is at the very least obvious, in light of Wu’s explicit teachings, in order to simplify the processing steps of making device, by making the “light-transmissive substrate” match the shape of overall device), the outer peripheral region is thicker than the central region of the light-transmissive substrate (see FIG. 2). Wu does not disclose “the light-transmissive substrate has a recess in at least one of: an up-down direction of the outer peripheral region, and a left-right direction of the outer peripheral region”. Ooka discloses in FIG. 6 and related text, e.g., “the light-transmissive substrate (134) has a recess (142) in at least one of: an up-down direction of the outer peripheral region, and a left-right direction of the outer peripheral region (it is by definition one or the other; the sides were taught by Wu in FIG. 13; one of them (either up-down one or left-right one) has the recess 142, since Ooka shows it is present on the edge of the chip)”. It would have been obvious to one of ordinary skill in the art at the time of the invention to modify the device of Wu with “the light-transmissive substrate has a recess in at least one of: an up-down direction of the outer peripheral region, and a left-right direction of the outer peripheral region” as taught by Ooka, in order to allow for good alignment between the light-transmissive substrate and the underlying device (see par. 126). Response to Arguments Applicant’s arguments with respect to above claims have been considered but are moot because the arguments do not apply to the current rejection. Conclusion Additional references (if any) are cited on the PTO-892 as disclosing similar features to those of the instant invention. THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Alexander Belousov whose telephone number is (571)-272-3167. The examiner can normally be reached on 10 am-4 pm. If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Jeff Natalini can be reached on 571-272-2266. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Alexander Belousov/Patent Examiner, Art Unit 2894 09/30/26 /JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818
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Prosecution Timeline

Dec 14, 2022
Application Filed
Sep 25, 2025
Non-Final Rejection mailed — §102, §103
Apr 02, 2026
Response after Non-Final Action
Jun 08, 2026
Response Filed
Oct 05, 2026
Final Rejection mailed — §102, §103 (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
77%
Grant Probability
93%
With Interview (+16.3%)
2y 11m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 525 resolved cases by this examiner. Grant probability derived from career allowance rate.

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