Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed on 03/04/2026 have been fully considered but they are not persuasive. Regarding claims 1, 9, 18 and 19, Applicant argues that the cited references fail to teach “wherein the wiring formed in the second semiconductor substrate has a prismatic shape or cylindrical shape”. However, Hara teaches rectangular parallelepiped connection conductors 30a, 30b, 40a, 40b formed in a semiconductor wiring structure. A rectangular parallelepiped conductor is a prismatic conductor. Therefore, Hara teaches or at least renders obvious the claimed wiring having a prismatic shape. Accordingly, Applicant’s argument and amendments do not overcome the rejection, and the rejection is maintained.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 5 and 9-17 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 5 recites “wherein each of the first wiring and the second wiring is connected to two or more vias formed in second semiconductor substrate and is connected to a wiring formed having the prismatic shape or the cylindrical via the vias”. It is unclear whether Applicant intended to recite that the wiring has a “cylindrical shape” and is connected “via the vias”, or whether “cylindrical via” refers to a separate cylindrical via structure. For the purpose of examination, this limitation is interpretated as reciting that the wiring has a prismatic shape or cylindrical shape and is connected through the vias.
Claim 9 recites “…a second wiring connected to the second transfer transistor are provided on the side of the wiring layer…”. It is unclear whether it means “provided on the second surface side of the wiring layer”. For the purpose of examination, this limitation is interpretated as “…a second wiring connected to the second transfer transistor are provided on the second surface side of the wiring layer…”.
Claims 10-17 inherit the indefiniteness of claim 9 for being dependent on claim 9. Hence, they are also rejected under 35 U.S.C. 112(b).
Claim 14 recites “…each of the third wiring and the fourth wiring is connected to two or more vias formed in the semiconductor substrate…”. The phrase “two or more vias formed in the semiconductor substrate” lacks clear antecedent basis. Claim 9 recited both a first semiconductor substrate and a second semiconductor substrate, and it is unclear which substrate is intended by the “semiconductor substrate”. For the purpose of examination, this limitation is interpretated as “…each of the third wiring and the fourth wiring is connected to two or more vias formed in the second semiconductor substrate…”, because claim 14 further recites that the vias connect to wiring formed in the second semiconductor substrate.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 5, 7-12, 14, 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over Ikeda (US 20190006403 A1) in the view of Yanagita (US 20150179691 A1) and further in view of Hara (US 20210083182 A1).
Re: Independent Claim 1 (Currently amended), Ikeda discloses an imaging element comprising:
a first semiconductor substrate in which a plurality of pixels including are arranged in a matrix of rows and columns, wherein each pixel of the plurality of pixels includes a photodiode, a first transfer transistor configured to transfer a charge generated by the photodiode to a first charge accumulation section, and a second transfer transistor configured to transfer the charge generated by the photodiode to a second charge accumulation section (Ikeda, Fig 3, ¶ [0028] - [0029], Ikeda discloses and imaging device including a first semiconductor substrate on which a pixel portion 104 is formed. The pixel portion includes pixel P (x, y) arranged in rows and columns (a matrix). Each pixel P includes a photoelectric conversion unit 10 that is a photodiode, a first transfer transistor 11, a second transfer transistor 12, a first signal holding portion 14, and a second signal holding portion 15. Transfer transistor 11 transfers charge generated in the photoelectric conversion unit 10 to signal holding portion 14, and transfer transistor 12 transfers charge generated in the photoelectric conversion unit 10 to signal holding portion 15).
Regarding the limitation: “a wiring layer laminated on the first semiconductor substrate wherein the wiring layer includes a first surface facing the first semiconductor substrate and a second surface facing opposite to the first surface; and a second semiconductor substrate laminated on the second surface of the wiring layer”, (Ikeda Fig. 4, ¶ [0040]) Ikeda discloses that the first substrate and the second substrate are connected by wiring provided as a line 130 arranged between the two substrates which connects circuitry on the first and second substrate, and in another embodiment by a line 47 passing through an interlayer insulating film 46 between the substrates.
Ikeda is silent regarding explicitly describing this inter-substrate wiring structure as "a wiring layer laminated on the first semiconductor substrate wherein the wiring layer includes a first surface facing the first semiconductor substrate and a second surface facing opposite to the first surface; and a second semiconductor substrate laminated on the second surface of the wiring layer".
However, Yanagita teaches, in Fig 3 and ¶ [0044], a sensor substrate 3 (semiconductor substrate), on which a first wiring layer 31 formed. Yanagita further teaches circuit substrate 9 corresponding to a second semiconductor substrate, and second wiring layer 41 formed on circuit substrate 9, and that the first wiring layer 31 and second wiring layer 41 are positioned between sensor substrate 3 and a circuit substrate 9. Yanagita further teaches surface electrodes on the wiring layers that electrically connect the sensor substrate side to the circuit substrate side. Thus, Yanagita teaches a laminating wiring-layer having a first surface facing the sensor substrate and an opposite surface facing the circuit substrate 9; and teaches laminating/coupling a second substrate on the second-surface side of the wiring layer. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to implement Ikeda's second substrate as a circuit substrate laminated on the second surface side of the wiring layer, as taught by Yanagita, in order to provide a conventional stacked image-sensor wiring architecture in which a pixel substrate and a circuit substrate are electrically connected through wiring layers positioned between the substrates.
Regarding the limitation: “wherein a first wiring connected to the first transfer transistor of the plurality of pixels arranged in a row direction or a column direction and a second wiring connected to the second transfer transistor of the plurality of pixels provided on the second surface of the wiring layer”, Ikeda also discloses that the pixel matrix 104 includes pixels P(x,y) with first and second transfer transistors 11 and 12 is driven by a vertical scanning unit 103. A person of ordinary skill would understand that this vertical scanning unit 103 that transfer-control signals are supplied to the gates of transfer transistors of pixel arranged in rows and/or columns. Thus, Ikeda teaches or at least suggest separate transfer-control wiring paths for controlling first transfer transistors 11 and second transfer transistors 12 of plural pixels arranged in rows or columns.
Ikeda is silent regarding explicitly describing these transfer-control wiring paths as a first wiring connected to the first transfer transistors of pixels in a row or a column direction and a second wiring connected to the second transfer transistor of pixels, and is further silent regarding such first and second wirings being provided on the second surfaces of a wiring layer.
However, Yanagita teaches a transfer-gate wiring connection architecture in a stacked imaging device. In particular, Yanagita teaches, in Fig 5 and ¶¶ [0078] - [0080] that TRG wiring 38 crosses pixel area 12, passes over transfer gate electrodes 21-24, and is connected to corresponding transfer gate electrodes. Yanagita further teaches that the TRG wiring 38 is connected through plug 34 to a third electrode 39 formed on a surface of first wiring layer 31 of sensor substrate 3, and that third electrode 39 is connected to fourth electrode 49 formed on a surface of second wiring layer 41 of circuit substrate 9. The fourth electrode 49 is further connected to circuitry on the circuit substrate side through plugs 42, 44, and wiring 48. Thus, Yanagita teaches arranging a transfer-control wiring path, including a transfer-gate wiring and a surface -side electrode/wiring portion electrically continuous with the transfer-gate wiring, at the surface side of the wiring layer facing the circuit substrate. Accordingly, the conductive wiring/electrode portions that are part of, and electrically continuous with, transfer-control wiring paths connected to the respective transfer transistors correspond to the claimed first wiring and second wiring. Hence, Yanagita teaches providing a transfer-control wiring/electrode portion on the second surface side of the first wiring layer 31. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to implement Ikeda’s first and second-transfer-control wiring paths for first and second transfer transistors 11 and 12 using Yanagita’s surface-side transfer-control wiring/electrodes connection arrangement, such that a first wiring connected to the first transfer transistors 11 and a second wiring connected to second transfer transistor 12 are provided on the second-surface side of the wiring layer, in order to route transfer-control signals between stacked substrates, increase wiring density, and secure reliable electrical connection between the pixel substrate and the circuit substrate.
Regarding the limitation “wherein each of the first wiring and the second wiring is electrically connected to a wiring formed in the second semiconductor substrate”, Ikeda discloses that the first and second transfer transistors 11 and 12 are driven by vertical scanning unit 103. Ikeda is silent regarding explicitly describing each of the first wiring and second wiring as being electrically connected to a wiring formed in the second semiconductor substrate.
However, Yanagita teaches that transfer-control wiring on the sensor-substrate side is electrically connected to circuitry on the circuit-substrate side. Specifically, Yanagita teaches, in Fig, 6C and ¶ [0083], that TRG wiring 38 is connected to third electrode 39 through plug 34, third electrode 39 is connected to fourth electrode 49 on the circuit-substrate-side wiring layer, and the fourth electrode 49 is connected to a circuit element formed on substrate 9 through plugs 42, 44 and wiring 48. Therefore, Yanagita teaches electrically connecting a transfer-control wiring/electrode structure on the sensor-substrate side to wiring/circuitry formed on the second semiconductor substrate side.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to electrically connect Ikeda’s first and second transfer-control wirings to corresponding wirings formed in or associated with the second semiconductor substrate using Yanagita’s surface electrode, plug, and wiring connection structure, in order to provide transfer-control signal transmission from circuit substrate circuitry to the pixel substrate in a stacked imaging device.
Ikeda and Yanagita are silent regarding
“wherein the wiring formed in the second semiconductor substrate has a prismatic shape or a cylindrical shape”.
However, Hara teaches semiconductor substrate 8, connection conductors and vias formed in a wiring structure on the semiconductor substrate. Hara teaches, in Fig. 3A and ¶ [0063], that a connection conductor is commonly connected to a plurality of vias, such as vias 20a and 20b, and also vias 20g, and 20h. Hara further teaches rectangular parallelepiped connection conductors, such as connection conductors 30a, 30b, 40a, and 40b, formed in the wiring stack on semiconductor substrate 8 and connected to the vias. A rectangular parallelepiped conductor is a prismatic conductor.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to form inside or on the circuit-substrate-side wiring structure of Yanagita’s circuit substrate 9 laminated on the second-surface side of the wiring layer, similar prismatic/ rectangular parallelepiped wiring block as taught by Hara, and to electrically connect the first wiring and second wiring to those wiring blocks, in order to adopt the simple and highly integrated wiring structure taught by Hara and to improve wiring density, and simplify electrical connection between the stacked substrates.
Ikeda and Yanagita disclose imaging device, and Hara is directed to semiconductor wiring/interconnect structures, hence analogous art. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Ikeda's imaging element to include Yanagita’s laminated wiring-layer and substrate-bonding structure, including surface-side transfer-control wiring/electrode connections and circuit-substrate-side plugs/wirings, and to further use Hara’s prismatic/rectangular-parallelepiped wiring blocks for the circuit-substrate-side wiring, in order to use a conventional stacked solid-state imaging-device architecture, increase wiring density, route control signals between stacked substrates, and improve electrical connection between the pixel substrate and the circuit substrate as taught by Yanagita in ¶ [0008].
Re: Independent Claim 9 (Currently amended), Ikeda discloses an imaging device comprising:
a first semiconductor substrate in which a plurality of pixels are arranged in a matrix of rows and columns, wherein each pixel of the plurality of pixels includes a photodiode, a first transfer transistor configured to transfer a charge generated by the photodiode to a first charge accumulation section, and a second transfer transistor configures to transfer the charge generated by the photodiode to a second charge accumulation section (Ikeda, Fig 3, ¶ [0028] - [0029], Ikeda discloses and imaging device including a first semiconductor substrate on which a pixel portion 104 is formed. The pixel portion includes pixels P (x, y) arranged in rows and columns. Each pixel P includes a photoelectric conversion unit 10 that is a photodiode, a first transfer transistor 11, a second transfer transistor 12, a first signal holding portion 14, and a second signal holding portion 15. Transfer transistor 11 transfers charge generated in the photoelectric conversion unit 10 to signal holding portion 14, and transfer transistor 12 transfers charge generated in the photoelectric conversion unit 10 to signal holding portion 15).
Regarding the limitation: “a wiring layer laminated on the first semiconductor substrate, wherein the wiring layer includes a first surface facing the first semiconductor substrate and a second surface facing opposite to the first surface”, Ikeda teaches, in Fig. 4, ¶ [0040], that the first substrate and the second substrate are connected by wiring provided as a line 130 arranged between the two substrates which connects circuitry on the first and second substrate, and in another embodiment by a line 47 passing through an interlayer insulating film 46 between the substrates.
Ikeda is silent regarding explicitly describing this inter-substrate wiring structure as " a wiring layer laminated on the first semiconductor substrate wherein the wiring layer includes a first surface facing the first semiconductor substrate and a second surface facing opposite to the first surface".
However, Yanagita teaches, in Fig 3 and ¶ [0044], a sensor substrate 3 (semiconductor substrate) on which a first wiring layer 31 is formed on the circuit-formation surface of the sensor substrate, the first wiring layer 31 having wiring and insulating layers laminated, and being positioned between the sensor substrate 3 and a circuit substrate 9 having a second wiring layer 41.
Ikeda is further silent regarding the limitation “a second semiconductor substrate laminated on the second surface of the wiring layer”.
However, Yanagita teaches a circuit substrate 9 corresponding to a second semiconductor substrate. Yanagita teaches that sensor substrate 3 and circuit substrate 9 are coupled with first wiring layer 31 and second wiring layer 41 positioned between them. Yanagita further teaches that electrodes on the surface of first wiring layer 31 are joined to electrodes on the surface of second wiring layer 41. Therefore, Yanagita teaches laminating/coupling a second semiconductor substrate on the second-surface side of the wiring layer, opposite the first semiconductor substrate.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to implement Ikeda's inter-substrate wiring (line 130/ line 47 and associated structures) as or within a wiring layer laminated on the first semiconductor substrate in the manner of Yanagita's first wiring layer 31, such that the wiring layer includes a first structure facing the first semiconductor substrate and a second surface facing opposite to the first surface, in order to use a conventional stacked image-sensor wiring architecture and to provide reliable electrical connection between the pixel substrate and the circuit substrate.
Regarding the limitation: “wherein a first wiring connected to the first transfer transistor and a second wiring connected to the second transfer transistor are provided on the side of the wiring layer”, Ikeda teaches that pixel matrix 104 includes pixel P(x,y) with first and second transfer transistors 11 and 12 driven by vertical scanning unit 103. Although Ikeda does not explicitly state which transistors in Fig. 2 are directly driven by the vertical scanning unit 103, a person of ordinary skill in the art would understand from Ikeda’s matrix pixel arrangement and vertical scanning unit 103 that transfer-control signals are supplies to the gates of transfer transistors of pixels arranged in rows/columns. Thus, Ikeda teaches or at least suggests transfer-control wiring paths for controlling first transfer transistors 11 and second transfer transistors 12 of plurality pixels.
Ikeda is silent regarding explicitly describing such first and second transfer-control wirings as being provided on the side of the wiring layer.
Yanagita teaches, in (Fig. 1 and pixel region figures), that TRG wiring 38 and other wirings such as GND wiring 55 are formed in first wiring layer 31 on sensor substrate 3, and that TRG wiring 38 crosses pixel area 12, passes over transfer gate electrode 21-24, and is connected to corresponding transfer gate electrodes. Yanagita further teaches that TRG 38 is connected through plug 34 to third electrode 39 formed on a surface of first wiring layer 31, and that third electrode 39 is connected to fourth electrode 49 formed on a surface of second wiring layer 41 of circuit substrate 9. Thus, Yanagita teaches arranging a transfer-control wiring path, including a transfer-gate wiring and a surface-side electrode/wiring portion electrically continuous with the transfer-gate wiring, on the side of the wiring layer 31 facing the circuit substrate.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to implement Ikeda's first and second transfer transistors 11 and 12 using Yanagita's surface-side transfer-control wiring/electrode connection arrangement, such that a first wiring connected to first transfer transistors 11 and a second wiring connected to second transfer transistor 12 are provided on the side of the wiring layer in order to distribute the two transfer gate control signals between stacked substrates, increase density of multilayer wiring structure.
Regarding the limitation: “a third wiring connected to the first wiring of the plurality of pixels arranged in a row direction or a column direction from among the plurality of pixels arranged in the matrix shape and a fourth wiring connected to the second transfer transistor of the plurality of pixels included on the second semiconductor substrate, Yanagita teaches, in Fig. 6C and ¶¶ [0083], [0084], that they are connected through a third electrode 39 on the surface of the first wiring 31 and a fourth electrode 49 on the surface of the second wiring 41, and that the fourth electrode 49 is connected to a circuit element on the circuit substrate 9 through plugs 42, 44 and a wiring 48. Thus, Yanagita teaches a circuit-substrate side-wiring/electrode structure on second semiconductor substrate 9 that is electrically connected to the pixel-side transfer-control wiring. Ikeda teaches or at least suggests separate first and second transfer control paths for first and second transfer transistors 11 and 12 of pixels arranged in rows/column. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide, on the surface side of Yanagita’s circuit substrate 9, a third wiring electrically connected to the first transfer-control wiring for Ikeda’s first transfer transistors 11, and a fourth wiring electrically connected to the second transfer-control wiring for Ikeda’s second transfer transistors 12, using Yanagita’s fourth electrode 49, plugs 42/44, wiring 48, and corresponding circuit-substrate-side wiring structures, in order to route separate first and second transfer-control signals between the circuit substrate and the pixel substrate in a compact stacked image sensor, while increasing layout freedom.
Ikeda and Yanagita are silent regarding “wherein each of the third wiring and the fourth wiring have a prismatic shape or a cylindrical shape”.
However, Hara teaches, in Fig. 3A and ¶ [0063], that a connection conductor is commonly connected to a plurality of vias, such as vias 20a and 20b, and also vias 20g, and 20h. Hara further teaches rectangular parallelepiped connection conductors, such as connection conductors 30a, 30b, 40a, and 40b, formed in the wiring stack on semiconductor substrate 8 and connected to the vias. A rectangular parallelepiped conductor is a prismatic conductor. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to form inside or on the circuit-substrate-side wiring structure of Yanagita’s circuit substrate 9 laminated on the second-surface side of the wiring layer, similar prismatic/ rectangular parallelepiped wiring block as taught by Hara, and to electrically connect the first wiring and second wiring to those wiring blocks, in order to adopt the simple and highly integrated wiring structure taught by Hara and to improve wiring density, and simplify electrical connection between the stacked substrates.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Ikeda's imaging device to adopt Yanagita's stacked architecture by implementing the pixel array on a semiconductor layer with a laminated wiring layer (sensor substrate 3/wiring layer 31) and by providing first and second wirings in that wiring layer and corresponding third and fourth wirings on the laminated circuit substrate 9, and further use Hara’s prismatic wiring blocks for the third and fourth circuit-substrate-side wiring, in order to realize a compact, highly integrated stacked imaging device with shortened wiring paths and increased layout freedom while ensuring reliable electrical connection between the sensor substrate and the circuit substrate, as taught by Yanagita in ¶ [0008].
Re: Claim 10 (Currently amended), Ikeda, Yanagita and Hara disclose all the limitations of claim 9 on which this claim depends.
Yanagita further discloses,
wherein the second semiconductor substrate is a substrate on which a circuit that processes signals from the plurality of pixels is formed. As explained in the rejection of claim 9, Yanagita discloses, in Figs. 3 and 6C, that the sensor substrate 3 (on which the pixels are formed) is bonded, via opposed wiring layers and connection electrodes (e.g., first wiring layers 31 on sensor substrate 3; second wiring layer 41 on the circuit substrate 9; connection electrodes 35/45, 39/49), to a circuit substrate 9, which is a semiconductor substrate. Yanagita further teaches that the circuit substrate 9 includes various circuits for driving and reading the sensor signals-such as scanning circuits and signal processing circuits- that receive and process the signals output from the pixels on sensor substrate 3 via the wiring layers and electrodes. Hence, the second semiconductor substrate/circuit substrate 9 of Yanagita is a substrate on which a circuit that processes signals from the plurality pixels is formed.
Re: Claim 2 (Previously presented), Ikeda, Yanagita and Hara disclose all the limitations of claim 1 on which this claim depends.
Hara further teaches
wherein each of the first wiring and the second wiring is a conductor formed into a rectangular parallelepiped shape (Hara, Fig 3A, ¶¶ [0063] and [0070]), Hara teaches wiring side connection conductors (connection conductors 30a and 30b) that are explicitly described as "rectangular parallelepiped conductors" used to connect between wiring layers/ lines in a semiconductor device. These are metal wiring conductors formed as rectangular parallelepiped blocks in the wiring stack.
Ikeda, Yanagita and Hara disclose semiconductor device with multilayer architecture, hence analogous art. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to implement the first wiring and the second wiring of the Ikeda in view of Yanagita imaging element as such rectangular parallelepiped conductors, in the same manner as the conductors of Hara, in order to provide a semiconductor device having a simple wiring structure (Hara, ¶ [0104]).
Re: Claim 3 (Previously presented), Ikeda, Yanagita and Hara disclose all the limitations of claim 1 on which this claim depends.
Hara further teaches
wherein each of the first wiring and the second wiring is connected to a wiring formed into a rectangular parallelepiped shape in the wiring layer via two or more vias per pixel. As explained in the rejection of claim 2, Hara discloses connection conductors 30a, 30b (and similar conductors) that are explicitly described as rectangular parallelepiped conductors formed in wiring layers, and used to connect between via conductors and main wiring lines. Hence, these connection conductors are wiring formed into rectangular parallelepiped shapes in a wiring layer. Hara further shows that each such rectangular parallelepiped connection conductor is connected by two vias (e.g., connection conductor 30a is connected to vias 20a and 20b, and connection conductor 30b is connected to vias 20g and 20h). Thus, Hara teaches a wiring formed into rectangular parallelepiped shape in the wiring layer that is connected via two or more vias to other wirings.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to implement, in Yanagita's wiring layer 31, rectangular parallelepiped wiring segments (like the connection conductors 30a, 30b of Hara) to which the first wiring and the second wiring are connected, and to connect each of the first wiring and the second wiring to those rectangular parallelepiped wiring segments by two or more vias for each pixel-associated connection region, in the same way Hara uses two vias into a single rectangular parallelepiped connection conductor, in order realize a simple wiring structure and increase the degree of integration by shortening wiring distances and reducing non-cell regions (Hara, ¶¶ [0095] and [0104]).
Re: Claim 5 (Currently amended), Ikeda, Yanagita and Hara disclose all the limitations of claim 1 on which this claim depends.
Hara further teaches wherein each of the first wiring and the second wiring is connected to two or more vias formed in a second semiconductor substrate and is connected to a wiring formed having the prismatic shape or the cylindrical via the vias (Hara teaches, in Fig. 3A, ¶ [0063], that a connection conductor is commonly connected to a plurality of vias (e.g., 20a and 20b, 20g and 20h). Hara further teaches rectangular parallelepiped connection conductors (e.g., 30a, 30b, 40a, 40b) formed in the wiring stack on semiconductor substrate 8 and connected to those plural vias. A rectangular parallelepiped conductor is a prismatic conductor).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to form, in or on the circuit-substrate-side wiring structure of Yanagita's circuit substrate 9 laminated on the second surface, similar prismatic/rectangular-parallelepiped wiring blocks as taught by Hara, and to connect each of Ikeda’s / Yanagita’s first and second transfer-control wirings to such wiring blocks through two or more vias, in order to reduce via resistance, improve connection reliability, increasing wiring density, and adopt the simple and highly integrated wiring structure taught by Hara (Hara, ¶ [0104]).
Re: Claim 7 (Currently amended), Ikeda, Yanagita and Hara disclose all the limitations of claim 1 on which this claim depends.
Yanagita further teaches
the second semiconductor substrate is a substrate on which a circuit that processes signals from the plurality of pixels is formed (Yanagita teaches, in Fig. 1 and ¶ [0038], solid-state imaging device 10 including a first semiconductor chip unit 11 having pixel area 12, and a second semiconductor chip unit 13 having control circuit 14 and logical circuit 15, where logic circuit 15 includes a signal processing circuit).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to implement the second semiconductor substrate of the Ikeda/Yanagita/Hara stacked imaging element as a circuit substrate on which signal-processing circuitry is formed, as taught by Yanagita in order to perform control and processing of signals output from the pixel array in a compact stacked image-sensor architecture.
Re: Claim 8 (Currently amended), Ikeda, Yanagita and Hara disclose all the limitations of claim 1 on which this claim depends.
Hara further teaches
wherein each of the first wiring and the second wiring is connected to two or more wirings per pixel that are formed into the prismatic shape or the cylindrical shape formed on the second semiconductor substrate (Hara teaches, in Fig. 3A, ¶ [0063], a semiconductor device having semiconductor substrate 8 with multiple wiring layers formed on it. In this structure, connection conductors 30a and 30b (and similarly 40a, 40b) are explicitly described as rectangular parallelepiped conductors formed in the wiring stack on the substrate 8 and used as thick wiring blocks that connect via conductors 20a, 20b, 20g, 20h to bit lines and word lines. These connection conductors 30a, 30b, 40a, 40b are wirings formed into rectangular parallelepiped shapes on a semiconductor substrate. A rectangular parallelepiped conductor is a prismatic conductor. These connection conductors therefore teach wirings formed into a prismatic conductor. Hara also shows that, in one local region (e.g., one memory-cell or cell-group region), there are two or more such rectangular parallelepiped wiring blocks (e.g., 30a and 30b, or 40a and 40b) associated with that region.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to implement the wiring inside Yanagita's circuit substrate 9, using the same prismatic/rectangular-block wiring scheme as Hara: namely, to provide, for each pixel-associated region under the imaging array, two or more rectangular-parallelepiped/prismatic wiring blocks (analogous to 30a and 30b) formed on the semiconductor substrate, and to connect each of the first wiring and the second wiring from the pixel-side wiring layer 31 to those multiple rectangular parallelepiped wirings in the substrate. Doing so would simply apply the known prismatic/rectangular parallelepiped wiring blocks of Hara to the substrate-side wiring of Yanagita's stacked imaging device, in order to realize a simple and highly integrated wiring structure with sufficient cross-section and flexible routing as taught by Hara (Hara, ¶ [0101]).
Re: Claim 11 (Currently amended), Ikeda, Yanagita and Hara disclose all the limitations of claim 9 on which this claim depends.
Hara further teaches wherein each of the third wiring and the fourth wiring is a conductor formed into the prismatic shape or the cylindrical shape (Hara discloses a semiconductor device in which connection conductors (e.g., conductors denoted 30a, 30b, etc., in the wiring stack over a semiconductor substrate) are explicitly described as "rectangular parallelepiped conductors" formed in the wiring layers and used as relatively thick wiring blocks that connect between via conductors and bit lines/word lines. These conductors have a substantially rectangular length-width-thickness geometry in cross-section and function as wiring in the interconnect stack. These connection conductors of Hara are conductors formed into rectangular parallelepiped shapes used as wiring lines in a semiconductor substrate-side wiring layer. A rectangular parallelepiped conductor is a prismatic conductor).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to implement the third wiring and fourth wiring on Yanagita's circuit substrate 9 (i.e., the substrate on which the circuits that process signals from the pixels are formed) as prismatic /rectangular-parallelepiped conductors in the wiring layers on that substrate, in the same manner as the prismatic /rectangular-parallelepiped connection conductors of Hara, in order to realize a simple, robust wiring structure with sufficient cross-sectional area and high integration density in the substrate-side wiring stack (Hara, ¶ [0104] and ¶ [0101]).
Re: Claim 12 (Previously presented), Ikeda, Yanagita and Hara disclose all the limitations of claim 9 on which this claim depends.
Hara further teaches wherein each of the third wiring and the fourth wiring is connected to a wiring formed into a rectangular parallelepiped shape in the wiring layer via two or more vias per pixel (Although Ikeda and Yanagita disclose wiring layers on both the sensor structure 3 (first wiring layer 31) and the circuit substrate 9 (second wiring layer 41, wiring 48), and the fact that these are connected via electrodes 35/45, 39/49 are vertical plugs 42,44, Ikeda and Yanagita are silent regarding the third/fourth wirings or intermediate wirings in layer 31 being explicitly formed into rectangular parallelepiped shapes, and the use of two or more vias per pixel to connect the third/fourth wirings to such rectangular parallelepiped wirings. Hara discloses, in Fig 3A, a semiconductor device having a semiconductor substrate with multiple wiring layers in which connection conductors 30a, 30b (and similar conductors 40a, 40b, etc.) are formed as rectangular parallelepiped conductors in the wiring stack and used to connect between via conductors (e.g., vias 20a, 20b, 20g, 20h) and main wiring lines such as bit lines/word lines. Each rectangular-parallelepiped connection conductor (e.g. 30a) is connected to an overlying wiring line by two vias (e.g. vias 20a and 20b), and similarly for other conductors (e.g., 30b via 20g, 20h). These connection conductors correspond to wiring formed into rectangular parallelepiped shapes in a wiring layer, and the multiple vias constitute two or more vias per local connection regions between the rectangular parallelepiped wiring block and another wiring line.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to implement, in Yanagita's structure, rectangular parallelepiped wiring segments in the wiring layer 31 (analogous to the connection conductors of Hara) for each pixel (or pixel-group) region and to connect Yanagita's third and fourth wirings on circuit substrate 9 to these rectangular parallelepiped wiring segments via two or more vias per pixel, in the same way that Hara connects its overlying wiring to one rectangular-parallelepiped conductor 30a/30b using two vias 20a/20b, 20g/20h. Doing so would simply apply the known multi-via rectangular block interconnect structure of Hara to the stacked imaging device of Ikeda in view of Yanagita in order to secure sufficient cross-sectional area and redundancy at each connection, reduce contact resistance, and improve reliability and integration of the vertical interconnects in the dense wiring stack, as taught by Hara in at least ¶ [0095] and ¶ [0102].
Re: Claim 14 (Currently amended), Ikeda, Yanagita and Hara disclose all the limitations of claim 9 on which this claim depends.
Hara further teaches
wherein each of the third wiring and the fourth wiring is connected to two or more vias formed in the semiconductor substrate and is connected to a wiring formed into a rectangular parallelepiped shape in the second semiconductor substrate via the vias. As described earlier, Yanagita disclose that second circuit substrate 9 includes wiring (second wiring layer 41, wiring 48) and vertical plugs (e.g., 42, 44) that connect the joined electrodes (such as fourth electrode 49) to internal circuit elements on substrate 9. Hara discloses a semiconductor device in which a semiconductor substrate 8 carries stacked wiring layers including connection conductors 30a, 30b, 40a, 40b, explicitly describes as rectangular parallelepiped conductors forming in the wiring stack. Each such rectangular-parallelepiped connection conductors (e.g., 30a, 30b) is connected to an overlying wiring line by two vias (e.g., vias 20a and 20b into 30a, vias 20g and 20h into 30b), and similarly for other conductors. Accordingly, these connection conductors are wirings formed into rectangular parallelepiped shapes in the semiconductor substrate side wiring stack, and the multiple vias are two or more vias formed in the semiconductor substrate that connect an upper wiring line to the rectangular- parallelepiped wiring block.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to implement Yanagita's third and fourth wirings on circuit substrate 9 so that each third/fourth wiring segment connects, via two or more vias, to a rectangular-parallelepiped wiring block formed in the wiring layers of the second semiconductor substrate 9, analogous to the way Hara connects its upper wiring to rectangular-parallelepiped connection conductors 30a, 30b, etc., through two vias per conductor. Doing so would simply apply the known multi-via/rectangular-block interconnect structure of Hara to the substrate-side wiring of Ikeda-Yanagita stacked imaging device in order to adopt the simple and highly integrated wiring structure taught by Hara (Hara, ¶ [0104]).
Re: Claim 16 (Previously Presented), Ikeda, Yanagita and Hara disclose all the limitations of claim 9 on which this claim depends.
Hara further teaches wherein each of the third wiring and the fourth wiring is connected to a wiring formed into a rectangular parallelepiped shape formed in the wiring layer.
As described in claim 9 above, Yanagita clearly teaches that the third and fourth wirings on circuit substrate 9 connect to wiring in the first wiring layer 31 (for example, TRG wiring 38/ GND wiring 55 or local connection segments in layer 31) through electrodes 39, 49 and wiring 48. Hara discloses a semiconductor device having a semiconductor substrate 8 with multiple wiring layers in which connection conductors 30a, 30b, 40a, 40b are explicitly described as rectangular parallelepiped conductors formed in the wiring stack and used as relatively thick wiring blocks to connect via conductors (e.g., vias 20a, 20b, 20g, 20h) to bit lines and word lines. Accordingly, these are wirings formed into rectangular parallelepiped shapes in a wiring layer that serve as connection nodes between other wires and vias.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to implement, in Yanagita's first wiring layer 31, local wiring blocks (e.g., short connection segment associated with the interface to electrodes 39) as rectangular parallelepiped conductors, analogous to the connection conductors 30a, 30b, etc. in Hara, and to have the third and fourth wirings on circuit substrate 9 connect through the joined electrodes 39/49 to these rectangular parallelepiped wiring blocks in the wiring layer 31. Doing so would simply apply the known rectangular parallelepiped wiring blocks of Hara to the wiring layer of Yanagita's stacked imaging device in order to obtain a simple, mechanically robust wiring shape with sufficient cross-section and improved integration/routing flexibility in the dense multilayer interconnect, as taught by Hara in ¶¶ [0100] - [0101].
Re: Claim 17 (Previously Presented), Ikeda, Yanagita and Hara disclose all the limitations of claim 9 on which this claim depends.
However, Hara teaches wherein each of the third wiring and the fourth wiring is connected to two or more wirings per pixel that are formed into rectangular parallelepiped shapes formed in the wiring layer. Yanagita discloses that TRG wiring 38, GND wiring 55, and related conductors in wring layer 31 connect to electrodes 39, 49 and wiring 48 on circuit substrate 9. Hara discloses that in the wiring stack over semiconductor substrate 8, a plurality of rectangular-parallelepiped connection conductors (e.g., 30a and 30b, and similarly 40a and 40b) are provided in associated with each memory cell region or local cell group, and these multiple rectangular-parallelepiped conductors are used to connect via conductors (e.g., 20a, 20b, 20g, 20h) to main bit line/word line wiring. Accordingly, this teaches that in one functional cell region, two or more rectangular parallelepiped wirings can be provided and used as connection blocks.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to implement Yanagita's wiring layer 31 so that, for each pixel (or pixel associated region) under the third and fourth wirings, two or more rectangular parallelepiped wiring blocks are formed in wiring layer 31 (analogous to 30a and 30b in Hara), and to connect each of the third wiring and the fourth wiring on circuit substrate 9 through the joined electrodes (e.g., 39/49) to these multiple rectangular parallelepiped wiring blocks per pixel in wiring layer 31. Doing so would simply apply the multi-block rectangular parallelepiped interconnect scheme of Hara to the stacked imaging device of Ikeda and Yanagita in order to improve routing flexibility and integration density and to provide sufficient conductor cross-section and redundancy at each pixel level connections, as taught by Hara in ¶ [0101].
Claims 4, 6, 13, 15 are rejected under 35 U.S.C. 103 as being unpatentable over Ikeda (US 20190006403 A1) in the view of Yanagita (US 20150179691 A1) further in view of Hara (US 20210083182 A1), and further in view of Kim (US 20040016964 A1).
Re: Claim 4 (Previously presented), Ikeda, Yanagita and Hara disclose all the limitations of claim 1 on which this claim depends.
Ikeda, Yanagita and Hara are silent regarding:
wherein each of the first wiring and the second wiring is connected to a wiring formed into a rectangular parallelepiped shape in the wiring layer via a trench formed into a rectangular parallelepiped shape.
However, Kim teaches wherein each of the first wiring and the second wiring is connected to a wiring formed into a rectangular parallelepiped shape in the wiring layer via a trench formed into a rectangular parallelepiped shape. (Kim, Fig. 9, ¶ [0061] - [0062]) Kim discloses a semiconductor device in which a contact opening 77 is formed as a vacancy having a rectangular parallelepiped shape, and then a contact plug 80 of conductive material is then formed to fill this rectangular parallelepiped opening and connect to the active area 10a. The opening 77 corresponds to a trench formed into a rectangular parallelepiped shape, and filled conductive plug 80 corresponds to a wiring formed into a rectangular parallelepiped shape in the wiring layer that is used to connect underlying regions to other wiring.
Ikeda, Yanagita and Kim disclose semiconductor device with multilayer architecture, hence analogous art. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to implement, in Yanagita's wiring layer 31, forming rectangular parallelepiped trenches (modeled on contact opening 77) and to form rectangular parallelepiped conductive wiring blocks (modeled on contact plug 80) in those trenches, and to connect each of the first wiring and the second wiring to such rectangular parallelepiped wiring blocks via the rectangular parallelepiped trenches- i.e., to use the trench-and-plug structure of Kim as the connection structure between the first/second wirings and other wirings in the wiring layer in order to minimize rounding of the opening edges, maintain the designed opening width, and thereby allow stable plug formation and higher integration (Kim, ¶ [0056]).
Re: Claim 6 (Currently amended), Ikeda, Yanagita and Hara disclose all the limitations of claim 1 on which this claim depends.
Ikeda, Yanagita and Hara are silent regarding:
wherein each of the first wiring and the second wiring is connected to a trench formed into the prismatic shape or the cylindrical shape in the second semiconductor substrate connected to a wiring via the trench.
However, Kim teaches wherein each of the first wiring and the second wiring is connected to a trench formed into a rectangular parallelepiped shape formed in a semiconductor substrate laminated on the second surface and is connected to a wiring formed into a rectangular parallelepiped shape in the semiconductor substrate via the trench. Kim, in Fig. 9 and ¶ [0061] - [0062], teaches that contact opening 77 is a vacancy having a rectangular parallelepiped shape, and a contact plug 80 of conductive material is formed to fill those rectangular parallelepipeds opening and connect the active region 10a to overlying wiring. A rectangular parallelepiped conductor is a prismatic conductor. Kim’s rectangular parallelepiped contact opening 77 teaches the claimed trench having a prismatic shape, and Kim’s conductive contact plug 80 formed in the contact opening 77 teaches a conductive connection/wiring block through which the claimed first and second wirings may be connected to the wiring in the second semiconductor substrate.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to implement the circuit-substrate-side connections of the Ikeda/Yanagita/Hara stacked imaging element using Kim’s rectangular parallelepiped contact opening 77 and conductive plug 80, such that each of the first wiring and second wiring is connected to a prismatic trench in the second semiconductor substrate and connected to the wiring via the trench, in order to maintain a well-defined contact opening, improving plug filling, and allow stable, dense interconnect formation as taught by Kim in ¶ [0003].
Re: Claim 13 (Previously presented), Ikeda, Yanagita and Hara disclose all the limitations of claim 9 on which this claim depends.
Ikeda, Yanagita and Hara are silent regarding:
wherein each of the third wiring and the fourth wiring is connected to a wiring formed into a rectangular parallelepiped shape in the wiring layer via a trench formed into a rectangular parallelepiped shape.
However, Kim teaches wherein each of the third wiring and the fourth wiring is connected to a wiring formed into a rectangular parallelepiped shape in the wiring layer via a trench formed into a rectangular parallelepiped shape. As explained in claim 9 above, Yanagita discloses that the pixel-side wirings (e.g., TRG wiring 38 and GND wiring 55) are formed in the first wiring layer 31, and that these are connected to wiring in the second wiring layer 41 on circuit substrate 9 by opposed electrodes 39/49 and plugs/wiring in the circuit substrate. Kim teaches, in Fig. 9 and ¶ [0061] - [0062], a semiconductor device in which: (i) on a semiconductor substrate 10, an insulating film pattern is formed and a trench 15 is defined and filled with a gap-fill insulating pattern 35; (ii) a contact opening 77 is then formed in that insulating region, and Kim explains that this contact opening 77 is a vacancy having a rectangular parallelepiped shape; (iii) a conductor contact plug 80 is formed to fill the rectangular parallelepiped opening 77 and connect an underlying active region 10a to upper wiring. Accordingly, the rectangular parallelepiped contact opening 77 in the insulating region corresponds to a trench formed into a rectangular parallelepiped shape, and the filled conductive plug 80 corresponds to a wiring block formed into a rectangular parallelepiped shape that is used as part of the wiring in the interconnect stack. Kim therefore teaches forming a rectangular parallelepiped trench and filling it with a rectangular parallelepiped conductor to connect lower and upper wiring.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to implement, at the interface between Yanagita's third/fourth wirings on circuit substrate 9 and the pixel side wiring layer 31, a connection structure in which the third and fourth wirings connect via rectangular parallelepiped trenches (Kim's type of opening 77) to rectangular parallelepiped wiring blocks formed in the wiring layer 31 (analogous to Kim's plug 80), in order to obtain well-defined rectangular openings, stable filling of the conductive plugs, low contact resistance, and high integration of vertical interconnects as taught by Kim in ¶ [0056].
Re: Claim 15 (Currently amended), Ikeda, Yanagita and Hara disclose all the limitations of claim 9 on which this claim depends.
Ikeda, Yanagita and Hara are silent regarding:
wherein each of the third wiring and the fourth wiring is connected to a trench formed into a rectangular parallelepiped shape formed in the second semiconductor substrate and is connected to a wiring formed into a rectangular parallelepiped shape in the second semiconductor substrate via the trench.
However, Kim teaches wherein each of the third wiring and the fourth wiring is connected to a trench formed into a rectangular parallelepiped shape formed in the second semiconductor substrate and is connected to a wiring formed into a rectangular parallelepiped shape in the second semiconductor substrate via the trench. Kim discloses a semiconductor device in which an insulating region over a semiconductor substrate 10 includes a trench/contact opening 77 that is expressly described as having a rectangular parallelepiped shape, and this opening is filled with a conductive contact plug 80 that connects an underlying active region 10a to overlying wiring. Accordingly, Kim's opening 77 corresponds to a trench formed into a rectangular parallelepiped shape in a semiconductor substrate-side structure, and the filled plug 80 corresponds to a wiring formed into a rectangular parallelepiped shape in that substrate.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to implement the connection from Yanagita's third wiring and fourth wiring on second semiconductor substrate/circuit substrate 9 down to deeper wiring in the second semiconductor substrate 9 by using rectangular parallelepiped trenches (similar to opening 77) and filling them with rectangular parallelepiped conductive plugs (similar to plug 80) that serve as wiring blocks in the substrate, so that each third/fourth wiring is connected to a trench formed into a rectangular parallelepiped shape and, via that trench, to a rectangular parallelepiped wiring in the substrate in order to obtain a well-defined rectangular opening, improving plug filling, and allow stable, dense interconnect formation as taught by Kim in ¶ [0003].
Claims 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Ikeda (US 20190006403 A1) in the view of Yanagita (US 20150179691 A1) further in view of Hara (US 20210083182 A1), and further in view of Hideaki (JP 2013096941 A).
Re: Independent Claim 18 (Currently amended), Ikeda discloses an imaging element comprising:
a first semiconductor substrate in which a plurality of pixels are arranged in a matrix of rows and columns, wherein each pixel of the plurality of pixels includes a photodiode, a first transfer transistor configured to transfer a charge generated by the photodiode to a first charge accumulation section, and a second transfer transistor configured to transfer the charge generated by the photodiode to a second charge accumulation section (Ikeda, Fig 3, ¶ [0028] - [0029], Ikeda discloses and imaging device including a first semiconductor substrate on which a pixel portion 104 is formed. The pixel portion includes pixel P (x, y) arranged in rows and columns (a matrix). Each pixel P includes a photoelectric conversion unit 10 that is a photodiode, a first transfer transistor 11, a second transfer transistor 12, a first signal holding portion 14, and a second signal holding portion 15. Transfer transistor 11 transfers charge generated in the photoelectric conversion unit 10 to signal holding portion 14, and transfer transistor 12 transfers charge generated in the photoelectric conversion unit 10 to signal holding portion 15).
Regarding the limitation: “a wiring layer laminated on the first semiconductor substrate, wherein the wiring layer includes a first surface facing the first semiconductor substrate and a second surface facing opposite to the first surface; and a second semiconductor substrate laminated on the second surface of the wiring layer”, (Ikeda Fig. 4, ¶ [0040]) Ikeda discloses that the first substrate and the second substrate are connected by wiring provided as a line 130 arranged between the two substrates which connects circuitry on the first and second substrate, and in another embodiment by a line 47 passing through an interlayer insulating film 46 between the substrates.
Ikeda is silent regarding explicitly describing this inter-substrate wiring structure as "a wiring layer laminated on the first semiconductor substrate, wherein the wiring layer includes a first surface facing the first semiconductor substrate and a second surface facing opposite to the first surface; and a second semiconductor substrate laminated on the second surface of the wiring layer".
However, Yanagita teaches, in Fig 3 and ¶ [0044], a sensor substrate 3 (semiconductor substrate), on which a first wiring layer 31 formed. Yanagita further teaches circuit substrate 9 corresponding to a second semiconductor substrate, and second wiring layer 41 formed on circuit substrate 9, and that the first wiring layer 31 and second wiring layer 41 are positioned between sensor substrate 3 and a circuit substrate 9. Yanagita further teaches surface electrodes on the wiring layers that electrically connect the sensor substrate side to the circuit substrate side. Thus, Yanagita teaches a laminating wiring-layer having a first surface facing the sensor substrate and an opposite surface facing the circuit substrate 9; and teaches laminating/coupling a second substrate on the second-surface side of the wiring layer. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to implement Ikeda's second substrate as a circuit substrate laminated on the second surface side of the wiring layer, as taught by Yanagita, in order to provide a conventional stacked image-sensor wiring architecture in which a pixel substrate and a circuit substrate are electrically connected through wiring layers positioned between the substrates.
Regarding the limitation: “wherein a first wiring connected to the first transfer transistor of the plurality of pixels arranged in a row direction or a column direction and a second wiring connected to the second transfer transistor of the plurality of pixels provided on the second surface of the wiring layer”, Ikeda also discloses that the pixel matrix 104 includes pixels P(x,y) with first and second transfer transistors 11 and 12 is driven by a vertical scanning unit 103. A person of ordinary skill would understand that this vertical scanning unit 103 that transfer-control signals are supplied to the gates of transfer transistors of pixel arranged in rows and/or columns. Thus, Ikeda teaches or at least suggest separate transfer-control wiring paths for controlling first transfer transistors 11 and second transfer transistors 12 of plural pixels arranged in rows or columns.
Ikeda is silent regarding explicitly describing these transfer-control wiring paths as a first wiring connected to the first transfer transistors of pixels in a row or a column direction and a second wiring connected to the second transfer transistor of pixels, and is further silent regarding such first and second wirings being provided on the second surfaces of a wiring layer.
However, Yanagita teaches a transfer-gate wiring connection architecture in a stacked imaging device. In particular, Yanagita teaches, in Fig 5 and ¶¶ [0078] - [0080] that TRG wiring 38 crosses pixel area 12, passes over transfer gate electrodes 21-24, and is connected to corresponding transfer gate electrodes. Yanagita further teaches that the TRG wiring 38 is connected through plug 34 to a third electrode 39 formed on a surface of first wiring layer 31 of sensor substrate 3, and that third electrode 39 is connected to fourth electrode 49 formed on a surface of second wiring layer 41 of circuit substrate 9. The fourth electrode 49 is further connected to circuitry on the circuit substrate side through plugs 42, 44, and wiring 48. Thus, Yanagita teaches arranging a transfer-control wiring path, including a transfer-gate wiring and a surface -side electrode/wiring portion electrically continuous with the transfer-gate wiring, at the surface side of the wiring layer facing the circuit substrate. Accordingly, the conductive wiring/electrode portions that are part of, and electrically continuous with, transfer-control wiring paths connected to the respective transfer transistors correspond to the claimed first wiring and second wiring. Hence, Yanagita teaches providing a transfer-control wiring/electrode portion on the second surface side of the first wiring layer 31. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to implement Ikeda’s first and second-transfer-control wiring paths for first and second transfer transistors 11 and 12 using Yanagita’s surface-side transfer-control wiring/electrodes connection arrangement, such that a first wiring connected to the first transfer transistors 11 and a second wiring connected to second transfer transistor 12 are provided on the second-surface side of the wiring layer, in order to route transfer-control signals between stacked substrates, increase wiring density, and secure reliable electrical connection between the pixel substrate and the circuit substrate.
Regarding the limitation “wherein each of the first wiring and the second wiring is electrically connected to a wiring formed in the second semiconductor substrate”, Ikeda discloses that the first and second transfer transistors 11 and 12 are driven by vertical scanning unit 103. Ikeda is silent regarding explicitly describing each of the first wiring and second wiring as being electrically connected to a wiring formed in the second semiconductor substrate.
However, Yanagita teaches that transfer-control wiring on the sensor-substrate side is electrically connected to circuitry on the circuit-substrate side. Specifically, Yanagita teaches, in Fig, 6C and ¶ [0083], that TRG wiring 38 is connected to third electrode 39 through plug 34, third electrode 39 is connected to fourth electrode 49 on the circuit-substrate-side wiring layer, and the fourth electrode 49 is connected to a circuit element formed on substrate 9 through plugs 42, 44 and wiring 48. Therefore, Yanagita teaches electrically connecting a transfer-control wiring/electrode structure on the sensor-substrate side to wiring/circuitry formed on the second semiconductor substrate side.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to electrically connect Ikeda’s first and second transfer-control wirings to corresponding wirings formed in or associated with the second semiconductor substrate using Yanagita’s surface electrode, plug, and wiring connection structure, in order to provide transfer-control signal transmission from circuit substrate circuitry to the pixel substrate in a stacked imaging device.
Ikeda and Yanagita are silent regarding
wherein the wiring formed in the second semiconductor substrate has a prismatic shape or a cylindrical shape.
However, Hara teaches semiconductor substrate 8, connection conductors and vias formed in a wiring structure on the semiconductor substrate. Hara teaches, in Fig. 3A and ¶ [0063], that a connection conductor is commonly connected to a plurality of vias, such as vias 20a and 20b, and also vias 20g, and 20h. Hara further teaches rectangular parallelepiped connection conductors, such as connection conductors 30a, 30b, 40a, and 40b, formed in the wiring stack on semiconductor substrate 8 and connected to the vias. A rectangular parallelepiped conductor is a prismatic conductor.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to form inside or on the circuit-substrate-side wiring structure of Yanagita’s circuit substrate 9 laminated on the second-surface side of the wiring layer, similar prismatic/ rectangular parallelepiped wiring block as taught by Hara, and to electrically connect the first wiring and second wiring to those wiring blocks, in order to adopt the simple and highly integrated wiring structure taught by Hara and to improve wiring density, and simplify electrical connection between the stacked substrates.
Ikeda and Yanagita disclose imaging device, and Hara is directed to semiconductor wiring/interconnect structures, hence analogous art. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Ikeda's imaging element to include Yanagita’s laminated wiring-layer and substrate-bonding structure, including surface-side transfer-control wiring/electrode connections and circuit-substrate-side plugs/wirings, and to further use Hara’s prismatic/rectangular-parallelepiped wiring blocks for the circuit-substrate-side wiring, in order to use a conventional stacked solid-state imaging-device architecture, increase wiring density, route control signals between stacked substrates, and improve electrical connection between the pixel substrate and the circuit substrate as taught by Yanagita in ¶ [0008].
Ikeda, Yanagita and Hara are silent regarding electronics equipment comprising a distance measurement module, a light source that emits irradiation light with a periodically varying brightness, and a light emission control section that controls an irradiation timing of the irradiation light.
However, Hideaki teaches (Hideaki, Configuration Example of Imaging Device 1 paragraph) distance measuring module (imaging device 1) that includes an imaging element (distance imaging sensor 25), a light source that emits irradiation light with a periodically varying brightness (LED 21a performs pulsed light emission, i.e., periodically varying brightness), and a light emission control section that controls an irradiation timing of the irradiation light (timing control unit 23).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to use imaging element obtained from the combination of Ikeda and Yanagita as imaging element in the distance-measurement module of Hideaki, and to provide together with that imaging element, the light source and light emission control section taught by Hideaki in order to realize electronic equipment capable of distance measurement using a solid-state imaging element with improved pixel and wiring structure, while employing the conventional modulated-illuminated and timing control scheme taught by Hideaki (¶ Configuration Example of Imaging Device 1 paragraph).
Re: Independent Claim 19 (Currently amended), Ikeda discloses an imaging element comprising:
a first semiconductor substrate in which a plurality of pixels are arranged in a matrix of rows and columns, wherein each pixel of the plurality of pixels includes a photodiode, a first transfer transistor configured to transfer a charge generated by the photodiode to a first charge accumulation section, and a second transfer transistor configured to transfer the charge generated by the photodiode to a second charge accumulation section (Ikeda, Fig 3, ¶ [0028] - [0029], Ikeda discloses and imaging device including a first semiconductor substrate on which a pixel portion 104 is formed. The pixel portion includes pixel P (x, y) arranged in rows and columns (a matrix). Each pixel P includes a photoelectric conversion unit 10 that is a photodiode, a first transfer transistor 11, a second transfer transistor 12, a first signal holding portion 14, and a second signal holding portion 15. Transfer transistor 11 transfers charge generated in the photoelectric conversion unit 10 to signal holding portion 14, and transfer transistor 12 transfers charge generated in the photoelectric conversion unit 10 to signal holding portion 15).
Regarding the limitation: “a wiring layer laminated on the first semiconductor substrate, wherein the wiring layer includes a first surface facing the first semiconductor substrate and a second surface facing opposite to the first surface: and a second semiconductor substrate laminated on the second surface of the wiring layer”, (Ikeda Fig. 4, ¶ [0040]) Ikeda discloses that the first substrate and the second substrate are connected by wiring provided as a line 130 arranged between the two substrates which connects circuitry on the first and second substrate, and in another embodiment by a line 47 passing through an interlayer insulating film 46 between the substrates.
Ikeda is silent regarding explicitly describing this inter-substrate wiring structure as " a wiring layer laminated on the first semiconductor substrate wherein the wiring layer includes a first surface facing the first semiconductor substrate and a second surface facing opposite to the first surface".
However, Yanagita teaches, in Fig 3 and ¶ [0044], a sensor substrate 3 (semiconductor substrate) on which a first wiring layer 31 is formed on the circuit-formation surface of the sensor substrate, the first wiring layer 31 having wiring and insulating layers laminated, and being positioned between the sensor substrate 3 and a circuit substrate 9 having a second wiring layer 41.
Ikeda is further silent regarding the limitation “a second semiconductor substrate laminated on the second surface of the wiring layer”.
However, Yanagita teaches a circuit substrate 9 corresponding to a second semiconductor substrate. Yanagita teaches that sensor substrate 3 and circuit substrate 9 are coupled with first wiring layer 31 and second wiring layer 41 positioned between them. Yanagita further teaches that electrodes on the surface of first wiring layer 31 are joined to electrodes on the surface of second wiring layer 41. Therefore, Yanagita teaches laminating/coupling a second semiconductor substrate on the second-surface side of the wiring layer, opposite the first semiconductor substrate.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to implement Ikeda's inter-substrate wiring (line 130/ line 47 and associated structures) as or within a wiring layer laminated on the first semiconductor substrate in the manner of Yanagita's first wiring layer 31, such that the wiring layer includes a first structure facing the first semiconductor substrate and a second surface facing opposite to the first surface, in order to use a conventional stacked image-sensor wiring architecture and to provide reliable electrical connection between the pixel substrate and the circuit substrate.
Regarding the limitation: “wherein a first wiring connected to the first transfer transistor and a second wiring connected to the second transfer transistor are provided on the side of the wiring layer “, Ikeda teaches that pixel matrix 104 includes pixel P(x,y) with first and second transfer transistors 11 and 12 driven by vertical scanning unit 103. Although Ikeda does not explicitly state which transistors in Fig. 2 are directly driven by the vertical scanning unit 103, a person of ordinary skill in the art would understand from Ikeda’s matrix pixel arrangement and vertical scanning unit 103 that transfer-control signals are supplies to the gates of transfer transistors of pixels arranged in rows/columns. Thus, Ikeda teaches or at least suggests transfer-control wiring paths for controlling first transfer transistors 11 and second transfer transistors 12 of plurality pixels.
Ikeda is silent regarding explicitly describing such first and second transfer-control wirings as being provided on the side of the wiring layer.
Yanagita teaches, in (Fig. 1 and pixel region figures), that TRG wiring 38 and other wirings such as GND wiring 55 are formed in first wiring layer 31 on sensor substrate 3, and that TRG wiring 38 crosses pixel area 12, passes over transfer gate electrode 21-24, and is connected to corresponding transfer gate electrodes. Yanagita further teaches that TRG 38 is connected through plug 34 to third electrode 39 formed on a surface of first wiring layer 31, and that third electrode 39 is connected to fourth electrode 49 formed on a surface of second wiring layer 41 of circuit substrate 9. Thus, Yanagita teaches arranging a transfer-control wiring path, including a transfer-gate wiring and a surface-side electrode/wiring portion electrically continuous with the transfer-gate wiring, on the side of the wiring layer 31 facing the circuit substrate.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to implement Ikeda's first and second transfer transistors 11 and 12 using Yanagita's surface-side transfer-control wiring/electrode connection arrangement, such that a first wiring connected to first transfer transistors 11 and a second wiring connected to second transfer transistor 12 are provided on the side of the wiring layer in order to distribute the two transfer gate control signals between stacked substrates, increase density of multilayer wiring structure.
Regarding the limitation: “a third wiring connected to the first wiring of the plurality of pixels arranged in a row direction or a column direction from among the plurality of pixels arranged in the matrix shape and a fourth wiring connected to the second transfer transistor of the plurality of pixels included on the second semiconductor substrate”, Yanagita teaches, in Fig. 6C and ¶¶ [0083], [0084], that they are connected through a third electrode 39 on the surface of the first wiring 31 and a fourth electrode 49 on the surface of the second wiring 41, and that the fourth electrode 49 is connected to a circuit element on the circuit substrate 9 through plugs 42, 44 and a wiring 48. Thus, Yanagita teaches a circuit-substrate side-wiring/electrode structure on second semiconductor substrate 9 that is electrically connected to the pixel-side transfer-control wiring. Ikeda teaches or at least suggests separate first and second transfer control paths for first and second transfer transistors 11 and 12 of pixels arranged in rows/column. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide, on the surface side of Yanagita’s circuit substrate 9, a third wiring electrically connected to the first transfer-control wiring for Ikeda’s first transfer transistors 11, and a fourth wiring electrically connected to the second transfer-control wiring for Ikeda’s second transfer transistors 12, using Yanagita’s fourth electrode 49, plugs 42/44, wiring 48, and corresponding circuit-substrate-side wiring structures, in order to route separate first and second transfer-control signals between the circuit substrate and the pixel substrate in a compact stacked image sensor, while increasing layout freedom.
Ikeda and Yanagita are silent regarding “wherein each of the third wiring and the fourth wiring have a prismatic shape or a cylindrical shape”.
However, Hara teaches, in Fig. 3A and ¶ [0063], that a connection conductor is commonly connected to a plurality of vias, such as vias 20a and 20b, and also vias 20g, and 20h. Hara further teaches rectangular parallelepiped connection conductors, such as connection conductors 30a, 30b, 40a, and 40b, formed in the wiring stack on semiconductor substrate 8 and connected to the vias. A rectangular parallelepiped conductor is a prismatic conductor. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to form inside or on the circuit-substrate-side wiring structure of Yanagita’s circuit substrate 9 laminated on the second-surface side of the wiring layer, similar prismatic/ rectangular parallelepiped wiring block as taught by Hara, and to electrically connect the first wiring and second wiring to those wiring blocks, in order to adopt the simple and highly integrated wiring structure taught by Hara and to improve wiring density, and simplify electrical connection between the stacked substrates.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Ikeda's imaging device to adopt Yanagita's stacked architecture by implementing the pixel array on a semiconductor layer with a laminated wiring layer (sensor substrate 3/wiring layer 31) and by providing first and second wirings in that wiring layer and corresponding third and fourth wirings on the laminated circuit substrate 9, and further use Hara’s prismatic wiring blocks for the third and fourth circuit-substrate-side wiring, in order to realize a compact, highly integrated stacked imaging device with shortened wiring paths and increased layout freedom while ensuring reliable electrical connection between the sensor substrate and the circuit substrate, as taught by Yanagita in ¶ [0008].
Ikeda, Yanagita and Hara are silent regarding electronics equipment comprising a distance measurement module, a light source that emits irradiation light with a periodically varying brightness, and a light emission control section that controls an irradiation timing of the irradiation light.
However, Hideaki teaches (Hideaki, Configuration Example of Imaging Device 1 paragraph) distance measuring module (imaging device 1) that includes an imaging element (distance imaging sensor 25), a light source that emits irradiation light with a periodically varying brightness (LED 21a performs pulsed light emission, i.e., periodically varying brightness), and a light emission control section that controls an irradiation timing of the irradiation light (timing control unit 23).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to use imaging element obtained from the combination of Ikeda and Yanagita as imaging element in the distance-measurement module of Hideaki, and to provide together with that imaging element, the light source and light emission control section taught by Hideaki in order to realize electronic equipment capable of distance measurement using a solid-state imaging element with improved pixel and wiring structure, while employing the conventional modulated-illuminated and timing control scheme taught by Hideaki (¶ Configuration Example of Imaging Device 1 paragraph).
Re: Claim 20 (New), Ikeda, Yanagita, Hara and Hideaki disclose all the limitations of claim 18 on which this claim depends.
Hara further teaches
wherein each of the first wiring and the second wiring is a conductor formed into a rectangular parallelepiped shape (Hara, Fig 3A, ¶¶ [0063] and [0070]), Hara teaches wiring side connection conductors (connection conductors 30a and 30b) that are explicitly described as "rectangular parallelepiped conductors" used to connect between wiring layers/ lines in a semiconductor device. These are metal wiring conductors formed as rectangular parallelepiped blocks in the wiring stack.
Ikeda, Yanagita, Hideaki and Hara disclose semiconductor device with multilayer architecture, hence analogous art. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to implement the first wiring and the second wiring of the Ikeda in view of Yanagita and Hideaki imaging element as such rectangular parallelepiped conductors, in the same manner as the conductors of Hara, in order to provide a semiconductor device having a simple wiring structure (Hara, ¶ [0104]).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/BIPANA ADHIKARI DAWADI/Examiner, Art Unit 2898
/JESSICA S MANNO/SPE, Art Unit 2898
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