DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment to the claims filed on 01/05/2026 does not comply with the requirements of 37 CFR 1.121(c) because some of the claims do have a proper identifier. Amendments to the claims filed on or after July 30, 2003 must comply with 37 CFR 1.121(c) which states:
In the claim listing, the status of every claim must be indicated after its claim number by using one of the following identifiers in a parenthetical expression: (Original), (Currently amended), (Canceled), (Withdrawn), (Previously presented), (New), and (Not entered). In this case, claims 13, 16, 19 and 21 should have a status of (Withdrawn).
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 10 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Liu et al. (US 20100163090 A1).
In regard to claim 10, Liu teaches a semiconductor refrigeration chip, comprising a semiconductor refrigeration assembly (100), wherein the semiconductor refrigeration assembly comprises a first insulating and heat-conducting layer (110) and a second insulating and heat-conducting layer (130) provided opposite to each other and a semiconductor layer (142) arranged between the first insulating and heat-conducting layer (110) and the second insulating and heat-conducting layer (130) (see fig. 2 and the annotated figure 5 below), a side of the semiconductor refrigeration assembly provided with the first insulating and heat-conducting layer (110) is a cold end (see ¶ 0039), and a side of the semiconductor refrigeration assembly provided with the second insulating and heat-conducting layer (110) is a hot end (¶ 0039); and
a packaging structure (530) wherein the packaging structure (530) covers side walls of the first insulating and heat-conducting layer (110), the second insulating and heat-conducting layer (130), and the semiconductor layer (142) and defines a first groove (see the annotated figure below wherein the groove is formed wherein the chip 410 is positioned) with the first insulating and heat-conducting layer (110) (see fig. 2 and the annotated fig. 5 below).
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Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 10-12, 14, 15, 17, 18 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Jun-ling Gao et al. (CN 103697618 B; Text references to Gao are made with respect to an English translation made of record in this office action) in view of Liu et al. (US 2010/0163090 A1).
In regard to claim 10, Gao teaches a semiconductor refrigeration chip, comprising:
a semiconductor refrigeration assembly, wherein the semiconductor refrigeration assembly comprises a first insulating and heat-conducting layer (11) and a second insulating and heat- conducting layer (12) provided opposite to each other and a semiconductor layer (13) arranged between the first insulating and heat-conducting layer (11) and the second insulating and heat-conducting layer (12) (see fig. 2, 3, 5 and 6; see page 2 of the translation of Gao),
a side of the semiconductor refrigeration assembly (bottom side) provided with the first insulating and heat-conducting layer (12) is a cold end, and a side of the semiconductor refrigeration assembly (top side) provided with the second insulating and heat-conducting layer (11) is a hot end (see page 2 and 3 of the English translation); and
a packaging structure (side wall 2 comprising adhesive layer 21 and reinforcing layer 22), wherein the packaging structure (2) covers a side wall of the semiconductor refrigeration assembly (see fig. 3-6), but does not teach the packaging structure defines a first groove with the first insulating and heat-conducting layer.
However, Liu teaches a semiconductor refrigeration assembly (100) comprises a first insulating and heat-conducting layer (110) and a second insulating and heat-conducting layer (130) provided opposite to each other and a semiconductor layer (142) arranged between the first insulating and heat-conducting layer (110) and the second insulating and heat-conducting layer (130) (see fig. 1 and the annotated figure 5 above), a side of the semiconductor refrigeration assembly provided with the first insulating and heat-conducting layer (110) is a cold end (see ¶ 0039), and a side of the semiconductor refrigeration assembly provided with the second insulating and heat-conducting layer (130) is a hot end (¶ 0039); and a packaging structure (530) wherein the packaging structure (530) covers side walls of the first insulating and heat-conducting layer (110), the second insulating and heat-conducting layer (130), and the semiconductor layer (142) and defines a first groove (see the annotated figure below wherein the groove is formed wherein the chip 410 is positioned) with the first insulating and heat-conducting layer (110) (see fig. 1 and the annotated fig. 5 above).
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to modify the packaging structure of Gao to define a first groove with the first insulating and heat-conducting layer by extending the walls of the packaging structure above the first insulating and heat-conducting layer, in view of the teachings of Liu, for the purpose of providing a protected cover for positioning a semiconductor chip/or other structure that can be cooled by the semiconductor refrigeration.
In regard to claim 11, the modified Gao teaches the semiconductor refrigeration chip according to claim 10, wherein the semiconductor layer comprises a plurality of thermocouples (13), the plurality of thermocouples are connected in series (see fig. 3), and the plurality of thermocouples (13) are electrically connected to a wire (electrode lead wire 17) (see Gao fig. 3, 4; see also page 3, ¶ 3 and page 7, ¶ 5 of the English translation of Gao).
In regard to claim 12, the modified Gao teaches the semiconductor refrigeration chip according to claim 10, wherein the wire (17) penetrates through the packaging structure (2) and extends to outside of the packaging structure (see Gao fig. 4; page 7, ¶ 5 of the English translation of Gao).
In regard to claims 14 and 15, the modified Gao teaches the semiconductor refrigeration chip according to claim 10, wherein a wall of the packaging structure (2) has a thickness (W1) and depth (H) (see fig. 6 of Gao), but does not explicitly teach a wall thickness of the packaging structure is 0.2-1 mm and a depth of the first groove is 0.2-1 mm. However, while the reference does not explicitly disclose the specific thickness and depth of the of the wall of the packaging structure, it would have been obvious to one of ordinary skill in the art at the time of the invention to change the thickness and depth of the wall of the packaging structure, since such a modification would have involved a mere change in the size (or dimension) of a component. A change in size (dimension) is generally recognized as being within the level of ordinary skill in the art. In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955). Where the only difference between the prior art and the claims is a recitation of relative dimensions of the claimed device, and the device having the claimed dimensions would not perform differently than the prior art device, the claimed device is not patentably distinct from the prior art device, Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984). Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to modify the thickness and depth of the wall of the packaging structure of Liu into a thickness of 0.2-1 mm and a depth of 0.2-1 mm, as an engineering expedient, in order to allow heat to be conducted faster, improving the overall cooling performance of the thermoelectric module.
In regard to claim 17, the modified Gao in view of Liu teaches the semiconductor refrigeration chip according to claim 10, wherein Liu teaches a shape of an opening of the groove (the groove occupied by Chip 410) comprises at least one of a quadrangle (see fig. 1 of Liu chip 410 shaped quadrangle), a circle, or an ellipse.
In regard to claim 18, the modified Gao in view of Liu teaches the semiconductor refrigeration chip according to claim 10, wherein an area of an opening of the first groove is consistent with an area of the first insulating and heat-conducting layer (see the rejection of claim 10). In this case, by modifying Gao’s, as modified, teaches the packaging structure to extend above the first insulating and heat-conducting layer (11) to create the groove, the groove will be formed consistent within an area of the first insulating and heat-conducting layer (11) and the packaging structure (see the annotated figure of Liu).
In regard to claim 20, the modified Gao teaches the semiconductor refrigeration chip according to claim 10, wherein a material for forming the packaging structure comprises at least one of a polyamide hot melt adhesive, a polyolefin hot melt adhesive, or a reactive polyurethane hot melt adhesive (see page 4, ¶ 4 of the English translation of Gao).
Response to Arguments
Applicant’s arguments with respect to the amended claims have been considered but are moot in view of the new ground(s) of rejection (in view of Liu et al. (US 20100163090 A1).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WEBESHET MENGESHA whose telephone number is (571)270-1793. The examiner can normally be reached Mon-Thurs 7-4, alternate Fridays, EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Frantz Jules can be reached at 571-272-6681. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/W.M/Examiner, Art Unit 3763
/FRANTZ F JULES/Supervisory Patent Examiner, Art Unit 3763