DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 10 is rejected under 35 U.S.C. 102(a)(1)as being anticipated by Liu et al. (US 2010/0163090 A1).
In regard to claim 10, Liu teaches a semiconductor refrigeration chip, comprising:
a semiconductor refrigeration assembly (thermoelectric device 100), wherein the semiconductor refrigeration assembly comprises a first insulating and heat-conducting layer (composite of substrate 130 + insulation layer 160 at the cold end- substrate 130 is metal or silicon providing heat conduction, and insulation layer 160 provides electrical insulation between the thermoelectric couple module 140 and substrate 130) and a second insulating and heat-conducting layer (composite of substrate 110 + insulation layer 150 at the hot end) provided opposite to each other, and a semiconductor layer (thermoelectric couple module 140 comprising thermoelectric couples 142 connected in series) arranged between the first insulating and heat-conducting layer (130+160) and the second insulating and heat-conducting layer (110+150) (see Liu, ¶[0027]-[0035]; Figs. 1, 5, 8A-8F),
a side of the semiconductor refrigeration assembly provided with the first insulating and heat-conducting layer (130+160) is a cold end, and a side of the semiconductor refrigeration assembly provided with the second insulating and heat-conducting layer (110+150) is a hot end. See Liu, ¶[0045] ("an end of the thermoelectric device 100 adjacent to the chip 410 is a cold end 102, and an end of the thermoelectric device 100 away from the chip 410 is a hot end 104"). The cold end 102 is the end at which substrate 130 and insulation layer 160 (the first insulating and heat-conducting layer composite) are located (see Liu, Fig. 5);
a packaging structure (molding compound 530) wherein the packaging structure (530): (i) Covers and directly contacts the side walls of the first insulating and heat-conducting layer (130+160), the second insulating and heat-conducting layer (110+150), and the semiconductor layer (module 140): Molding compound 530 is disposed between heat sink 520 and carrier substrate 210 and encapsulates thermoelectric device 100, chip 410, and conductive lines 510 (see Liu, ¶ [0048]; Fig. 5: by encapsulating the thermoelectric device 100, the molding compound 530 covers and directly contacts the lateral side walls of the first insulating and heat-conducting layer composite (130+160), the second insulating and heat-conducting layer composite (110+150), and the thermoelectric couple module 140 (semiconductor layer). Consistent with the scope of claim 10 as reflected in the claimed invention's Fig. 2, the "covers side wall" limitation is directed to the lateral side faces of the assembly layers, not the top or bottom faces, and Liu's molding compound 530 plainly covers and directly contacts those lateral side faces), and (ii) Defines a first groove with the first insulating and heat-conducting layer (130+160): In Liu's chip package structure 500 (Fig. 5), chip 410 is positioned at the cold end of the thermoelectric device 100, adjacent to the cold-end surface of substrate 130. The region in which chip 410 is seated is bounded on its sides by the walls of molding compound 530 and on its base by the cold-end outer surface of substrate 130: the outer face of the first insulating and heat-conducting layer composite (130+160). This defines a groove between the packaging structure (530) and the first insulating and heat-conducting layer (130+160). See Liu, ¶ 0044-0048; Fig. 5.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 10-12, 14, 15, 17, 18 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Jun-ling Gao et al. (CN 103697618 B; Text references to Gao are made with respect to an English translation made of record in this office action) in view of Liu et al. (US 2010/0163090 A1).
In regard to claim 10, Gao teaches a semiconductor refrigeration chip, comprising:
a semiconductor refrigeration assembly, wherein the semiconductor refrigeration assembly comprises a first insulating and heat-conducting layer (insulating and heat-conducting layer 11) and a second insulating and heat-conducting layer (insulating and heat-conducting layer 12) provided opposite to each other, and a semiconductor layer(semiconductor layer 13 comprising thermocouples) arranged between the first insulating and heat-conducting layer (11) and the second insulating and heat-conducting layer (12) (see Gao, Figs. 2, 3, 5, 6; page 2 of the English translation);
a side of the semiconductor refrigeration assembly provided with the first insulating and heat-conducting layer (11, bottom side) is a cold end, and a side of the semiconductor refrigeration assembly provided with the second insulating and heat-conducting layer (12, top side) is a hot end (see Gao, pages 2-3 of the English translation); and
a packaging structure (side wall 2 comprising adhesive layer 21 and reinforcing layer 22), wherein the packaging structure (2) covers the side walls of the semiconductor refrigeration assembly (see Gao, Figs. 3-6). The packaging structure (2), through its adhesive layer 21, directly contacts the side walls of the first insulating and heat-conducting layer (11), the second insulating and heat-conducting layer (12), and the semiconductor layer (13) (see Gao, Figs. 3-6; page 2-3 of the English translation).
however, Gao does not explicitly teach that the packaging structure covers and directly contacts lateral side walls of the first and second heat-conducting layers and defines a first groove with the first insulating and heat-conducting layer.
Liu teaches, in the context of chip package structure 500 (Fig. 5), a packaging structure (molding compound 530) that defines a first groove with the first insulating and heat-conducting layer. Specifically, under the composite interpretation, the first insulating and heat-conducting layer is the composite of substrate 130 + insulation layer 160 at the cold end of thermoelectric device 100 (see Liu, ¶[0044]-[0045]; Fig. 5). Chip 410 is positioned at the cold end adjacent to the cold-end outer surface of substrate 130. The region where chip 410 is seated is bounded on its sides by the walls of molding compound 530 and on its base by the cold-end outer surface of substrate 130 — the outer face of the first insulating and heat-conducting layer composite (130+160). This defines a groove between the packaging structure (530) and the first insulating and heat-conducting layer (130+160). See Liu, ¶[0044]-[0048]; Fig. 5. Notably, in Liu's Fig. 5 the cold-end top face of the first insulating and heat-conducting layer (outer surface of substrate 130) is not covered by the molding compound 530, it is exposed as the floor of the groove where chip 410 is seated, which is the identical geometry to Applicant's Fig. 2. Furthermore, Liu expressly teaches that its molding compound 530 encapsulates the thermoelectric device 100 (see Liu, ¶[0048]; Fig. 5), thereby covering and directly contacting the side walls of the first insulating and heat-conducting layer composite (130+160), the second insulating and heat-conducting layer composite (110+150), and the semiconductor layer (module 140). This further confirms that Liu teaches the "covers and directly contacts side walls" limitation in addition to Gao.
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the packaging structure of Gao to extend the walls of the packaging structure above the cold-end first insulating and heat-conducting layer (11), thereby defining a first groove between the packaging structure walls and the cold-end first insulating and heat-conducting layer (11), in view of the teachings of Liu. The motivation to make this modification is: (1) Liu teaches that positioning a component to be cooled at the cold end of a thermoelectric device within a defined groove-like region formed by the packaging structure walls and the cold-end layer surface protects the cooled component and ensures reliable thermal contact (see Liu, ¶ [0044]-[0048]; Fig. 5); and (2) as recognized in the art, extending the packaging walls above the cold-end insulating layer transfers assembly fixture loads from the brittle ceramic insulating layers and semiconductor dies to the packaging structure, significantly improving overload resistance and reducing breakage during assembly, which is a known problem with conventional TEC chips.
In regard to claim 11, the modified Gao teaches the semiconductor refrigeration chip according to claim 10, wherein the semiconductor layer comprises a plurality of thermocouples (13), the plurality of thermocouples are connected in series (see fig. 3), and the plurality of thermocouples (13) are electrically connected to a wire (electrode lead wire 17) (see Gao fig. 3, 4; see also page 3, ¶ 3 and page 7, ¶ 5 of the English translation of Gao).
In regard to claim 12, the modified Gao teaches the semiconductor refrigeration chip according to claim 10, wherein the wire (17) penetrates through the packaging structure (2) and extends to outside of the packaging structure (see Gao fig. 4; page 7, ¶ 5 of the English translation of Gao).
In regard to claims 14 and 15, the modified Gao teaches the semiconductor refrigeration chip according to claim 10, wherein a wall of the packaging structure (2) has a thickness (W1) and depth (H) (see fig. 6 of Gao), but does not explicitly teach a wall thickness of the packaging structure is 0.2-1 mm and a depth of the first groove is 0.2-1 mm. However, while the reference does not explicitly disclose the specific thickness and depth of the of the wall of the packaging structure, it would have been obvious to one of ordinary skill in the art at the time of the invention to change the thickness and depth of the wall of the packaging structure, since such a modification would have involved a mere change in the size (or dimension) of a component. A change in size (dimension) is generally recognized as being within the level of ordinary skill in the art. In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955). Where the only difference between the prior art and the claims is a recitation of relative dimensions of the claimed device, and the device having the claimed dimensions would not perform differently than the prior art device, the claimed device is not patentably distinct from the prior art device, Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984). Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to modify the thickness and depth of the wall of the packaging structure of Liu into a thickness of 0.2-1 mm and a depth of 0.2-1 mm, as an engineering expedient, in order to allow heat to be conducted faster, improving the overall cooling performance of the thermoelectric module. The present application itself discloses (see US 2024/0011678 A1, ¶[0043]) that wall thickness greater than 1 mm reduces refrigeration effect and thickness less than 0.2 mm is insufficient for overload resistance — establishing that this range represents an optimal engineering tradeoff that would be arrived at by routine experimentation within the level of ordinary skill.
In regard to claim 17, the modified Gao in view of Liu teaches the semiconductor refrigeration chip according to claim 10, wherein a shape of an opening of the groove comprises at least one of a quadrangle, a circle, or an ellipse. Liu teaches that chip 410, which is positioned within the groove defined by molding compound 530 and the cold-end surface of the first insulating and heat-conducting layer (130+160), is quadrilateral in cross-section (see Liu, Fig. 1, Fig. 5; chip 410 shown with rectangular/quadrilateral geometry). See Liu, claims 8 and 17; Figs. 1, 4-5. One of ordinary skill in the art would understand that the shape of the groove opening corresponds to the shape of the component to be cooled and would select a quadrangular, circular, or elliptical groove opening as appropriate for the component, as a matter of routine engineering expedient.
In regard to claim 18, the modified Gao in view of Liu teaches the semiconductor refrigeration chip according to claim 10, wherein an area of an opening of the first groove is consistent with an area of the first insulating and heat-conducting layer. In the modified Gao, when the packaging structure walls are extended above the cold-end first insulating and heat-conducting layer (11) to define the first groove, and where the packaging structure walls extend around the entire perimeter of the first insulating and heat-conducting layer (11), the area of the groove opening will be consistent with the area of the cold-end surface of the first insulating and heat-conducting layer (11). This is confirmed by Liu, wherein the groove defined between molding compound 530 walls and the cold-end surface of substrate 130 has an opening area consistent with the cold-end surface area of the first insulating and heat-conducting layer composite (130+160) (see Liu, ¶[0046]; Figs. 1, 5; see also US 2024/0011678 A1, Figs. 1-2, ¶[0046]).
In regard to claim 20, the modified Gao teaches the semiconductor refrigeration chip according to claim 10, wherein a material for forming the packaging structure comprises at least one of a polyamide hot melt adhesive, a polyolefin hot melt adhesive, or a reactive polyurethane hot melt adhesive. See Gao, page 4, ¶4 of the English translation (disclosing that the packaging material for side wall 2 includes polyamide hot melt adhesive, polyolefin hot melt adhesive, or reactive polyurethane hot melt adhesive).
Remarks
Claim Interpretation: Composite Layer Reading (BRI)
Under the broadest reasonable interpretation, the claimed "first insulating and heat-conducting layer" and "second insulating and heat-conducting layer" do not require a single discrete layer and do not exclude having a substrate on top of the insulating layer. The claim imposes two functional requirements: (1) the layer insulates, and (2) the layer conducts heat. These requirements are met by a composite structure comprising a substrate (providing heat conduction) and an insulation layer (providing electrical insulation).
Accordingly, the following composite element mapping to Liu et al. (US 2010/0163090 A1) is adopted:
First insulating and heat-conducting layer = substrate 130 (metal/silicon, heat-conducting) + insulation layer 160 (electrically insulating)- the cold-end composite. See Liu, ¶ 0028-0031, 0062; Figs. 1, 5, 8C-8E.
Second insulating and heat-conducting layer = substrate 110 (metal/silicon, heat-conducting) + insulation layer 150 (electrically insulating)- the hot-end composite. See Liu, ¶ 0027-0029, 0058; Figs. 1, 5, 8A-8B.
Semiconductor layer = thermoelectric couple module 140. See Liu, ¶ 0032; Fig. 1.
This correction does not constitute a new ground of rejection. The same reference (Liu), the same statutory basis (§102(a)(1) and §103), and the same claim limitation are at issue. The composite reading flows directly from the BRI of the claim language that was always present in claim 10. See MPEP § 1207.03(a); In re Kronig, 539 F.2d 1300, 1303 (CCPA 1976). The correction was necessitated by, and is a direct response to, Applicant's own arguments regarding Liu's element identifications. No new reference has been introduced. See MPEP § 1207.03(a). Same Statutory Basis. The rejection remains grounded in 35 U.S.C. § 102(a)(1) (anticipation) and 35 U.S.C. § 103 (obviousness). No new legal theory has been introduced.
Response to Arguments
Applicant's arguments filed 04/08/2024 have been fully considered but they are not persuasive.
Applicant’s argument (Remark page 6-7) that Liu's elements 110 and 130 are substrates, not insulating and heat-conducting layers, and the Office Action mapping of 110/130 to the claimed insulating layers is inconsistent with Liu's express disclosure.
In response, the prior element mapping is corrected as set forth in Section I above in view of applicant’s arguments and interpretation of the insulating and heat-conducting layers. The rejection no longer maps the substrate alone (110 or 130) to the claimed insulating and heat-conducting layers. Rather, the rejection maps the composite of substrate + insulation layer (130+160 at the cold end; 110+150 at the hot end) to the claimed layers. This composite as a whole is both heat-conducting (by virtue of the metal/silicon substrate) and electrically insulating (by virtue of the dedicated insulation layer). Applicant's argument that 110 and 130 standing alone are not insulation layers does not address the composite reading and is therefore not persuasive.
Applicant’s argument (Remark page 7) that Liu does not disclose a packaging structure that covers and directly contacts the side walls of the first insulating and heat-conducting layer, the second insulating and heat-conducting layer, and the semiconductor layer.
In response, the argument is not persuasive. Under the composite interpretation, Liu's molding compound 530 clearly and expressly teaches a packaging structure that covers and directly contacts the side walls of the first insulating and heat-conducting layer (130+160), the second insulating and heat-conducting layer (110+150), and the semiconductor layer (module 140). Liu expressly discloses that molding compound 530 is disposed between heat sink 520 and carrier substrate 210 for encapsulating the thermoelectric device 100, chip 410, and conductive lines 510. See Liu, ¶[0048]; Fig. 5. Encapsulation means the molding compound 530 surrounds and directly contacts the lateral side walls of all components of thermoelectric device 100, including the composite first insulating and heat-conducting layer (130+160), the composite second insulating and heat-conducting layer (110+150), and the thermoelectric couple module 140 (semiconductor layer). This is geometrically and physically required by encapsulation. Furthermore, as the Examiner notes, the "covers side wall" limitation in claim 10, in the context of Applicant's own Fig. 2, is directed to the lateral side walls of the assembly, not the top or bottom faces of the insulating and heat-conducting layers. Applying the same reading to Liu: the molding compound 530 covers and directly contacts the lateral side walls of the first and second insulating and heat-conducting layer composites and the semiconductor layer. Liu therefore satisfies this limitation in an identical structural manner to Applicant's own embodiment.
Applicant’s argument (Remark page 7-8) that Liu does not disclose a first groove defined with the first insulating and heat-conducting layer. Liu's sealing chamber A is a closed internal vacuum chamber. The chip 410 position does not define a groove co-defined with an insulating layer. The molding compound 530 is part of a larger chip package structure, not a packaging structure of the thermoelectric device defining a first groove.
In response, the arguments are not persuasive. The rejection does not rely on Liu's sealing chamber A as the claimed groove. The claimed first groove is identified in Liu's Fig. 5 chip package structure 500 as the region where chip 410 is seated, which is bounded by the walls of molding compound 530 on the sides and the cold-end outer surface of substrate 130 (the outer face of the first insulating and heat-conducting layer composite 130+160) at the base. This is a groove defined between the packaging structure (molding compound 530) and the first insulating and heat-conducting layer (130+160). The fact that molding compound 530 is part of a "chip package structure" rather than a standalone thermoelectric device packaging does not remove it from the scope of the claim, which does not restrict the packaging structure to any particular context.
Applicant's argument (Remark page 8) that chip 410 is a "separate component" and its position does not define a groove co-defined with an insulating layer.
In response, the argument is not persuasive. The groove is defined by the structural geometry of the molding compound 530 walls and the cold-end surface of the first insulating and heat-conducting layer composite (130+160), not by the presence or absence of chip 410. Chip 410 merely occupies the groove; it does not define it. The groove exists as a physical space bounded by those structures whether chip 410 is present or not.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/W.M/Examiner, Art Unit 3763
/FRANTZ F JULES/Supervisory Patent Examiner, Art Unit 3763
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