DETAILED ACTION
This action is responsive to the amendment received March 9, 2026. The amendment has been entered.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1, 4-5, and 7-11 are rejected under 35 U.S.C. 103 as being unpatentable over Turner et al. (US 2003/0186513) in view of Muntifering et al. (US 6,162,703), Akram et al. (US 2006/0043599), Oliver et al. (US 2007/0045632), Lai et al. (US 2011/0193219), and Xue et al. (US 2013/0037935).
(Re Claim 1) Turner teaches a method of manufacturing a semiconductor device, the method comprising (see Figs. 2A-3B and ¶¶47-77):
forming a chip region in which a semiconductor element (37/77) is formed on a principal surface of a main substrate (32/50);
forming a groove (40/52) around the chip region on the principal surface of the main substrate;
forming a recess for forming a through electrode in the main substrate, the recess having a depth less than a depth of the groove (recesses at 33/73, filled with 34, 36, 38);
forming the through electrode in the recess after the recess is formed (recesses at 33/73, filled with 34, 36, 38, ¶¶47-54), and thinning the main substrate from a backside of the main substrate to cause the groove and the through electrode to reach the backside of the main substrate, thereby singulating the chip region into a chip (Figs. 2B-2C, 3B, the wafer is thinned to cause the groove 40/52/80 to reach the backside thereby singulating the devices and the vias at 33/73 are also exposed).
Turner is silent regarding bonding a support substrate onto the principal surface of the main substrate by an adhesive layer while forming an empty space between a bottom of the groove and the adhesive layer after the through electrode is formed; and that the thinning is performed after the support substrate is bonded. A PHOSITA would be motivated to look to related art to teach details with respect to how to hold the wafer when thinning the wafer from the backside. Related art from Muntifering teaches when thinning a wafer from the backside to singulate the wafer by exposing grooves formed in the frontside the wafer is bonded to a support with an adhesive (see Figs. 4-5 and col 5 lines 4-24). When doing this, air gaps are formed between the adhesive layer 14 and the bottoms of the trenches 31 as shown in Fig. 4. Mounting the wafer in this manner provides mechanical support and keeps the dies securely in place during the singulation. A PHOSITA would find it obvious to mount the wafer according to Muntifering when thinning and singulating Turner’s wafer.
Turner is silent regarding wherein the thinning of the main substrate from the backside thereof is carried out by one of a mechanical grinding method, chemical mechanical polishing, mechano-chemical polishing, or a combination thereof. Turner discloses conventional wafer thinning may be accomplished by grinding, CMP, or etching (¶11). In light of this disclosure of alternative conventional methods, a PHOSITA would find these methods obvious to try to determine if any of these offer any advantages over Turner’s plasma process. Further still, a PHOSITA may not have access to the magnetic mirror plasma apparatus disclosed by Turner (Fig. 8) while having access to more readily available, conventional tools for CMP/grinding. A PHOSITA would be motivated to look to related art to determine other suitable methods for thinning device wafers having TSVs, specifically within the context of wafer level packaging (WLP). Related art from Akram teaches (Figs. 9-28) processes suitable for wafer level packaging (abstract, ¶¶3, 4, 61) for a device wafer having a TSV wherein a thinning operation is required (Fig. 23), and discloses the wafer may be thinned by various processes including CMP and back-grinding (¶53). Related art from Oliver teaches (Figs. 7-8) processes suitable for wafer level packaging (¶¶8, 25, 29, 30, 55) for a device wafer having a TSV wherein a thinning operation is required (Fig. 8), and discloses the wafer may be thinned by various processes including CMP and back-grinding (¶58). Related art from Lai teaches (Figs. 8A-8B) processes suitable for wafer level packaging (¶2) for a device wafer having a TSV wherein a thinning operation is required (Fig. 8B), and discloses the wafer may be thinned by various processes including CMP and back-grinding (¶37). Related art from Xue teaches (Figs. 3A-3F) processes suitable for wafer level packaging (¶30) for a device wafer having a TSV wherein a thinning operation is required (Fig. 3E), and discloses the wafer may be thinned by various processes including CMP and back-grinding (¶31). In light of the teaching of the prior art, a PHOSITA would recognize that in addition to the plasma etching disclosed by Turner, other techniques for thinning a device wafer for WLP and having TSVs such as CMP and/or grinding are also well known in the art and conventionally used to thin device wafers having TSVs. Grinding and CMP are generally considered superior for bulk wafer thinning than plasma etching due to their high material removal rates, cost-effectiveness, and capability to achieve high-precision global flatness. While plasma etching is excellent for precision, selectivity, and high aspect ratio processes, etc., it is slow and expensive for bulk, high-volume thinning. In view of the prior art, and knowledge of the advantages of CMP and/or grinding noted above, a PHOSITA would find it obvious to select either CMP or grinding for thinning the wafer for their known advantages and being widely adopted and readily available. Also, based on ample evidence from Akram, Oliver, Lai, and Xue, the mechanical processes of CMP and/or grinding are clearly compatible with device wafers for WLP having TSVs, regardless of Turner’s biased opinions disparaging conventional processes in favor of the inventors’ disclosed process (¶¶11-14).
(Re Claim 4) wherein the groove around the chip region is formed by cutting with a dicing blade (¶¶54,57).
(Re Claim 5) wherein the groove around the chip region is formed by etching (¶¶54,59).
(Re Claim 7) wherein the empty space is fully disposed within the groove (Muntifering Fig. 4).
(Re Claim 8) wherein the empty space extends from the bottom of the groove to the adhesive layer (Muntifering Fig. 4).
(Re Claim 9) wherein the empty space extends from the bottom of the groove to a bottom surface of the adhesive layer (Muntifering Fig. 4).
(Re Claim 10) wherein the empty space is void of any physical, solid structure (Muntifering Fig. 4).
(Re Claim 11) wherein the adhesive layer has a thickness and the main substrate is thinned to have a thickness that is the same as or less than the thickness of the adhesive.
There are multiple interpretations: 1. see Muntifering Fig. 5 clearly showing the adhesive 14 is thicker than the thinned substrate/dies, drawings may be relied upon for what they reasonably disclose and suggest to one of ordinary skill in the art and Fig. 5 shows the thinned dies are less than the thickness of the adhesive; 2. alternatively considering the method, the portion of the thinned wafer that is removed in the thinning process in Fig. 4 corresponding to the grooves is thinned until it is gone, such that just before the devices are singulated, the substrate in the locations of the grooves will have a thickness that is the same as or less than the thickness of the adhesive.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Turner et al. and Muntifering et al. as applied above, and further in view of Lin et al. (US 2013/0134559, of record).
(Re Clam 3) Turner is silent regarding forming, on the backside of the main substrate, a back-surface wiring electrically connected to the through electrode after cutting out a portion that is to be a chip of the chip region. Turner thins the wafer to simultaneously expose the through vias and singulate the wafer and at this step the through vias are exposed but not connected to anything. A PHOSITA would recognize that in order to use the vias in a functional device, additional wiring, interconnects, etc. are required, and obviously one cannot apply metallization prior to the thinning step since the thinning would remove or destroy the metal. Therefore, additional wiring for making connections with the vias must be formed after Turner’s thinning step that exposes the vias and singulates the dies. Related art from Lin teaches after thinning the wafer, additional backside wiring is formed (Fig. 8, backside wiring 64 is connected to the through vias after the wafer is thinned and singulated). A PHOSITA would find it obvious to form backside wiring after the thinning step as taught by Lin because doing it before the thinning step simply would not work or make sense as the thinning would remove or damage the wiring.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Turner et al. and Muntifering et al. as applied above, and further in view of Kato et al. (US 2012/0018854), Ohashi et al. (US 2005/0269717), and Martens et al. (US 2013/0084659), each newly cited.
(Re Claim 6) Turner and Muntifering are silent regarding bonding a film for transfer to the back surface of the thinned main substrate; and removing the support substrate and adhesive layer, thereby separating the main substrate into the chips on the film for transfer by virtue of the space formed inside of the groove.
While Muntifering teaches the conventional process of expanding the tape and picking the dies from the tape, a PHOSITA would recognize alternative techniques for removing the singulated dies are well known in the art. Related art from Kato teaches after the thinning to singulate the dies, a transfer film is bonded to the backside and then all of the dies are separated from the adhesive and support substrate (Figs. 4A-5C). Related art from Ohashi similarly teaches after the thinning to singulate the dies, a transfer film is bonded to the backside and then all of the dies are separated from the adhesive and support substrate (Figs. 1-5). Related art from Martens also similarly teaches after the thinning to singulate the dies, a transfer film is bonded to the backside and then all of the dies are separated from the adhesive and support substrate (Figs. 4-7A). Transferring all of the dies at once using a transfer film is faster than a serial operation of picking one die at a time, allows for the die positions to be maintained for subsequent processes, tracking, and traceability, and allows for additional batch processing, e.g. packaging steps, to be performed. In view of the prior art, this well-known alternative offers several advantages and would be obvious to a PHOSITA.
Response to Arguments
Applicant’s arguments have been considered but are not persuasive. Applicant argues that Turner discusses a wafer level package process (WLP), and while conventional thinning processes are disclosed, e.g. CMP, grinding, etc., Turner disparages these other processes in favor of the inventors’ plasma process, and based on Turner’s discussion, Applicant asserts Turner teaches away from these well-known thinning processes. The Examiner disagrees with Turner’s mischaracterization in ¶14 stating CMP cannot be used on WLP devices (it clearly can be used) and that CMP has a low throughput (CMP is considered a high throughput process, i.e. many wafers can be polished simultaneously, compared to plasma etching a single wafer at a time, pump down times, etc.). Turner’s statements are not true. CMP and/or grinding is used successfully on WPL device wafers having devices and TSVs, just like Turner’s wafer, without resulting in an inoperable process or device as evidenced by Akram, Oliver, Lai, and Xue. It appears Turner is biased towards their disclosed magnetic mirror plasma process. Related art from Akram teaches (Figs. 9-28) processes suitable for wafer level packaging (abstract, ¶¶3, 4, 61) for a device wafer having a TSV wherein a thinning operation is required (Fig. 23), and discloses the wafer may be thinned by various processes including CMP and back-grinding (¶53). Related art from Oliver teaches (Figs. 7-8) processes suitable for wafer level packaging (¶¶8, 25, 29, 30, 55) for a device wafer having a TSV wherein a thinning operation is required (Fig. 8), and discloses the wafer may be thinned by various processes including CMP and back-grinding (¶58). Related art from Lai teaches (Figs. 8A-8B) processes suitable for wafer level packaging (¶2) for a device wafer having a TSV wherein a thinning operation is required (Fig. 8B), and discloses the wafer may be thinned by various processes including CMP and back-grinding (¶37). Related art from Xue teaches (Figs. 3A-3F) processes suitable for wafer level packaging (¶30) for a device wafer having a TSV wherein a thinning operation is required (Fig. 3E), and discloses the wafer may be thinned by various processes including CMP and back-grinding (¶31). In light of the teaching of the prior art, a PHOSITA would recognize that in addition to the plasma etching disclosed by Turner, other techniques for thinning a device wafer for WLP and having TSVs such as CMP and/or grinding are also well known in the art and conventionally used to thin device wafers having TSVs. Grinding and CMP are generally considered superior for bulk wafer thinning than plasma etching due to their high material removal rates, cost-effectiveness, and capability to achieve high-precision global flatness. While plasma etching is excellent for precision, selectivity, and high aspect ratio processes, etc., it is slow and expensive for bulk, high-volume thinning. Plasma etching can also cause surface damage, roughness, excessive heating, and charging/ESD damage. In view of the prior art, and knowledge of the advantages of CMP and/or grinding noted above, a PHOSITA would find it obvious to select either CMP or grinding for thinning the wafer for their known advantages and being well established processes, widely adopted, and readily available. Applicant further argues, without evidence, that Turner’s wafer cannot be processed according to Muntifering because the grinding would destroy the devices. This is not persuasive, first noting Muntifering is grinding a device wafer and does not destroy the devices, in addition see Akram, Oliver, Lai, and Xue as discussed above, all disclosing CMP and/or grinding, while none disclose damaging the devices, wiring, TSVs, etc., present.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The additional cited art teaches wafer level packaging processes wherein CMP or grinding is used to thin a device wafer having TSVs, without damaging or rendering the device wafer inoperable.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIK T. K. PETERSON whose telephone number is (571)272-3997. The examiner can normally be reached M-F, 9-5 pm (CST).
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/ERIK T. K. PETERSON/ Primary Examiner, Art Unit 2898