DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Application
Applicant’s election without traverse of Species III claims 1-7, and 9-11 in the reply filed on 01/12/2026 is acknowledged. Claim 8 withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Species I and II.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2 and 9-10 are rejected under 35 U.S.C. 102 (a) (1) as being anticipated by Hara et al (US20120108963A1).
Re claim 1 Hara does teach a semiconductor device (4, fig 1) [0027] in which a first semiconductor element (11, fig 1) [0036] and one or a plurality of second semiconductor elements (12, fig 1) [0036] are connected in series (see fig 1), wherein
the first semiconductor element (11, fig 1) and the second semiconductor element (12, fig 1) each has a control signal output terminal (18/19, fig 1) [0032] between a source terminal ( source terminal of 11 and 12, fig 1) and a drain terminal (drain terminals of 11 and 12, fig 1) or between an emitter terminal and a collector terminal, and
a gate terminal (gate of 12, fig 1) [0041] of the second semiconductor element (12, fig 1) is connected to the control signal output terminal (18 through 3, fig 1) of the first semiconductor element (11, fig 1) or the second semiconductor element connected in series adjacent to a source or emitter side of the second semiconductor element.
Re claim 2 Hara teaches, the semiconductor device according to claim 1, wherein a gate terminal (gate terminal of 11) and a source terminal of the first semiconductor element (bottom terminal of 11, fig 1) are connected to a gate drive circuit (1, fig 1) [0036], and ON/OFF control of all semiconductor elements [0044] of the first semiconductor element (11, fig 1) and the second semiconductor element (12, fig 1) is enabled by a drive signal from the gate drive circuit (1, fig1) to the gate terminal of the first semiconductor element [0012].
Re claim 9 Hara teaches the semiconductor device according to claim 1, wherein a diode (10, fig 1) [0036] is connected between a drain terminal (drain terminals of 11 and 12, fig 1) [0036] or a collector terminal and the control signal output terminal (18 and 19, fig 1) [0032] of each of the first semiconductor element (11, fig 1) [0036] and the second semiconductor element (12, fig 1) [0036].
Re claim 10 Hara teaches the semiconductor device according to claim 9, wherein the diode (10, fig 1) [0036] is an avalanche diode or a Zener diode [0036].
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3 and 5 is rejected under 35 U.S.C. 103 as being unpatentable over Hara et al (US20120108963A1) in view of Endo et al (US 20150171117A1).
Re claim Hara teaches the semiconductor device according to claim 1,
Hara does not teach the second semiconductor element is a depletion-type semiconductor element in which a threshold of gate voltage is a negative voltage.
Endo teaches the second semiconductor element (251, fig 5A) [0118] is a depletion-type semiconductor element in which a threshold of gate voltage is a negative voltage [0118].
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by Endo into the structure of Hara to include the second semiconductor element is a depletion-type semiconductor element in which a threshold of gate voltage is a negative voltage as claimed.
The ordinary artisan would have been motivated to modify Hara based on the teaching of Endo in the above manner for the purpose of power consumption is sufficiently reduced [0181].
Re claim 5 Hara in view of Endo teaches the semiconductor device according to claim 3.
wherein at least one of the first semiconductor element (12, fig 2) [Hara 0036] and the second semiconductor element (20, fig 2) [Hara, 0073] includes a lateral IGBT [Hara, 0073] and a diode connected in antiparallel to the lateral IGBT (34, fig 3) [Hara, 0073].
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Hara modified by Endo as applied to claim 3 further in view of Bobde et al (US 20080079035A1).
Re claim 4 Hara in view of Endo teach the semiconductor device according to claim 3,
Hara and Endo do not teach the first semiconductor element and the second semiconductor element are lateral MOSFETs.
Bobde teaches the first semiconductor element (110, fig 3A) [0027] and the second semiconductor element (120, fig 3A) [0027] are lateral MOSFETs.[0027].
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by Bobde into the structure of Hara and Endo to include the first semiconductor element and the second semiconductor element are lateral MOSFETs. as claimed.
The ordinary artisan would have been motivated to modify Hara & Endo based on the teaching of Bobade in the above manner for the purpose to achieve improved circuit configuration [0008]
Claims 6 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Hara modified by Endo as applied to claim 3 further in view of Huang et al (US20160262228A1).
Re claims 6-7 Hara in view of Endo teach, the semiconductor device according to claim 3,
Hara and Endo do not teach at least one of the first semiconductor element and the second semiconductor element is an HEMT claim 6 and at least one of the first semiconductor element and the second semiconductor element includes an HEMT and a diode connected in antiparallel to the HEMT claim 7.
Huang does teach at least one of the first semiconductor element (T1, fig 2) [0054] and the second semiconductor element (T2, fig 2) [0054] is an HEMT claim 6 and at least one of the first semiconductor element (T1, fig 2) [0054] and the second semiconductor element [0054] includes an HEMT [0051] and a diode (DVF3, fig 2) [0062] connected in antiparallel to the HEMT (T2, fig 2) claim 7.
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by Huang into the structure of Hara and Endo to include at least one of the first semiconductor element and the second semiconductor element is an HEMT claim 6 and at least one of the first semiconductor element and the second semiconductor element includes an HEMT and a diode connected in antiparallel to the HEMT claim 7 as claimed.
The ordinary artisan would have been motivated to modify Hara and Endo based on the teaching Huang in the above manner for the purpose of improving the performance of the device.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Hara et al (US20120108963A1) in view of Huang et al (US20160262228A1).
Re claim 11 Hara teaches, the semiconductor device
Hara does not teach a power converter using the semiconductor device according to claim 1.
Huang does teach a power converter using the semiconductor device according to claim 1. [0005].
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by Huang into the structure of Hara to include a power converter using the semiconductor device according to claim 1 as claimed.
The ordinary artisan would have been motivated to modify Hara based on the teaching of Huang in the above manner for the purpose of improve the performance of the device.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PRATIKSHA J LOHAKARE whose telephone number is (571)270-1920. The examiner can normally be reached Monday - Friday 7.30 am-4.30 pm.
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/PRATIKSHA JAYANT LOHAKARE/ Examiner, Art Unit 2818
/DUY T NGUYEN/ Primary Examiner, Art Unit 2818 2/11/26