DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kasuya et al (US Publication 20090115050).
Regarding claim 1, Kasuya teaches an interposer, comprising:
a wiring substrate that includes a first insulating resin (Fig. 4, 121, para 63, resin);
a wiring via for electrical connection between a top surface of the wiring substrate and-a bottom surface of the wiring substrate (Fig. 4, 126);
a plurality of heat dissipation vias in a region (Fig. 3, 127) of a chip mounting section (Fig. 3, 122) wherein
the wiring substrate further includes the chip mounting section on the top surface of-the wiring substrate (Fig. 4, 122 on top surface of 121) and
a semiconductor chip is mounted on the chip mounting section of the wiring substrate (Fig. 4, 111);[[ and]]
an insulating layer that covers the top [[a]] surface of the wiring substrate (Fig. 4, 125), wherein the insulating layer includes:
an opening for [[of]] the wiring via (Fig. 3, openings in 125 for 126), and
a plurality of openings for [[of ]] the plurality of heat dissipation vias (Fig. 3, openings in 125 for 127): and a filling portion in each opening of the plurality of openings (Fig. 3, tops of 126/127), wherein
the filling portion includes a resin (para 94, resin) and
the insulating layer includes a second insulating resin that has a thermal conductivity lower than a thermal conductivity of the resin (Fig. 4, 125, solder resist with lower thermal conductivity than para 94 metal particle resin).
Regarding claim 2, Kasuya teaches the limitations of claim 1 upon which claim 2 depends.
Kasuya teaches the plurality of heat dissipation vias has a plurality of circular openings (Fig. 3, 127 circular), respectively, with a same diameter (para 79)[[ and]]
the plurality of heat dissipation vias is are in a grid pattern and in the grid pattern, the plurality of heat dissipation vias is at equal intervals (Fig. 3, 127 in grid pattern, para 79).
Regarding claim 3, Kasuya teaches the limitations of claim 1 upon which claim 3 depends.
Kasuya teaches the second insulating resin includes a solder resist (Fig. 3, 125, para 95, solder resist), and
the resin includes a silver (Ag) paste (para 98, silver paste).
Regarding claim 7, Kasuya teaches a method of manufacturing an interposer, the method comprising
forming, on a wiring substrate that includes a first insulating resin (Fig. 4, 121, para 13), a wiring via for electrical connection between a top surface of the wiring substrate and a bottom surface of the wiring substrate (Fig. 3/4, 126, para 69);
forming, on the wiring substrate. a plurality of heat dissipation vias in a region of a chip mounting section (Fig. 3/4, 127 in mounting section 122, para 69), wherein
the wiring substrate further includes the chip-mounting section on the top surface of the wiring substrate (Fig. 3/4, 122 on top surface of 121), and
a [[the ]] semiconductor chip on the chip mounting section of the wiring substrate (Fig. 4, 111 on 122);[[ and]]
forming an insulating layer to cover the top [[a]] surface of the wiring substrate (Fig. 3, 125)
forming, in the insulating layer, an opening for [[of ]] the wiring via (Fig. 3, openings in 125 for 126) [[and]];
forming. in the insulating layer. a plurality of openings for [[of]] the plurality of heat dissipation vias (Fig. 3, openings in 125 for 127); and
filling a filling portion in each opening of the plurality of openings (para 94), wherein
the filling portion includes a resin (para 94, resin), and
the insulating layer includes a second insulating resin that has a thermal conductivity lower than a thermal conductivity of the resin (Fig. 4, 125, solder resist with lower thermal conductivity than para 94 metal particle resin).
Regarding claim 8, Kasuya teaches the limitations of claim 7 upon which claim 8 depends.
Kasuya teaches the formation of the plurality of heat dissipation vias includes;
forming the plurality of heat dissipation vias in [into]] a circular shape with a same opening diameter (Fig. 3, 127 circular, para 79);[[,]] and
forming the plurality of heat dissipation vias in a grid pattern, wherein in the grid pattern, the plurality of heat dissipation vias is at equal intervals (Fig. 3, 127 in grid pattern, para 79).
Regarding claim 9, Kasuya teaches the limitations of claim 7 upon which claim 9 depends.
Kasuya teaches the second insulating resin includes a solder resist (Fig. 3, 125, para 95, solder resist), and the resin includes a silver (Ag) paste (para 98, silver paste).
Regarding claim 16, Kasuya teaches the limitations of claim 1 upon which claim 16 depends.
Kasuya teaches wherein the filling portion is in direct contact with each heat dissipation via of the plurality of heat dissipation vias (Fig. 3, top portion of 127s).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4-6, and 10-15 are rejected under 35 U.S.C. 103 as being unpatentable over Kasuya et al (US Publication 20090115050).
Regarding claim 4, Kasuya teaches a circuit device, comprising:
a wiring substrate that includes a first insulating resin (Fig. 4, 121, para 63, resin);
a wiring via for electrical connection between a top surface of the wiring substrate and a bottom surface of the wiring substrate (Fig. 4, 126);
a plurality of heat dissipation vias in a region (Fig. 3, 127) of a chip mounting section (Fig. 3, 122), wherein the wiring substrate further includes the chip mounting section on the top surface of the wiring substrate (Fig. 3, 122):
a semiconductor chip on the chip mounting section of the wiring substrate (Fig. 4, 111);
an insulating layer that covers the top [[a]] surface of the wiring substrate (Fig. 3, 125), wherein the insulating layer includes:
an opening for [[of]] the wiring via (Fig. 3, openings in 125 for 126), and
a plurality of openings for [of ]] the plurality of heat dissipation vias (Fig. 3, openings in 125 for 127); a filling portion in each opening of the plurality of openings (Fig. 3, top of 126/127), wherein
the filling portion includes a resin (para 94, resin), and
the insulating layer includes a second insulating resin that has a thermal conductivity lower than a thermal conductivity of the resin (Fig. 4, 125, solder resist with lower thermal conductivity than para 94 metal particle resin): and
an adhesive layer that includes the resin (Fig. 4, 112, para 98, Ag paste), wherein the adhesive layer:
adhesively fixes a back surface of the semiconductor chip to the chip mounting section (Fig. 4, 112 affixing 111 on 122), and
thermally connects the semiconductor chip to the plurality of heat dissipation vias (Fig. 4, 111 thermally connected to 127s).
Kasuya does not specifically disclose the filling portion includes a resin and the adhesive layer that includes the resin (as described above, they both include resins, but not necessarily the same resin).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Kasuya to include wherein the filling portion and the adhesive layer to include the same resin, which in this case would be Ag paste, in order to more efficiently form the semiconductor device and make it easier for the creator to use the same material, thus increasing efficiency and decreasing the cost of the device.
Regarding claim 5, Kasuya teaches the limitations of claim 4 upon which claim 5 depends.
Kasuya teaches the plurality of heat dissipation vias has a plurality of circular openings (Fig. 3, 127 circular), respectively, with a same diameter (para 79), [[ and]]
the plurality of heat dissipation vias is in a grid pattern, and
in the grid pattern, the plurality of heat dissipation vias is at equal intervals (Fig. 3, 127 in grid pattern, para 79).
Regarding claim 6, Kasuya teaches the limitations of claim 4 upon which claim 6 depends.
Kasuya teaches the second insulating resin includes a solder resist (Fig. 3, 125, para 95, solder resist), and
the resin includes a silver (Ag) paste (para 98, silver paste).
Regarding claim 10, Kasuya teaches a method of manufacturing a circuit device, the method comprising:
forming, on a wiring substrate that includes a first insulating resin (Fig. 4, 121, para 13), a wiring via for electrical connection between a top surface of the wiring substrate and a bottom surface of the wiring substrate (Fig. 3/4, 126, para 69);
forming. on the wiring substrate. a plurality of heat dissipation vias in a region of a chip mounting section (Fig. 3/4, 127 in mounting section 122, para 69), wherein the wiring substrate further includes the chip mounting section on the top surface of the wiring substrate (Fig. 3/4, 122 on top surface of 121);
forming an insulating layer to cover the top [[a]] surface of the wiring substrate (Fig. 3, 125)
forming, in the insulating layer. an opening for [of]] the wiring via (Fig. 3, openings in 125 for 126) [[ and]]
forming. in the insulating layer. a plurality of openings [[of ]] for the plurality of heat dissipation vias (Fig. 3, openings in 125 for 127);
filing a filling portion in each opening of the plurality of openings (para 94), wherein
the filling portion includes a resin (para 94, resin), and
the insulating layer includes a second insulating resin that has a thermal conductivity lower than a thermal conductivity of the resin (Fig. 4, 125, solder resist with lower thermal conductivity than para 94 metal particle resin);
forming an adhesive layer that includes a resin (Fig. 4, 112, para 98, Ag paste);
mounting a semiconductor chip on the chip mounting section of the wiring substrate (Fig. 4, 112 affixing 111 to 122) wherein the adhesive-laver:
fixes a back surface of the semiconductor chip to the chip mounting section (Fig. 4, back surface of 111 affixed to 122); and
thermally connects the semiconductor chip to [[and ]] the plurality of heat dissipation vias (Fig. 4, 111 thermally connected to 127s); and
bonding and fixing the semiconductor chip to the adhesive layer (Fig. 4, 111 and 112).
Kasuya does not specifically disclose the filling portion includes a resin and the adhesive layer that includes the resin (as described above, they both include resins, but not necessarily the same resin).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Kasuya to include wherein the filling portion and the adhesive layer to include the same resin, which in this case would be Ag paste, in order to more efficiently form the semiconductor device and make it easier for the creator to use the same material, thus increasing efficiency and decreasing the cost of the device.
Regarding claim 11, Kasuya teaches the limitations of claim 10 upon which claim 11 depends.
Kasuya teaches wherein the formation the plurality of heat dissipation vias includes;
forming the plurality of heat dissipation vias in a circular shape with a same diameter (Fig. 3, 127 circular, para 79);[[,]] and
forming the plurality of heat dissipation vias in a grid pattern, wherein in the grid pattern. the plurality of heat dissipation vias is at equal intervals (Fig. 3, 127 in grid pattern, para 79).
Regarding claim 12, Kasuya teaches the limitations of claim 10 upon which claim 12 depends.
Kasuya teaches the second insulating resin includes a solder resist (Fig. 3, 125, para 95, solder resist), and the resin includes a silver (Ag) paste (para 98, silver paste).
Regarding claim 13, Kasuya teaches a method of manufacturing a circuit device, the method comprising
forming, on a wiring substrate that includes a first insulating resin (Fig. 4, 121, para 13), a wiring via for electrical connection between a top surface both surfaces of the wiring substrate and a bottom surface of the wiring substrate (Fig. 3/4, 126, para 69);
forming, on the wiring substrate, a plurality of heat dissipation vias in a region of a chip mounting section (Fig. 3/4, 127 in mounting section 122, para 69), wherein the wiring substrate further includes the chip mounting section on the top surface of the wiring substrate (Fig. 3/4, 122 on top surface of 121);
forming an insulating layer to cover the top [[a]] surface of the wiring substrate (Fig. 3, 125)
forming, in the insulating layer. an opening [[of ]]for the wiring via (Fig. 3, openings in 125 for 126) [[ and]]
forming, in the insulating layer. a plurality of openings for [[of ]] the plurality of heat dissipation vias (Fig. 3, openings in 125 for 127);
filling a filling portion in each opening of the plurality of openings (para 94) wherein
the filling portion includes a resin (para 94, resin), and
the insulating layer includes a second resin that has a thermal conductivity lower than a thermal conductivity of the resin (Fig. 4, 125, solder resist with lower thermal conductivity than para 94 metal particle resin);
coating an adhesive layer including a resin, on a back surface of a [[the]] semiconductor chip (Fig. 4, 112, para 98, Ag paste); and
bonding and fixing, via the coated adhesive layer, the semiconductor chip to the chip mounting section [[on ]] of the wiring substrate (Fig. 4 111 affixed to 122 via 112), wherein the adhesive layer:
fixes the back surface of the semiconductor chip to the chip mounting section (Fig. 4, back of 111 attached to 122); and
thermally connects the semiconductor chip [[and ] to the plurality of heat dissipation vias (Fig. 4, 111 thermally connected to 127s).
Kasuya does not specifically disclose the filling portion includes a resin and the adhesive layer that includes the resin (as described above, they both include resins, but not necessarily the same resin).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Kasuya to include wherein the filling portion and the adhesive layer to include the same resin, which in this case would be Ag paste, in order to more efficiently form the semiconductor device and make it easier for the creator to use the same material, thus increasing efficiency and decreasing the cost of the device.
Regarding claim 14, Kasuya teaches the limitations of claim 13 upon which claim 14 depends.
Kasuya teaches wherein the formation of the plurality of heat dissipation vias includes;
forming the plurality of heat dissipation vias in a circular shape with a same diameter (Fig. 3, 127 circular, para 79);[[,]] and
forming the plurality of heat dissipation vias in a grid pattern, wherein in the grid pattern. the plurality of heat dissipation vias is at equal intervals (Fig. 3, 127 in grid pattern, para 79).
Regarding claim 15, Kasuya teaches the limitations of claim 13 upon which claim 15 depends.
Kasuya teaches wherein the second insulating resin includes a solder resist (Fig. 3, 125, para 95, solder resist), and
the resin includes a silver (Ag) paste (para 98, silver paste).
Response to Arguments
A new rejection has been made in light of a different embodiment of the same reference used in the previous rejection based on the limitations of the amended claims, therefore, Applicants arguments are moot.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NICHOLAS HUTSON whose telephone number is (571)270-1750. The examiner can normally be reached Mon-Fri 8am-5pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jeff Natalini can be reached at 571 272 2266. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/NICHOLAS LELAND HUTSON/ Examiner, Art Unit 2818
/JEFF W NATALINI/ Supervisory Patent Examiner, Art Unit 2818