DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This Office Action is in response to Applicant's amendments filed October 28, 2025. Claims 1, 4, and 6-8 have been amended. No claims have been added. Claim 9 has been canceled. Claims 10-12 stand withdrawn. Currently, claims 1-8 are pending.
Response to Arguments
Applicant’s arguments with respect to claim 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, and 6 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Takachi (US 20130038764 A1).
Regarding claim 1, Fig. 3 of Takachi discloses a semiconductor package (Fig. 3, CSP structure 1A, ¶ [0016]) comprising:
a semiconductor substrate (Fig. 3, “substrate on which the CSP is mounted”, see Annotation 1, Fig. 3 of Takachi, “SUB”, ¶ [0014]) including;
a pixel region (see Annotation 1, Fig. 3 of Takachi, “PIX”) that includes a light receiving element (Fig. 3, light receiving unit 21, ¶ [0006]), and
a peripheral region (see Annotation 1, Fig. 3 of Takachi, “PER”) around the pixel region (PIX);
an on-chip lens (see Annotation 1, Fig. 3 of Takachi, “OCL”, ¶ [0084]) on an incident surface side of the semiconductor substrate (SUB);
a resin layer (Fig. 3, resin 4, ¶ [0007]) in contact with a central portion of the on-chip lens (OCL), wherein the central portion includes a most protruding portion of the on-chip lens (OCL);
a glass substrate (Fig. 3, sealing glass 3, ¶ [0007]) in contact with a first surface (top surface in Fig. 3) of the resin layer (4), wherein the first surface is opposite to a second surface (bottom surface in Fig. 3) of the resin layer (4), and the second surface is in contact with the on-chip lens (OCL),
a space (see Annotation 1, Fig. 3 of Takachi, “SPC”) between a peripheral portion of the on-chip lens (OCL) and the resin layer (4), wherein the peripheral portion of the on-chip lens (OCL) is around the central portion of the on-chip lens (OCL); and
a flat region (see Annotation 1, Fig. 3 of Takachi, “FR”) in the peripheral region (PER), wherein the flat region (FR) has a same height as an upper end of the on-chip lens (OCL), and in the peripheral region (PER), the flat region (FR) holds the resin layer (4) at a same height as the pixel region (PIX).
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Annotation 1, Fig. 3 of Takachi
Regarding claim 2, Fig. 3 of Takachi discloses the semiconductor package according to claim 1 as applied above, and further discloses wherein the resin layer (4) has a refractive index within a range of 1.0 to 1.5 (Fig. 3, “the refractive index of a transparent resin 4 is… approximately 1.5, ¶ [0028]).
Regarding claim 3, Fig. 3 of Takachi discloses the semiconductor package according to claim 2 as applied above, and further discloses wherein the refractive index of the resin layer (4) is greater than a refractive index of air (Fig. 3, “the refractive index of a transparent resin 4 is… approximately 1.5, ¶ [0028]).
Regarding claim 6, Fig. 3 of Takachi discloses the semiconductor package according to claim 1 as applied above, and further discloses further comprising a color filter (see Annotation 1, Fig. 3 of Takachi, “CF”, ¶ [0081]) between the semiconductor substrate (SUB) and the on-chip lens (OCL).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4, and 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over Takachi (US 20130038764 A1) in view of Hirano et al. (US 20160027830 A1) herein after “Hirano”.
Regarding claim 4, Fig. 3 of Takachi discloses the semiconductor package according to claim 1 as applied above, but Takachi fails to explicitly disclose wherein the resin layer is made of epoxy resin, low-melting glass, or ultraviolet curable resin.
In the similar field of endeavor of solid-state imaging elements, Fig. 4 of Hirano discloses wherein the resin layer (Fig. 4, material layer 222, ¶ [0069]) includes one of epoxy resin, low-melting glass, or ultraviolet curable resin (Fig. 4, “The second organic material layer 222 is formed of an… epoxy resin material”, ¶ [0070]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the semiconductor package of Takachi with the resin layer as disclosed by Hirano, to obtain the desired refractive properties (see Hirano, ¶ [0073]) and/or because the use of conventional materials to perform their known function is prima-facie obvious (MPEP 2144.07).
Regarding claim 7, Fig. 3 of Takachi discloses the semiconductor package according to claim 1 as applied above, but Takachi fails to disclose comprising a planarization layer between the semiconductor substrate and the color filter.
In the similar field of endeavor of solid-state imaging elements, Fig. 4 of Hirano discloses comprising a planarization layer (Fig. 4, planarization film 217, ¶ [0066]) between the semiconductor substrate (Fig. 4, substrate 211, ¶ [0065]) and the color filter (Fig. 4, color filter layer 218, ¶ [0067]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the semiconductor package of Takachi with the planarization film as disclosed by Hirano, to flatten the color filter region (see Hirano, ¶ [0066]).
Regarding claim 8, Fig. 3 of Takachi discloses the semiconductor package according to claim 1 as applied above, but Takachi fails to explicitly disclose comprising a wiring layer between the semiconductor substrate and the color filter.
In the similar field of endeavor of solid-state imaging elements, Fig. 4 of Hirano discloses comprising a wiring layer (Fig. 4, interconnection layer 212, ¶ [0065]) between the semiconductor substrate (211) and the color filter (218).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the semiconductor package of Takachi with the wiring layer as disclosed by Hirano, to provide interconnection in the device (see Hirano, ¶ [0065]).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Takachi (US 20130038764 A1) in view of Adkisson et al. (US 20080116537 A1) herein after “Adkisson”.
Regarding claim 5, Fig. 3 of Takachi discloses the semiconductor package according to claim 1 as applied above, but Takachi fails to explicitly disclose wherein a maximum height of the space is 100 nm or more.
In the similar field of endeavor of CMOS image sensors, Fig. 3 of Adkisson further discloses wherein a maximum height of the space is 100 nm or more (“the height of the air gap ranges from 2 µm up to 50 µm”, ¶ [0047]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the semiconductor package of Takachi with the space as disclosed by Adkisson, to avoid defects in the image (see Adkisson, ¶ [0047]).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/C.A.N./Examiner, Art Unit 2893
/YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893
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