DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The Amendment filed on 01/23/2026 has been entered. Claims 1-2, 5-11 and 14-20 remain pending in the application. Claims 3-4 and 12-13 were cancelled by way of previous amendment.
Claim Objections
Claim 14 is objected to because of the following informalities: “The device according to claim 13,9,” should read “The device according to claim 9,”, same as its previous version filed on 08/11/2025. Appropriate correction is required.
Claim Rejections - 35 USC § 112(a)
Claim 16 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 16 recites the limitations “a plurality of conductive vias vertically in line with the gate electrode and the field plate, and extending through the substrate to the gate terminal” and “the respective set of conductive vias including multiple conductive vias that are horizontally aligned with each other along the respective gate electrode and that are each directly contacting the gate terminal and the respective field plate.”.
Fig.5A shows the conductive via, element #22, extending through the substrate, element #5, and directly contacting the gate terminal, element #20, and the gate electrode, element #2, but not the field plate. The field plate, element #2b is shown in Fig.3A, on top of the gate, element #2a. Since the conductive via, extending through the substrate to the gate terminal, has to be vertically in line with the gate electrode, as shown in Fig.5A, it cannot directly contact with the field plate. Furthermore, no other parts of the specification appear to include a written description of how both limitations listed above may work together. Therefore, a person skilled in the art, at the time the application was filed, would have not recognized that the inventor was in possession of the invention as claimed, in view of the disclosure of the application as filed, and therefore, this constitutes new matter.
Claims 17-20 are also rejected as being depended on claim 16.
Claim Rejections - 35 USC § 112(b)
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 16 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 16 recites the limitations “ a field plate vertically in line with the gate electrode” , “a plurality of conductive vias vertically in line with the gate electrode and the field plate, and extending through the substrate to the gate terminal” and “the respective set of conductive vias including multiple conductive vias that are horizontally aligned with each other along the respective gate electrode and that are each directly contacting the gate terminal and the respective field plate.”. In order for the transistor to function the field plate cannot be located between the gate and the transistor channel. Therefore, in order for the field plate to be vertically in line with the gate electrode, as required by the limitation of claim 16, the field plate or part of the field plate, needs to be located on top and not below of the gate electrode. Also, the field plate may not directly contact the gate electrode. Therefore, it is not clear how the conductive vias, which are located below and in line with the gate electrode can directly contact the field plate. Furthermore, no other parts of the specification appear to include a written description of how this can be accomplished. This renders the claim indefinite.
Claims 17-20 are also rejected as being depended on claim 16.
For the purpose of examination, claim 16 will be interpreted as: A transistor comprising: a substrate; a gate terminal on a first surface of the substrate; a source terminal on a second surface of the substrate; a drain terminal opposite the source terminal on the second surface of the substrate; a plurality of source electrodes extending from the source terminal toward the drain terminal; a plurality of drain electrodes extending from the drain terminal toward the source terminal; and a plurality of gate electrodes between adjacent ones of the plurality of drain electrodes and the plurality of source electrodes, the plurality of gate electrodes being spaced from the gate terminal by the substrate, each gate electrode including: a field plate vertically in line with the gate electrode; and a plurality of conductive vias vertically in line with the gate electrode and the field plate, and extending through the substrate to the gate terminal, the gate terminal being spaced from the plurality of gate electrodes by the plurality of conductive vias, and the gate terminal being vertically in line with the plurality of conductive vias, the plurality of source electrodes, the plurality of drain electrodes, and the plurality of gate electrodes, each respective gate electrode being coupled to the gate terminal by a respective set of conductive vias of the plurality of conductive vias
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 16, 17, 19 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Li-Fan Lin et al. (United States Patent Application Publication Number, US 2015/0243657 A1) hereinafter referenced as Lin, in view of Wu et al., (United States Patent Application Publication Number, US 2006/0202272 A1), hereinafter references as Wu, in view of Zijian” Ray” Li et al., (United States Patent Application Publication Number, US 2015/0311330 A1), and in view of Jeon et al., (United States Patent Application Publication Number, US 2014/0091366 A1), hereinafter references as Jeon.
Regarding claim 16, Lin teaches a transistor comprising: a substrate (Fig.11, comprised of elements #300, paragraph [0071], row 17 and element #112 and 114, paragraph [0071], rows 6-7); a gate terminal (Fig.11, element #400, is connected to the gate electrodes through element #260 and so it is a gate terminal paragraph [0095], row 10-16), on a first surface of the substrate (Fig.11, element #400 is on the bottom surface of the substrate) a source terminal on a second surface of the substrate (Fig.7A, element #240, paragraph [0076], row 6, on the top surface of the substrate); a drain terminal (Fig.7A, element #250, paragraph [0076], row 6), opposite the source terminal (Fig.6, drain terminal, element #250 and source terminal, element #240 are on opposite ends) on the second surface of the substrate (Fig.7A, element #250 is on the top surface of the substrate); a plurality of source electrodes (each element #160 in Fig.6 corresponds to a source electrode, element #120, in Fig.2, paragraph [0061], row 5 ) extending from the source terminal toward the drain terminal (Fig.6, elements #160 extend from top to bottom); a plurality of drain electrodes (each element #170 in Fig.6 corresponds to a drain electrode, element #130, in Fig.2, paragraph [0061], rows 5-6); extending from the drain terminal toward the source terminal (Fig.6, elements #170 extend from bottom to top) and a plurality of gate electrodes (each element #180 in Fig.6 corresponds to a gate electrode, element #140, in Fig.2, paragraph [0072], rows 12-14) between adjacent ones of the plurality of drain electrodes and the plurality of source electrodes (Fig.2, elements #140 are between elements #120 and 130), the plurality of gate electrodes being spaced from the gate terminal by the substrate (Fig.11, gate electrodes, element #140 are located on the top surface of the substrate and the gate terminal, element #400 is located on the bottom of the substrate), including a field plate (Fig.2, element #145).
Lin does not teach the field plate vertically in line with the gate electrode. Wu teaches the field plate vertically in line with the gate electrode (Fig.7, field plate, element #96 is vertically in line with the gate electrode, element #92). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Wu and disclose the field plate vertically in line with the gate electrode. As disclosed by Wu, this allows the field plate to be integrally formed with the gate electrode, thus minimizing the number of process steps. Furthermore, having the field plate vertically in line with the gate electrode allows biasing both simultaneously using a shorter conduction path, which reduces electrical resistance and therefore allows for a larger current to flow.
The combination of Lin and Wu does not teach a plurality of conductive vias that extend through the substrate to the gate terminal. Li teaches each gate electrode (Fig.5, element #22, paragraph [0059], rows 9-11) including: a plurality of conductive vias (Fig.5, via element #50, paragraph [0059], rows 9-11), that extend through the substrate (Fig.6, element #50 extends through the substrate formed by layer element #14, #12 and #35) to the gate terminal (Fig.6, element #48 paragraph [0059], rows 9-11 is at the bottom of the substrate same as terminal element #400 of Lin) and the gate terminal being spaced from the plurality of gate electrodes by the plurality of conductive vias (Fig.6). Li further teaches each respective gate electrode (Fig.5, element #22, paragraph [0059], rows 9-11) being coupled to the gate terminal by a respective set of conductive vias of the plurality of conductive vias (Fig.6, element #48 paragraph [0059], rows 9-11 is at the bottom of the substrate same as terminal element #400 of Lin) (Fig.5 and 6, elements # 50 are identical and are horizontally aligned along the gate electrode, element #48, and are directly contacting element #48). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Li and disclose each gate electrode including a plurality of conductive vias that extend through the substrate to the gate terminal. Vias facilitate vertical electrical connections between the gate electrode and the gate terminal, enabling vertical integration, device miniaturization and efficient signal routing. Using a plurality of vias allows for a more robust contact by increasing the contact area. This reduces contact resistance which mitigates the voltage drops across the gate.
Li teaches the plurality of conductive vias vertically in line with the field plate (Fig.5, via element #50 are vertically in line with the field plate, element #28). The combination of Lin, Wu and Li does not teach the plurality of conductive vias vertically in line with the gate electrode and the field plate. Jeon teaches a via vertically in line with the gate electrode and directly contacting the gate electrode (Fig.16D, via element #151 is vertically in line and in direct contact with the gate electrode, element #200G-2). Since the field plate disclosed by Wu extends across the gate electrode (Fig.7) a via vertically in line with the gate electrode will also be vertically in line with the field plate. Therefore, the combination of Jeon and Wu teaches vias vertically in line with the gate electrode and the field plate and in direct contact with the gate electrode. It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Wu and Jeon and disclose vias vertically in line with the gate electrode and the field plate. Vias facilitate vertical electrical connection between the gate electrode and the gate terminal and having the vias vertically in line with the gate electrodes and the field plate allows biasing both simultaneously using the shorter conduction path, which reduces electrical resistance and therefore allows for a larger current to flow.
Lin further teaches the gate terminal being vertically in line with, the plurality of source electrodes, the plurality of drain electrodes, and the plurality of gate electrodes (Fig.11, element #400 is vertically in line with source electrodes, elements #120, drain electrodes, element #130 and gate electrodes, element #140, and element #400 covers the entire active region as shown in Fig.12). As noted above, Li teaches the plurality of vertical conductive vias between the gate terminal and the gate electrodes therefore, the gate terminal is vertically in line with the vias.
Regarding claim 17, the combination of Lin, Wu, Li and Jeon teaches the device of claim 16 as set forth in the obviousness rejection, Lin further teaches wherein the substrate includes gallium (paragraph [0061], rows 13-15).
Regarding claim 19, the combination of Lin, Wu, Li and Jeon teaches the device of claim 16 as set forth in the obviousness rejection. The combination of Lin, Wu, Li and Jeon does not teach the device of claim 16 further including an insulating film around each one of the plurality of conductive vias. Jeon teaches an insulating film around each one of the plurality of conductive vias. (Fig.16D, element #150, paragraph [0121], rows 8-9). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Jeon and disclose an insulating film around each one of the plurality of conductive vias. The film physically and electrically separates the conductive material inside the via from the electron gas in the transistor channel (Jeon, paragraph [0121], rows 7-9) and helps prevent diffusion of the conductive material (such as copper) outside the vias.
Regarding claim 20, the combination of Lin, Wu, Li and Jeon teaches the device of claim 16 as set forth in the obviousness rejection. Lin further teaches including an active region at a first surface of the transistor (Fig.6, element #102, paragraph [0072], rows 2-4 is on top surface of transistor, element #100), wherein the gate terminal is aligned with at least a portion of the active region (Fig.11, the horizontal side of the terminal, element #400, is parallel to the horizontal bar of element #250 which is parallel to the top and bottom side of the active region, element #102 as shown in Fig.6).
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Lin in view of Wu, Li, Jeon and in view of Hyuk-soon Choi et al., (United States Patent Application Publication Number, US 2013/0234207 A1) hereinafter referenced as Choi.
Regarding claim 18, the combination of Lin, Wu, Li and Jeon teaches the device of claim 16 as set forth in the obviousness rejection. Lin teaches a plurality of gate electrodes (each element #180 in Fig.6 corresponds to a gate electrode, element #140, in Fig.2, paragraph [0072], rows 12-14). The combination of Lin, Wu, Li and Jeon does not teach the drain and source terminals extend further into the substrate than the plurality of gate electrodes. Choi teaches the drain terminal (Fig.16, element #50D’’ including the connection part to element #30D, same as element #50D’ in Fig.15 paragraph [0060], rows 8-10) and source terminal (Fig.16, element #50S including the connection part to element #30S, paragraph [0043], rows 21-24) extend further into the substrate (Fig.16, elements #26’, #24’ and #22’ paragraph [0043], rows 1-2) than the gate electrodes (Fig.16, element #30G, paragraph [0043], row 3). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Choi and disclose the drain and source terminals extend further into the substrate than the plurality of gate electrodes. Burring the source and drain terminals further into the substrate than the gate electrodes, reduces the electric field strength in the gate dielectric and increases current drivability inside the channel.
Allowable Subject Matter
Claims 1 and 9 are allowed. Claims 2, 5-8 are allowed as being dependent on claim 1. Claims 10-11 and 15 are allowed as being dependent on claim 9. Claim 14 is allowed as being dependent on claim 9, only if amended to overcome the objection.
The following is a statement of reasons for the indication of allowable subject matter.
Regarding claim 1, the cited prior art does not teach or fairly suggests, along with other
claimed features: “the respective set of conductive vias including multiple conductive vias that are horizontally aligned with each other along the respective gate electrode and that are each directly contacting the gate terminal and the respective field plate”.
Regarding claim 9, the cited prior art does not teach or fairly suggests, along with other
claimed features: “the respective set of conductive vias including multiple conductive vias that are horizontally aligned with each other along the respective gate electrode and that are each directly contacting the gate terminal and the respective field plate”.
Response to Arguments
Applicant’s arguments filed on 01/23/2026 have been fully considered but they
are not persuasive. Applicant’s arguments with respect to claim 16 have been considered but they relate to the vias directly contacting the field plate, which is new matter. Therefore, in light of the interpretation given to claim 16, the arguments are moot.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/CRISTIAN A TIVARUS/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899