DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 4, and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Nakajima et al. (“Nakajima ‘979” US 2003/0213979) and Nakajima et al. (“Nakajima ‘374” US 2002/0190374).
Regarding claim 1, Nakajima ‘979 discloses a semiconductor device (Figure 4) comprising:
a substrate (metal block 15);
a semiconductor chip (1) provided on the substrate (15, see Figure 4);
a nut (12);
a case (casing 14) surrounding the semiconductor chip (1, see Figure 4);
a lead frame (6/13) provided on the semiconductor chip (1) and the nut (12) and screwed to the nut (12, para. [0070] discloses using bolts and the nut to fix the lead frame to external wirings, thus the lead frame is screwed to the nut via the bolt, which is not shown), the lead frame (6/13) having a portion contacting an outer surface of the case (portions 6b/13b, see Figure 4), and the portion of the lead frame (6b/13b) and the nut (12) being in direct physical contact with each other (see Figure 4 which shows direct physical contact between the portion of the lead frame 6b/13b and the nuts 12);
a nut box (portion of the case 14 that accommodates the nut 12, see Figure 4) provided in the case (14) and accommodating the nut (12, see Figure 4), and having an opening (14f) formed in a bottom portion of the nut box which exposes the nut downward (see Figure 4, where the opening 14f in the bottom portion of the nut box, which exposes the bottom surface of the nut);
and solder (not shown, but disclosed in para. [0041], [0042]) provided at least between the semiconductor chip (1) and the substrate (15) or the lead frame (6/13, para. [0041], [0042] discloses the use of solder between the semiconductor chip 1 and the lead frame 6, as well as solder between the wire 9 and each of the lead frame 13 and semiconductor chip 1, and the wire 9 is between the lead frame portion 13 and the semiconductor chip 1, thus this solder material is between the lead frame portion 13 and the semiconductor chip 1, these solder materials are in reference to the first embodiment of Figure 1, however para. [0069] discloses that the second embodiment of Figure 4 is a modification of the first embodiment regarding the disposition of the external electrodes and the shape of the casing, thus all other features would remain the same, and the solder materials would also be between the lead frame 6/13 and the semiconductor chip 1 in Figure 4).
Nakajima ‘979 does not disclose the case defining the opening as a stepped opening including a large cross-sectional portion and a small cross-sectional portion closer to the nut that is smaller than an outer diameter of the nut.
Nakajima ‘374 discloses in Figures 15 and 16, however, a case defining the opening (OS) as a stepped opening (see Figures 15 and 16) including a large cross-sectional portion (lower portion having a wider width in the horizontal direction) and a small cross-sectional portion (upper portion, closer to the nut 31 having a smaller width) closer to the nut (31) that is smaller than an outer diameter of the nut (31, see Figures 15 and 16, the outer diameter of the upper portion of the case opening OS is smaller than that of the nut 31, see also para. [0176]).
It would have been obvious to a person having ordinary skill in the art to incorporate the teachings of Nakajima ’374 into the teachings of Nakajima ‘979 to include the stepped configuration of the case opening for the purpose of burying the nuts in the mold resin, securely fixing the nuts in place (Nakajima ‘374, para. [0178], [0183]).
Regarding claim 4, Nakajima ‘979 discloses wherein the lead frame (6/13) includes a main body section (6) provided directly above the semiconductor chip (1, see Figure 4) and an external connection terminal section (13) bonded to the main body section (6) with solder (since the lead frame portion 13 is soldered to the wire 9, the wire 9 is soldered to the semiconductor chip 1, and the semiconductor chip 1 is soldered to the lead frame portion 6, see para. [0041], [0042], the lead frame portion 13 is thus bonded to the lead frame portion 6 through solder material) and provided directly above the nut (12, see Figure 4).
Regarding claim 15, Nakajima ‘979 discloses a semiconductor device (Figure 4) comprising:
a substrate (metal block 15);
a semiconductor chip (1) provided on the substrate (15, see Figure 4);
a nut (12);
a case (casing 14) surrounding the semiconductor chip (1, see Figure 4);
a lead frame (6/13) provided on the semiconductor chip (1) and the nut (12) and screwed to the nut (12, para. [0070] discloses using bolts and the nut to fix the lead frame to external wirings, thus the lead frame is screwed to the nut via the bolt, which is not shown), the lead frame (6/13) having a portion contacting an outer surface of the case (portions 6b/13b, see Figure 4), and the portion of the lead frame (6b/13b) and the nut (12) being in direct physical contact with each other (see Figure 4 which shows direct physical contact between the portion of the lead frame 6b/13b and the nuts 12);
a nut box (portion of the case 14 that accommodates the nut 12, see Figure 4) provided in the case (14) and accommodating the nut (12, see Figure 4), and having an opening (14f) formed in a bottom portion of the nut box which exposes the nut downward (see Figure 4, where the opening 14f in the bottom portion of the nut box, which exposes the bottom surface of the nut); and
solder provided at least between the semiconductor chip and the substrate or the lead frame.
Nakajima ‘979 does not disclose the case defining the opening as a stepped opening including a large cross-sectional portion and a small cross-sectional portion closer to the nut, and a surface of a portion of the case defining the small cross-sectional portion contacts the nut and supports the nut in an upward direction which is opposite to a downward direction in which the nut is exposed.
Nakajima ‘374 discloses in Figures 15 and 16, however, a case defining the opening (OS) as a stepped opening (see Figures 15 and 16) including a large cross-sectional portion (lower portion with greater width in the horizontal direction of Figures 15 and 16) and a small cross-sectional portion (upper portion with smaller width in the horizontal direction) closer to the nut (31, see Figure 16), and a surface of a portion of the case defining the small cross-sectional portion (see Figure 15) contacts the nut (31, see upper surface of the smaller cross-sectional portion directly contacting the nut 31) and supports the nut (31) in an upward direction which is opposite to a downward direction in which the nut (31) is exposed.
It would have been obvious to a person having ordinary skill in the art to incorporate the teachings of Nakajima ’374 into the teachings of Nakajima ‘979 to include the small and large cross-sectional portion configuration of the case opening for the purpose of burying the nuts in the mold resin, securely fixing the nuts in place (Nakajima ‘374, para. [0178], [0183]).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Nakajima ‘979 and Nakajima ‘374 as applied to claim 1 above, and further in view of Adachi et al. (“Adachi” US 2022/0122902).
Regarding claim 5, Nakajima ‘979 does not explicitly disclose a fin.
Adachi discloses in Figure 2, however, a semiconductor device having a fin (fins 32) provided below the substrate (6, see Figure 2).
It would have been obvious to one having ordinary skill in the art to incorporate the teachings od Adachi into the teachings of Nakajima ‘979 and Nakajima ‘374 to include the fins below the substrate for the purpose of increasing the surface area of heat dissipation means, thereby improving heat dissipation performance (Adachi, para. [0074]).
Claims 6-7 are rejected under 35 U.S.C. 103 as being unpatentable over Nakajima ‘979 and Nakajima ‘374 as applied to claim 1 above, and further in view of Kim et al. (“Kim” US 2022/0157959).
Regarding claim 6, Nakajima ‘979 does not explicitly disclose the specific materials used for the semiconductor chip (1).
Kim discloses in Figure 2A, however, a semiconductor chip where the semiconductor chip (Figure 2A) is made with a wide bandgap semiconductor (para. [0005] discloses silicon carbide as a wide bandgap semiconductor used).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the present invention to incorporate the teachings of Kim into the teachings of Nakajima ‘979 and Nakajima ‘374 to include a wide bandgap semiconductor material for the semiconductor chip for the purpose of employing advantageous characteristics of a wide band gap semiconductor such as high electric field breakdown strength and high thermal conductivity (Kim, para. [0005]).
Regarding claim 7, Kim discloses wherein the wide bandgap semiconductor is silicon carbide, a gallium nitride-based material, or diamond (para. [0005], silicon carbide).
Claim 16 ius rejected under 35 U.S.C. 103 as being unpatentable over Nakajima et al. (“Nakajima ‘979” US 2003/0213979), and Adachi et al. (“Adachi” US 2022/0122902).
Regarding claim 16, Nakajima ‘979 discloses a semiconductor device (Figure 4) comprising:
a substrate (metal block 15);
a semiconductor chip (1) provided on the substrate (15, see Figure 4);
a nut (12);
a case (casing 14) surrounding the semiconductor chip (1, see Figure 4);
a lead frame (6/13) provided on the semiconductor chip (1) and the nut (12) and screwed to the nut (12, para. [0070] discloses using bolts and the nut to fix the lead frame to external wirings, thus the lead frame is screwed to the nut via the bolt, which is not shown), the lead frame (6/13) having a portion contacting an outer surface of the case (portions 6b/13b, see Figure 4), and the portion of the lead frame (6b/13b) and the nut (12) being in direct physical contact with each other (see Figure 4 which shows direct physical contact between the portion of the lead frame 6b/13b and the nuts 12);
a nut box (portion of the case 14 that accommodates the nut 12, see Figure 4) provided in the case (14) and accommodating the nut (12, see Figure 4), and having an opening (14f) formed in a bottom portion of the nut box which exposes the nut downward (see Figure 4, where the opening 14f in the bottom portion of the nut box, which exposes the bottom surface of the nut); and
solder (not shown, but disclosed in para. [0041], [0042]) provided at least between the semiconductor chip (1) and the substrate (15) or the lead frame (6/13, para. [0041], [0042] discloses the use of solder between the semiconductor chip 1 and the lead frame 6, as well as solder between the wire 9 and each of the lead frame 13 and semiconductor chip 1, and the wire 9 is between the lead frame portion 13 and the semiconductor chip 1, thus this solder material is between the lead frame portion 13 and the semiconductor chip 1, these solder materials are in reference to the first embodiment of Figure 1, however para. [0069] discloses that the second embodiment of Figure 4 is a modification of the first embodiment regarding the disposition of the external electrodes and the shape of the casing, thus all other features would remain the same, and the solder materials would also be between the lead frame 6/13 and the semiconductor chip 1 in Figure 4).
Nakajima ‘979 does not disclose wherein the lead frame includes a main body section provided directly above the semiconductor chip and an external connection terminal section bonded to the main body section with solder and provided directly above the nut, and the main body section and the external connection terminal section have a region overlapping each other in a plan view, and are bonded to each other with the solder at the region.
Adachi discloses in Figure 2, however, wherein the lead frame (8/13/16) includes a main body section (8/16) provided directly above the semiconductor chip (7) and an external connection terminal section (13) bonded to the main body section (8/16) with solder (S4) and provided directly above the nut (14, see Figure 2), and the main body section (8/16) and the external connection terminal section (13) have a region overlapping each other in a plan view (portion 16 of the main body section and 13 overlap in plan view, see Figure 2), and are bonded to each other with the solder (S4) at the region (see Figure 2).
It would have been obvious to a person having ordinary skill in the art to incorporate the teachings of Adachi into the teachings of Nakajima ‘979 to include the lead frame configuration as claimed. One having ordinary skill in the art would have recognized that the lead from of Nakajima ‘979 and the lead frame of Adachi are known equivalents for providing electrical connection between the semiconductor chip and external connections. Thus, it would have been obvious to substitute one known element for another known element resulting in the predictable result of forming electrical connection means. See KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007), Rationale B.
Response to Arguments
Applicant’s arguments with respect to claims 1 , 15, and 16 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Genevieve G Bullard-Connor whose telephone number is (571)270-0609. The examiner can normally be reached Mon-Fri, 9am-5pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dale Page can be reached at 571-270-7877. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Genevieve G Bullard-Connor/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
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