DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Acknowledgement of Amendments
Claims submitted 06 November 2025 are acknowledged.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-4, 6-9, and 12-17 is/are rejected under 35 U.S.C. 102(a)(1) as being obvious over US 20070138624 (Sudo et al) in light of US 20190157194 (Iyama).
As to Claim 1, Sudo teaches a semiconductor device (Sudo Fig 4) comprising:
a first conductive plate (first plate comprising pattern 34 on conducting base plate 20 as seen in Fig 3) having a first obverse face facing in a thickness direction (Fig 4, top face of 34 faces along z-axis);
a second conductive plate (second plate comprising pattern 36 on conducting base plate 20 as seen in Fig 3) that has a second obverse face facing in a same direction (Fig 4, top face of 36 faces along z-axis), in the thickness direction, as the first obverse face, and is located apart from the first conductive plate in a first direction perpendicular to the thickness direction (34 and 36 separated along x-axis);
a plurality of semiconductor elements (semiconductor elements 26/28) that are joined to the first obverse face (26/28 both joined to top face of 34) and include respective electrodes that face in the same direction, in the thickness direction, as the first obverse face (25/29 electrodes of 26/28, respectively ¶0041); and
a conductive member (conductive lead member 42) that is electrically joined to the electrodes of the plurality of semiconductor elements and the second obverse face (42 connects to 25, 29, and top face of 36),
wherein the conductive member includes a main body portion which extends along a second direction perpendicular to the thickness direction and to the first direction (main body portion being the top portions of 42 which are flat in the xy-plane and extending along the y-axis), a plurality of first junction portions that are individually and electrically joined to the electrodes of the plurality of semiconductor elements (first junction portions being parts of 42 contacting 25/29 and being flat in the xy-plane), a second junction portion that is electrically joined to the second obverse face (second junction portion being part of 42 contacting top of 36 and being flat in the xy-plane), a first connection portion that connects the main body portion and the plurality of first junction portions (portion between main body portion and first junction portion being flat in the yz-plane), and a second connection portion that connects the main body portion and the second junction portion (portion between main body portion and second junction portion being flat in the yz-plane).
Sudo further teaches wherein the first connection portion includes a plurality of connection areas (Sudo Fig 4, connection portions split into areas over elements 26/28), and the plurality of connection areas are individually connected to the plurality of first junction portions (plural connection areas each connect to a corresponding first junction portion above semiconductor elements 26/28).
However, Sudo explicitly teaches the plural connection areas are located apart from each other in the first direction (Sudo Fig 4, x-axis since this is the axis along which the semiconductor elements are spaced).
Iyama teaches a device similar to that of Sudo, and explicitly teaches a plurality of semiconductor elements arranged along a second direction (Fig 7 chips 186, which are arranged along the y-axis when combined with the view in Fig 6) and by consequence that these plural connection areas are located apart from each other in the second direction (semiconductor elements being along second direction makes the connection areas also located apart from each other along second direction).
It would have been obvious to one of ordinary skill in the art at the time of filing to combine the semiconductor devices and conducting member taught by Sudo with the semiconductor elements and main body of conducting member extending along the second axis taught by Iyama. The claim would have been obvious because the substitution of one known element for another would have yielded predictable results to one of ordinary skill in the art. In this case, the substitution of the main body of the conducting member extending along a first direction with the main body of a conducting member extending along a second direction would not have changed the functioning of the device, and as such the substitution would have been predictable to one of ordinary skill in the art.
As to Claim 2, the combination of Sudo and Iyama teaches the semiconductor device according to claim 1. Sudo further teaches wherein the plurality of first junction portions each include an overlapping area that overlaps with the electrode of one of the plurality of semiconductor elements, as viewed along the thickness direction (first junction portions each overlap with 25/29 when viewed along z-axis), and
the areas of the overlapping areas are each 70% or more of each of the areas of the electrodes of the plurality of semiconductor elements, as viewed along the thickness direction (first junction portions reasonably interpreted to cover more than 70% of each of 25/29 in the view shown in Fig 4).
As to Claim 3, the combination of Sudo and Iyama teaches the semiconductor device according to claim 2. Sudo further teaches wherein at least a portion of the main body portion overlaps with the first obverse face, as viewed along the thickness direction (some of main body portion of 42 overlaps with top face of 34).
As to Claim 4, the combination of Sudo and Iyama teaches the semiconductor device according to claim 2. Iyama, as applied to claim 1, then teaches that these plural connection areas are located apart from each other in the second direction (semiconductor elements being along second direction makes the connection areas also located apart from each other along second direction).
As to Claim 6, the combination of Sudo and Iyama teaches semiconductor device according to claim 1. Sudo further teaches wherein the plurality of connection areas are each inclined, as viewed along the second direction (i.e., along the y-axis in Sudo), away from the first obverse face while extending from the corresponding one of the plurality of first junction portions toward the main body portion (connection areas between first junctions and main body portion inclined vertically up).
As to Claim 7, the combination of Sudo and Iyama teaches the semiconductor device according to claim 6. Sudo only explicitly teaches the connection areas being inclined at a 90 degree angle to the first obverse face.
Iyama teaches connection areas (Iyama Fig 11, connection areas 30) forming an acute angle between the first junction portions (14). Though the angle between 30 and 14 is not explicitly disclosed as being between 30 and 60 degrees, examiner is reasonably interpreting the disclosure of Iyama to teach such a range (Iyama discloses the angle between 14 and 30 to be “not perpendicular” ¶0089. i.e., the angle may be between 0 and 90 degrees, which includes the range of 30 to 60 degrees as claimed.)
It would have been obvious to one of ordinary skill in the art at the time of filing to combine the connection member having angled connection areas taught by Sudo and Iyama with the angling of the connection areas with respect to the first junction portions taught by Iyama in order to improve the heat dissipation properties of the conducting member (Iyama ¶0089).
As to Claim 8, the combination of Sudo and Iyama teaches the semiconductor device according to claim 2. Sudo further teaches the device further comprising a plurality of first junction layers that have conductivity, and individually and electrically join the plurality of first junction portions and the electrodes of the plurality of semiconductor elements (Sudo discloses solder connecting first junction portions to electrodes 25/29 ¶0042),
wherein the plurality of first junction layers each include a portion that extends outward from the overlapping area of corresponding one of the plurality of first junction portions, viewed along the thickness direction (solder layer reasonably interpreted to extend outward from the first junction portions as seen along the z-axis).
As to Claim 9, the combination of Sudo and Iyama teaches the semiconductor device according to claim 8. Sudo further teaches wherein the plurality of first junction layers each contain tin (solder may include tin ¶0042).
As to Claim 12, the combination of Sudo and Iyama teaches the semiconductor device according to claim 8. Sudo further teaches the device further comprising a second junction layer that has conductivity and electrically joins the second junction portion and the second obverse face (same solder joins 42 to 36 ¶0042),
wherein the second junction layer is made of a same material as the plurality of first junction layers (first and second junction layers are the same solder material ¶0041+0042).
As to Claim 13, the combination of Sudo and Iyama teaches the semiconductor device according to claim 1. Sudo further teaches wherein the first conductive plate, the second conductive plate, and the conductive member each contain copper (plate 20 in each of first and second conductive plate may contain copper ¶0050. 42 may contain copper ¶0052).
As to Claim 14, the combination of Sudo and Iyama teaches the semiconductor device according to claim 1. Sudo further teaches wherein a thickness of the first conductive plate and a thickness of the second conductive plate are each respectively larger than a maximum thickness of the conductive member (radiating plate 20 comprising first and second conductive plates may be 2 mm thick ¶0044; 42 may have a maximum thickness of 300 µm ¶0044).
As to Claim 15, the combination of Sudo and Iyama teaches the semiconductor device according to claim 1. Sudo further teaches wherein the second connection portion (Sudo Fig 4, second connecting portion connecting second junction portion on 36 to main body portion of 42 above) is inclined, as viewed along an in-plane direction of the second obverse face (e.g., viewed along the y-axis), away from the second obverse face while extending from the second junction portion toward the main body portion (second connection portion inclined vertically upwards).
As to Claim 16, the combination of Sudo and Iyama teaches the semiconductor device according to claim 1. Sudo further teaches wherein the first connection portion and the second connection portion are spaced apart from each other in the first direction with the main body portion intervening therebetween (portions spaced along x-axis with main body portion of 42 between).
As to Claim 17, the combination of Sudo and Iyama teaches the semiconductor device according to claim 1. Though neither of the currently cited embodiments of Sudo or Iyama explicitly teach wherein each of the connection areas of the first connection portion are smaller in size in the second direction than the second connection portion, the embodiment in Sudo presented in FIG 20 shows first connection portions (curved sides of 72) being smaller in size along the y-axis than the second connection portion (portion of 68 above 36 lying in the yz-plane). In other words, such changes in dimension were known to those having ordinary skill in the art at the time of filing. All of the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, and the combination would have yielded predictable results to one of ordinary skill in the art at the time of applicant’s filing.
Claim(s) 10-11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sudo and Iyama as applied to claim 9 above, and further in view of US 20150091164 (Yamagami et al).
As to Claim 10, the combination of Sudo and Iyama teaches the semiconductor device according to claim 9, but does not explicitly teach wherein a thickness of each of the plurality of first junction portions is twice or less of a maximum thickness of the corresponding one of the plurality of first junction layers that is in contact therewith. Sudo is silent as to the relative thicknesses between the solder and the first junction portions.
Yamagami teaches a device similar to that of Sudo and Iyama, and explicitly teaches a first junction portion (Yamagami Fig 3A, clip 9) having a thickness approximately equal to a first junction layer (solder 21; 9 and 21 have approximately same thickness in view of Fig 3A). In other words, the first junction portion is twice or less than a maximum thickness of the corresponding first junction layer that is in contact therewith.
It would have been obvious to one of ordinary skill in the art at the time of filing to combine the semiconductor device having a junction portion and a junction layer joining the junction portion to an electrode taught by Sudo and Iyama with the thickness of the junction portion being twice or less than a maximum thickness of the junction layer in contact therewith taught by Yamagami in order to more uniformly distribute thermal stress across the entire junction, improving resilience of the device.
As to Claim 11, the combination of Sudo, Iyama, and Yamagami teaches the semiconductor device according to claim 10. Yamagami, as applied to claim 10, further teaches wherein the maximum thickness is 100 µm or more (Yamagami, clip 9 may have thickness between 50 µm and 400 µm ¶0092).
Response to Arguments
Applicant's arguments filed 06 November 2025 have been fully considered but they are not persuasive.
Applicant argues that Sudo fails to explicitly teach a main body portion, first/second connection portions, and first/second junction portions since all these components are integrally part of the conductive member 42 in Sudo. However, it is reasonably interpreted that the areas may still reasonably be considered portions. Further, nowhere in applicant’s claims is it made necessary that the main body portion, first/second connection portions, and first/second junction portions have been separated before construction.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/Corbyn D Mellinger/ Examiner, Art Unit 2899
/ZANDRA V SMITH/Supervisory Patent Examiner, Art Unit 2899
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