DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on April 15, 2026 has been entered.
Response to Arguments
Applicant’s arguments, see Remarks, filed on April 15, 2026, with respect to claims 14 and 15 have been fully considered and are persuasive. The 35 USC § 112 (b) rejection of claims 14 and 15 have been withdrawn.
Applicant's arguments filed on April 15, 2026 have been fully considered but they are not persuasive. Upon further considerations, the examiner finds that Sato teaches the amended limitations of the first joining layer contains silver (Sato ¶ [0128]: solder 11d can contain Pb—Sn—Ag based solder ) and the second joining layer contains tin (¶ [0137]: solder 11b can contain Pb—Sn based solder). Sato also teaches the first joining layer to also contain tin (see ¶ [0128] reference above). The ordinary skilled artisan would find it obvious to combine Saito with Sato since Saito teaches increasing the melting point of the first joining layer by decreasing the amount of tin in the said joining layer (Saito ¶ [0055] ). Please see the 35 USC § 103 rejections below of independent claims 1 and 14.
In summary, this application is not placed in a condition for an allowance.
Specification
The specification is objected to as failing to provide proper antecedent basis for the claimed subject matter. See 37 CFR 1.75(d)(1) and MPEP § 608.01(o). Correction of the following is required: new claim 21 requires an overlapping region of the first joining layer that overlaps with the semiconductor element and a non-overlapping region. There are no references to said overlapping and non-overlapping regions in the specification.
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they do not include the following reference sign(s) mentioned in the description: the overlapping region and non-overlapping region as described in the objections to specifications above are not labelled in the Figures. For the purpose of compact prosecution, the examiner has labelled these said elements by annotating Figs. 3 and 7 of the instant application. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
PNG
media_image1.png
713
785
media_image1.png
Greyscale
PNG
media_image2.png
444
713
media_image2.png
Greyscale
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-2, 7, 9, and 12-15 are rejected under 35 U.S.C. 103 as being unpatentable over Sato (US 2010/0123240 A1) and further in view of Saito (US 2018/0012826 A1) and Onoda (US 2018/0012847 A1).
Regarding claim 1, Sato teaches a semiconductor device (Fig 3: 1) comprising:
a die pad (2, see ¶ [0054]) that includes an obverse surface (top surface of 2; plain meaning of obverse: rear or covered surface) facing in a thickness direction (vertical direction);
a semiconductor element (3) that includes a first electrode (3d) opposing the obverse surface (plain meaning: facing the obverse surface), and a second electrode (3s) opposite to the first electrode in the thickness direction (Fig. 3 shows 3s is opposite to 3d along the vertical direction), the first electrode being electrically joined to the obverse surface (3d joined to top surface of 2 using 11a);
a first joining layer (11a) that electrically joins the first electrode and the obverse surface to each other;
a first conductive member (6) electrically joined (using 11b) to the second electrode; and
a second joining layer (11b) that electrically joins the first conductive member and the second electrode to each other,
the first joining layer and the second joining layer sandwich the semiconductor element in the thickness direction (Fig. 3 shows 11a and 11b sandwich 3 along the vertical direction), and
the first joining layer contains silver (¶ [0128]: solder 11d can contain Pb—Sn—Ag--Cu based solder; note: solder 11d later becomes 11a, see ¶ [0133]: “solder 11d is melted (melted again) and solidified (solidified again)… to become… solder 11a” ) , and the second joining layer contains tin (¶ [0137]: solder 11b can contain Pb—Sn based solder).
Sato further teaches both first joining layer and second joining layer to contain tin (see ¶ [0128] and ¶ [0133]). However, Sato does not a semiconductor device wherein a melting point of the first joining layer is higher than a melting point of the second joining layer.
Saito, in the same field of invention, teaches a semiconductor device (Figs 1-5, ¶ [0030]: A1) wherein a melting point (¶ [0055]: first melting point of 320 C) of a first joining layer (Fig. 2, ¶ [0055]: 31) is higher (see ¶ [0055]) than a melting point (¶ [0055]: second melting point: 290 C) of a second joining layer (Fig. 2, [0055]: 32).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Saito into the device of Sato to provide a melting point of a first joining layer to be higher than a melting point of a second joining layer. The ordinary artisan would have been motivated to modify Sato in the manner set forth above for at least the purpose of preventing or suppressing a re-melting of the first joining layer when the second joining layer is applied (Saito ¶ [0070]), since a preferred method of manufacturing the semiconductor device requires a first bonding step (Saito Fig 6: S21) wherein the first joining layer is used to join corresponding semiconductor device elements (Saito [0069]; this is analogous to Sato’s step S2 in Figs. 13 & 17 wherein semiconductor device 3 is joined to die pad 2 using 11d/11a; see also Sato ¶ [0126]-[0127] ) and a second bonding step (Saito Fig. 6: S22) wherein the second joining layer is used to join corresponding elements of the semiconductor device (Saito ¶ [0070], this is analogous to Sato’s step S3 in Figs. 13 & 19 wherein conductive member 6 is joined to semiconductor die 3 using 11e/11b; see also Sato ¶ [0129]-[0130]) and for the further purpose of preventing cracks in the solder (Saito ¶ [0189]). The ordinary skilled artisan would also find it obvious to combine Saito with Sato since Saito teaches increasing the melting point of the first joining layer by decreasing the amount of tin in the said joining layer (Saito ¶ [0055] ), with the skilled artisan noting that Sato also teaches the first joining layer having tin (Sato ¶ [0128]).
However, Sato in view of Saito does not teach: wherein a thickness of the first joining layer is greater than a thickness of the second joining layer.
Onoda, in the same field of invention, teaches a semiconductor device (Fig. 7) wherein a thickness of a first joining layer (25) is greater (¶ [0092]) than a thickness of a second joining layer (24).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Onoda into the device of Sato in view of Saito to set a thickness of a first joining layer to be greater than a thickness of a second joining layer. The ordinary artisan would have been motivated to modify Sato in view of Saito in the manner set forth above for at least the purpose of strengthening the reliability of the connection of the solder by thickening, i.e., adding more solder material, specific solder locations that the ordinary skilled artisan deems is critical due to previously observed and/or perceived failure points (Onoda ¶ [0092]).
Regarding claim 2, the semiconductor device according to claim 1, wherein the die pad (Sato ¶ [0059]) and the first conductive member (Sato ¶ [0082]) each contain copper.
Regarding claim 7, the semiconductor device according to claim 2, further comprising:
a first lead (Sato Fig. 3, ¶ [0054]: 4) that includes a first joining surface (top surface of 4) that faces a same side (top side) as the obverse surface in the thickness direction (Fig. 3 shows top surface of 4 is on the top side; the obverse surface is also on the top side of 2; both these sides are in the vertical direction) and is spaced apart from the die pad (Fig. 3 shows 4 is spaced apart from 2); and
a third joining layer (¶ [0075]: 11c) that electrically joins the first conductive member and the first joining surface to each other (Fig. 3 shows 11c joining 6 and top of 4),
wherein the first lead contains copper (¶ [0076]), and
the third joining layer is made of a same material as the second joining layer (¶ [0137]: 11c and 11b are made of solder paste having the same melting point of 320C).
Regarding claim 9, the semiconductor device according to claim 7, wherein a thickness of the die pad is greater than a maximum thickness of the first lead (using BRI, Fig. 3 shows die pad 2 is thicker than the thickest portion of first lead 4, which is the horizontal portion of 4 under 11c).
Regarding claim 12, the semiconductor device according to any one of claim 1, further comprising a sealing resin (Sato Fig. 3, ¶ [0053]: 8) that covers the semiconductor element (Fig. 3 shows 8 covering 3), the first conductive member (Fig. 3 shows 8 covering 6), and a portion of the die pad (Fig. 3 shows 8 covering top portions of 2).
Regarding claim 13, the semiconductor device according to claim 12, wherein the die pad has a reverse surface (Sato Fig. 3: bottom surface of 2) opposite to the obverse surface in the thickness direction (Fig. 3 shows bottom surface is opposite the top surface of 2 along the vertical direction), and the reverse surface is exposed from the sealing resin (Fig. 3 shows the bottom surface is not covered by resin 8).
Regarding claim 14, Sato teaches method of manufacturing a semiconductor device (Fig 3: 1) comprising the steps of:
disposing a conductive first joining material (11a) on an obverse surface (top surface of 2; plain meaning of obverse: rear or covered surface) of a die pad (2), the obverse surface facing in a thickness direction (vertical direction);
disposing a semiconductor element (3) on the first joining material so that a first electrode (3d) opposes the first joining material (plain meaning: 3d faces the obverse surface), the semiconductor element having the first electrode and a second electrode (3s) positioned on opposite sides to each other (Fig. 3 shows 3s is opposite to 3d along the vertical direction);
electrically joining the first electrode to the obverse surface by melting (¶ [0014]: heat treatment for melting the first solder; also ¶ [0128]: solder wire is melted) and solidifying (¶ [0128]: solder wire solidifies after melting to form 11d; Fig. 20 and ¶ [0133] shows 11d and 11a are the same) the first joining material, thereby forming a first joining layer (11d) between the first electrode and the obverse surface;
disposing a conductive second joining material (11b) on the second electrode; and
disposing a conductive member (6) on the second joining material and electrically joining the conductive member to the second electrode by melting (¶ [0014]: heat treatment for melting the second solder 11e; also see ¶ [0133]) and solidifying (¶ [0133]: 11e solidifies to become 11b) the second joining material, thereby forming a second joining layer (11b) between the conductive member and the second electrode (see Fig. 20),
the first joining layer and the second joining layer sandwich the semiconductor element in the thickness direction (Figs. 3 & 20 shows 11d and 11b sandwich 3 along the vertical direction), and
the first joining layer contains silver (¶ [0128]: solder 11d can contain Pb—Sn—Ag--Cu based solder; note: solder 11d later becomes 11a, see ¶ [0133]: “solder 11d is melted (melted again) and solidified (solidified again)… to become… solder 11a” ) , and the second joining layer contains tin (¶ [0137]: solder 11b can contain Pb—Sn based solder).
Sato further teaches both first joining layer and second joining layer to contain tin (see ¶ [0128] and ¶ [0133]). However, Sato does not the method wherein the melting point of the first joining material is higher than a melting point of the second joining material.
Saito, in the same field of invention, teaches a method of manufacturing a semiconductor device (Figs 1-5, ¶ [0030]: A1) wherein a melting point (¶ [0055]: first melting point of 300 C to 340 C) of the first joining material (Fig. 2, ¶ [0055]: 31) is higher (see ¶ [0055]) than a melting point (¶ [0055]: second melting point: 280 C to 320 C) of a second joining material (Fig. 2, [0055]: 32).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Saito into the method of Sato to provide a melting point of a conductive first joining material to be higher than a melting point of a second conductive joining material. The ordinary artisan would have been motivated to modify Sato in the manner set forth above for at least the purpose of preventing or suppressing a re-melting of the first joining layer when the second joining layer is applied (Saito ¶ [0070]) since a preferred method of manufacturing the semiconductor device requires a first bonding step (Saito Fig 6: S21) wherein the first joining layer is used to join corresponding semiconductor device elements (Saito ¶ [0069]; this is analogous to Sato’s step S2 in Figs. 13 & 17 wherein semiconductor device 3 is joined to die pad 2 using 11d/11a; see also Sato ¶ [0126]-[0127] ) and a second bonding step (Saito Fig. 6: S22) wherein the second joining layer is used to join corresponding elements of the semiconductor device (Saito ¶ [0070], this is analogous to Sato’s step S3 in Figs. 13 & 19 wherein conductive member 6 is joined to semiconductor die 3 using 11e/11b; see also Sato ¶ [0129]-[0130]) and for the further purpose of preventing cracks in the solder (Saito [0189]). The ordinary skilled artisan would also find it obvious to combine Saito with Sato since Saito teaches increasing the melting point of the first joining layer by decreasing the amount of tin in the said joining layer (Saito ¶ [0055] ), with the skilled artisan noting that Sato also teaches the first joining layer having tin (Sato ¶ [0128]).
However, Sato in view of Saito does not teach: wherein a thickness of the first joining layer is greater than a thickness of the second joining layer.
Onoda, in the same field of invention, teaches a semiconductor device (Fig. 7) wherein a thickness of a first joining layer (25) is greater (¶ [0092]) than a thickness of a second joining layer (24).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Onoda into the method of Sato in view of Saito to set a thickness of a first joining layer to be greater than a thickness of a second joining layer. The ordinary artisan would have been motivated to modify Sato in view of Saito in the manner set forth above for at least the purpose of strengthening the reliability of the connection of the solder by thickening, i.e., adding more solder material, specific solder locations that the ordinary skilled artisan deems is critical due to previously observed and/or perceived failure points (Onoda ¶ [0092]).
Regarding claim 15, the method of manufacturing a semiconductor device according to claim 14, wherein the first joining material is a wire solder (Sato ¶ [0060], ¶ [0128]: wire-like solder).
Claims 6 is rejected under 35 U.S.C. 103 as being unpatentable over Sato (US 2010/0123240 A1) in view of Saito (US 2018/0012826 A1) and Onoda (US 2018/0012847 A1), as applied to claim 2 above, further in view of Rodriguez (US 2018/0190576 A1).
Regarding claim 6, Sato in view of Saito and Onoda teaches the semiconductor device according to claim 2, but does not teach: wherein an area of the semiconductor element is 40% or less of an area of the obverse surface as viewed along the thickness direction.
Rodriguez, in the same field of invention, teaches a semiconductor device (Fig. 11: 600) wherein an area (footprint area of 1104) of the semiconductor element (1104) is 40% or less (see ¶ [0042]: “the footprint area of the die pad… is more than 80% of the footprint area of the semiconductor die 1104”) of an area (footprint area of the top surface of the 602) of the obverse surface (top surface of 602) as viewed along the thickness direction (viewed from the top of 600, which is along the vertical axis).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Rodriguez into the device of Sato in view of Saito and Onoda to set the area of a semiconductor element to be 40% or less of an area of the obverse surface as viewed along the thickness direction. The ordinary artisan would have been motivated to modify Sato in view of Saito and Onoda in the manner set forth above for at least the purpose of using the extended, larger area of the die pad as a recess region (see Rodriguez Fig. 11, ¶ [0038]: 704) to catch an overflow of conductive adhesive, i.e., solder (802). Without this recess, the adhesive would have overflowed and caused unintended contact with other elements (Fig. 4) due to adhesive creep (¶ [0006]-[0008]), thus increasing the die pad area relative to the area of the semiconductor element improves the reliability of the device (Abstract).
Claims 8 is rejected under 35 U.S.C. 103 as being unpatentable over Sato (US 2010/0123240 A1) in view of Saito (US 2018/0012826 A1) and Onoda (US 2018/0012847 A1), as applied to claim 7 above, further in view of Hasegawa (US 2021/0118781 A1).
Regarding claim 8, Sato in view of Saito and Onoda teaches the semiconductor device according to claim 7, but does not teach: wherein, in the thickness direction, the first joining surface is opposite to the obverse surface with respect to the semiconductor element.
Hasegawa, in the same field of invention, teaches a device (Fig. 27) wherein, in the thickness direction (vertical direction), the first joining surface (bottom surface of LD2 where BD5 is attached) is opposite to the obverse surface (bottom surface of DPH) with respect to the semiconductor element (CPH; Fig. 27 shows the bottom surface of LD2 is below CPH, i.e., opposite to the bottom surface of DPH with respect to CPH ).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Hasegawa into the device of Sato in view of Saito and Onoda to have the first joining surface be opposite to the obverse surface with respect to the semiconductor element. The ordinary artisan would have been motivated to modify Sato in view of Saito in the manner set forth above for at least the purpose of attaching a heat sink (HS, see Hasegawa Fig. 27) to the side opposite of the obverse surface and to attach the bottom surface of the first lead to a wiring board (PB1). This improves the heat dissipation of the device package (¶ [0127]-[0129]) while at the same time allowing the device to be connected to terminal electrodes of the circuit board (TM).
Claims 10 and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Sato (US 2010/0123240 A1) in view of Saito (US 2018/0012826 A1) and Onoda (US 2018/0012847 A1), as applied to claim 7 above, further in view of Hayashi (US 2020/0098672 A1).
Regarding claim 10, Sato in view of Saito and Onoda teaches the semiconductor device according to claim 7, further comprising
a second lead (Sato Fig. 3, [0054]: 5) , a second conductive member ( ¶ [0054]: 7; using BRI, wire 7 is a conductive member since it is used to electrically connect lead to the gate electrode 3g),
wherein the semiconductor element includes a third electrode (3g) opposite to the first electrode in the thickness direction (Fig. 3 shows 3g is opposite 3d along the vertical direction) and spaced apart from the second electrode (Fig. 3 shows 3g is spaced apart from 3s),
the second lead has a second joining surface (top surface of 5) that faces a same side (top side) as the obverse surface in the thickness direction (top surface of 5 and the top surface of 2 are both top surfaces along the vertical direction), and is spaced apart from the die pad and the first lead (5 is spaced apart from 2 and 4),
the second conductive member is electrically joined to the third electrode and the second joining surface (7 is electrically joined to 3a and 5; see ¶ [0058]),
the second lead contain copper (¶ [0076]).
However, Sato in view of Saito and Onoda does not teach a semiconductor device further comprising a fourth joining layer, and a fifth joining layer, wherein
the fourth joining layer electrically joins the second conductive member and the third electrode to each other,
the fifth joining layer electrically joins the second conductive member and the second joining surface to each other,
the second conductive member and the second lead contain copper, and
the fourth joining layer and the fifth joining layer are each made of a same material as the second joining layer.
Saito, in another embodiment, further teaches a semiconductor device (Fig. 14) further comprising a fourth joining layer ([¶ 0072]: layer formed by wire bonder connecting wire 41 to first electrode pad 113 using a “first bonding” step), and a fifth joining layer ([¶ 0072]: layer formed by wire bonder connecting wire 41 to terminal 221 using a “second bonding” step), wherein
the fourth joining layer electrically joins the second conductive member and the third electrode to each other (as explained in ¶ [0072], the “first bonding” joins 41 to 113),
the fifth joining layer electrically joins the second conductive member and the second joining surface to each other (as explained in ¶ [0072], the “second bonding” joins 41 and top surface of 221),
the fourth joining layer and the fifth joining layer are each made of a same material as the second joining layer (both first bonding and second bonding uses the same wire bonder, as explained in ¶ [0072]).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of another embodiment of Saito into the device of Sato in view of Saito and Onoda to add a fourth joining layer and a fifth joining layer, wherein the fourth joining layer electrically joins a second conductive member and a third electrode to each other and the fifth joining layer electrically joins the second conductive member and a second joining surface to each other and wherein the fourth joining layer and the fifth joining layer are each made of a same material as the second joining layer. The ordinary artisan would have been motivated to modify Sato in view of Saito and Onoda in the manner set forth above for at least the purpose of using any material known in the art as wire bonders (Saito ¶ [0071]) to electrically and mechanically connect the second conductive member to both the third electrode of the semiconductor element and the second joining surface of the second lead (Saito ¶ [0072]).
Sato in view of Saito and Onoda further teaches the second conductive member contains gold (Sato ¶ [0068]). However, Sato in view of Saito and Onoda does not teach the second conductive member contains copper.
Hayashi, in the same field of invention, teaches a semiconductor device (Fig. 6: 20) wherein a second conductive member (22) contains copper or gold (¶ [0072]).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Hayashi into the device of Sato in view of Saito and Onoda to substitute copper for gold as the material for the second conductive member. The ordinary artisan would have been motivated to modify Sato in view of Saito and Onoda in the manner set forth above for the predictable result of providing electrical connectivity due to the conductive nature of these materials or, alternatively, for the purpose of substituting equivalent materials known in the prior art for the same purpose of providing electrical connection. Furthermore, the skilled artisan may be motivated to reduce cost as copper is more cost-effective than gold.
Regarding claim 18, the semiconductor device according to claim 10, further comprising a sealing resin (8, see Sato Fig. 3), a third lead connected to the die pad (Sato Figs. 4 & 5 shows multiple leads of 4 and 5), wherein the sealing resin covers the semiconductor element (Fig. 4 shows 8 covering 3), the first conductive member (8 covers 6), the second conductive member (8 covers 7), a portion of the die pad (8 covers a portion of 2), a portion of the first lead, a portion of the second lead, and a portion of the third lead (Fig. 4 shows 8 covering portions of each of the multiple leads of 4 and 5 ).
Regarding claim 19, the semiconductor device according to claim 18, wherein the sealing resin includes a side surface (8d1 or 8d2; see Sato Fig. 3) facing a direction (8d1 & 8d2 faces the horizontal direction) perpendicular to the thickness direction (the horizontal direction and the vertical direction are perpendicular to each other), and the first lead, the second lead, and the third lead protrudes from the side surface (as shown in Figs. 3 & 4).
Regarding claim 20, Sato et al teaches the semiconductor device according to claim 19, but does not teach:
wherein the sealing resin is formed with an attachment hole extending through the sealing resin in the thickness direction,
the die pad is formed with a through-hole extending through the die pad in the thickness direction, and
the attachment hole is contained within the through-hole as viewed in the thickness direction.
Saito, teaches a semiconductor device (Fig. 3), wherein a sealing resin (5) is formed with an attachment hole (56) extending through the sealing resin in the thickness direction (¶ [0203]: from resin main surface 51 to back surface 52; see also Fig. 4),
a die pad (211) is formed with a through-hole (211c) extending through the die pad in the thickness direction (see Fig. 2 and ¶ [0175]), and
the attachment hole is contained within the through-hole as viewed in the thickness direction (see Fig. 3).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Saito into the device of Sato et al to provide an attachment hole in the resin and a through-hole in the die pad, wherein the attachment hole is contained within the through-hole when the device is viewed in the thickness direction. The ordinary artisan would have been motivated to modify Sato et al in the manner set forth above for at least the purpose of using the attachment hole of the resin and the die pad through-hole as a means for attaching the semiconductor device to heat spreaders through the use of screws to improve the heat dissipation of the device (Saito ¶ [0203]).
Claims 11 is rejected under 35 U.S.C. 103 as being unpatentable over Sato (US 2010/0123240 A1), Saito (US 2018/0012826 A1), Onoda (US 2018/0012847 A1), and Hayashi (US 2020/0098672 A1), as applied to claim 10 above, further in view of Hasegawa (US 2021/0118781 A1).
Regarding claim 11, Sato in view of Saito and Onoda teaches the semiconductor device according to claim 7, but does not teach: wherein, in the thickness direction, the first joining surface is opposite to the obverse surface with respect to the semiconductor element.
Hasegawa, in the same field of invention, teaches a device (Fig. 27) wherein, in the thickness direction (vertical direction), the first joining surface (bottom surface of LD2 where BD5 is attached) is opposite to the obverse surface (bottom surface of DPH) with respect to the semiconductor element (CPH; Fig. 27 shows the bottom surface of LD2 is below CPH, i.e., opposite to the bottom surface of DPH with respect to CPH ).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Hasegawa into the device of Sato in view of Saito and Onoda to have the first joining surface be opposite to the obverse surface with respect to the semiconductor element. The ordinary artisan would have been motivated to modify Sato in view of Saito in the manner set forth above for at least the purpose of attaching a heat sink (HS, see Hasegawa Fig. 27) to the side opposite of the obverse surface and to attach the bottom surface of the first lead to a wiring board (PB1). This improves the heat dissipation of the device package (¶ [0127]-[0129]) while at the same time allowing the device to be connected to terminal electrodes of the circuit board (TM).
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Sato (US 2010/0123240 A1) and further in view of Saito (US 2018/0012826 A1) and Onoda (US 2018/0012847 A1) as evidenced by Yoshihara (US 2016/0293473 A1).
Regarding claim 16, Sato et al teaches the semiconductor device according to claim 1, wherein the first conductive member is a metal clip (Sato ¶ [0053]: 6 is a metal plate; metal clips and metal plates are analogous, as evidenced by Yoshihara ¶ [0071]).
Claims 17 is rejected under 35 U.S.C. 103 as being unpatentable over Sato (US 2010/0123240 A1) in view of Saito (US 2018/0012826 A1), Onoda (US 2018/0012847 A1), and Hayashi (US 2020/0098672 A1) as applied to claim 10 above, further in view of Calo (US 2021/0233839 A1).
Regarding claim 17, Sato et al teaches the semiconductor device according to claim 10 and further teaches the device wherein the second conductive member is a bond wire (Sato ¶ 0054). However, they do not teach the device wherein the second conductive member is a metal clip.
Calo, in the same field of invention, teaches a device wherein a conductive member can be a bond wire or a metal clip (¶ [0001]).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to substitute the bond wire that comprises the second conductive member of Sato et al with that of a metal clip for the predictable result of providing electrical connection of a semiconductor die terminal (Calo ¶ [0001]).
Claim 21 is rejected under 35 U.S.C. 103 as being unpatentable over Sato (US 2010/0123240 A1) in view of Saito (US 2018/0012826 A1) and Onoda (US 2018/0012847 A1) as applied to claim 1 above and further in view of Kanazawa (US 2010/0289127 A1).
Regarding claim 21, Sato et al. teach the semiconductor device according to claim 1, but do not teach: wherein as viewed in the thickness direction, the first joining layer includes an overlapping region that overlaps with the semiconductor element, and a non-overlapping region located outside the semiconductor element, the non-overlapping region being greater in area than the overlapping region.
Kanazawa, in the same field of invention, teaches a semiconductor device (see Fig. 41) wherein as viewed in the thickness direction (direction from the top view of Fig. 41), the first joining layer (4) includes an overlapping region (region of 4 under 5B) that overlaps with the semiconductor element (5B), and a non-overlapping region (region of 4 not under 5B ) located outside the semiconductor element, the non-overlapping region being greater in area than the overlapping region (see Fig. 41).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Kanazawa into the device of Sato et al. to add an overlapping region and non-overlapping region of the joining layer, wherein the overlapping region overlaps the semiconductor element and the non-overlapping region is located outside the overlapping region, and wherein the non-overlapping region is greater in area than the overlapping region. The ordinary artisan would have been motivated to modify Sato in the manner set forth above for at least the purpose of adding a second semiconductor element (such as diode 5B, see Kanazawa Fig. 5) in order to connect the second semiconductor element with the semiconductor element (5B is a transistor, see ¶ [0070]-[0072], which is analogous to Sato’s transistor 3) to design a switch circuit (see Fig. 1 and ¶ [0065] ) used as an inverter in an H-bridge motor (¶ [0007] ), with the further purpose of reducing the size of the device (¶ [0004] ), improving device reliability (¶ [0009], [0011], Abstract ) and decreasing the manufacturing cost (¶ [0004] ).
Furthermore, the recitation of the non-overlapping region having an area greater than the overlapping region is a recitation of relative dimensions. A person of ordinary skill would be motivated to optimize the area of the non-overlapping region with respect to the overlapping region depending on the size and configuration of the second semiconductor element (see Kanazawa ¶ [0125] ). Also, n Gardner v. TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984), the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device. Please see MPEP § 2144.04 (IV)(A).
Conclusion
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DOUGLAS YAP whose telephone number is (703)756-1946. The examiner can normally be reached Monday - Friday 8:00 AM - 5:00 PM ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Zandra Smith can be reached at (571) 272-2429. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/DOUGLAS YAP/Assistant Examiner, Art Unit 2899 /ZANDRA V SMITH/Supervisory Patent Examiner, Art Unit 2899
Prosecution Insights