Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
2. This action is responsive to the application No. 18/005,010 filed on September 17, 2025.
Priority
3. Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Specification
4. The title of the invention has been amended as “Semiconductor Device With Conduction Portion and Method For Manufacturing The Same”.
Claim Objections
5. The objections on claims 1, 10 have been withdrawn per the Applicant’s response dated on 09/17/2025.
Claim Objections
6. Claims 1, 3, 5-6, 11-13 are further objected to because of the following informalities: the claims should be recited as follows to avoid indefiniteness due to lack of antecedent basis and/or proper alignment of the claim limitations:
1. (Currently Amended) A semiconductor device. comprising:
an electrode pad formed at a specific depth from a surface of a substrate; and
a conductive portion in a region from the electrode pad to the surface of the substrate, wherein
the conductive portion is in a state in which the conductive portion is electrically connected to a wiring on the surface of the substrate the conductive portion includes a probe region to contact a probe.
3. (Currently Amended) The semiconductor device according to claim 1, wherein the conductive portion includes a wiring region for an electrical connection with the wiring. at a first position that is directly above the electrode pad on the surface of the substrate.
5. (Currently Amended) The semiconductor device according to claim 3, wherein the probe region is at a second position first position.
6. (Currently Amended) The semiconductor device according to claim 1, wherein the conductive portion includes a wiring region for an electrical connection with the wiring at a second position
11. (Currently Amended) A method for manufacturing a semiconductor device, the method comprising:
forming an electrode pad at a specific from a surface of a substrate;
applying a conductive paste in a region from the electrode pad to the surface of the substrate; and
curing the
the conductive paste and
12. (Currently Amended) The method for manufacturing the semiconductor device according to claim 11, wherein
13. (Currently Amended) The method for manufacturing the semiconductor device according to claim 11, wherein
producing a mask having openings at a plurality of positions directly above the electrode pad; and
applying the conductive paste over the mask.
Appropriate corrections are needed.
Claim Rejections - 35 USC § 102
7. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
8. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless–
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
9. Claims 1, 3-9 are rejected under 35 U.S.C. 35 U.S.C. 102 (a)(1)/102 (a)(2) as being anticipated by Yong et al. (US 2003/0173667 A1).
Regarding independent claim 1, Yong et al. teaches a semiconductor device (34, para [0016]) comprising (Fig. 3, para [0016]):
an electrode pad (30 metal layers, para [0017]) at a specific depth (see the annotated figure below) from a surface of a substrate (24/26); and
a conductive portion (16 metal layer pad, para [0016]) in a region from the electrode pad (30) to the surface of the substrate (24/26), wherein
the conductive portion (16) is in a state in which the conductive portion (16) is electrically connected to a wiring (36, para [0017]) on the surface of the substrate (24/26), and
the conductive portion (16) includes a probe region (37, para [0016]) to contact a probe (this is a functional limitation/intended use).
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Regarding claim 3, Yong et al. teaches wherein (Fig. 3), the conductive portion (16) includes a wiring region (22) for an electrical connection with the wiring (36: 38) at a first position (where the wire bond 38 located) that is directly above the electrode pad (30) on the surface of the substrate (24/26) (this is a functional limitation/intended use).
Regarding claim 4, Yong et al. teaches wherein (Fig. 3), an area of the wiring region (22) is larger area (see Fig. 3) than an area of the electrode pad (30).
Regarding claim 5, Yong et al. teaches wherein (Fig. 3), the probe region (37) is at a second position (where the probe 37 located) different from the first position.
Regarding claim 6, Yong et al. teaches wherein (Fig. 3), the conductive portion (16) includes a wiring region (22) for an electrical connection with the wiring (36) at a second position different from a first position that is directly above the electrode pad (30) on the surface of the substrate (24/26) (this is a functional limitation/intended use).
Regarding claim 7, Yong et al. teaches wherein (Fig. 3), the probe region (37) is at the first position.
Regarding claim 8, Yong et al. teaches wherein (Fig. 3),
a plurality of electrode pads (30, 30….are horizontally place in the substrate 24/26) and a plurality of conductive portions (16, 16…. are horizontally place in the substrate 24/26) are in series (horizontally lined up, see Fig. 3) along an edge of the substrate (24/26),
the plurality of electrode pads (30, 30….) includes the electrode pad (30), and
the plurality of conductive portions (16, 16….) includes the conductive portion (16).
Regarding claim 9, Yong et al. teaches wherein (Fig. 3),
a plurality of electrode pads (30, 30….) and a plurality of conductive portions (16, 16….) are in a zigzag pattern (see the annotated figure below) along an edge of the substrate (22/26),
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the plurality of electrode pads (30, 30….) includes the electrode pad (30), and
the plurality of conductive portions (16, 16….) includes the conductive portion (16).
Claim Rejections - 35 USC § 103
10. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
11. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
12. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
13. The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
a. Determining the scope and contents of the prior art.
b. Ascertaining the differences between the prior art and the claims at issue.
c. Resolving the level of ordinary skill in the pertinent art.
d. Considering objective evidence present in the application indicating obviousness or non-obviousness.
14. Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Yong et al. (US 2003/0173667 A1) as applied to claim 1 above.
Regarding claim 2, Yong et al. teaches all of the limitations of claim 1 from which this claim depends.
Yong et al. teaches wherein (Fig. 3), a certain depth of the electrode pad from the surface of the substrate as shown in the annotated figure of claim 1.
However, Yong et al. is explicitly silent of disclosing wherein ‘the specific depth is one of equal to 1 micrometer or greater than 1 micrometer’. It would have been obvious to select intended ‘specific depth’ so that the depth to be within the quoted range, to optimize the package thickness of the electronic device. In addition, to an ordinary artisan practicing the invention, absent evidence of disclosure of criticality for the range giving unexpected results, it is not inventive to discover optimal or workable ranges by routine experimentation. In re Aller, 220 F. 2d 454, 105 USPQ 233, 235 (CCPA 1955). Furthermore, the specification contains no disclosure of either the critical nature of the claimed depth or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen depth or upon another variable recited in a claim, the Applicant must show that the chosen depth is critical. See In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ 2d 1934, 1936 (Fed. Cir. 1990).
15. Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Yong et al. (US 2003/0173667 A1) as applied to claim 1 above, and further in view of Mitsuhashi (US 2014/0231950 A1).
Regarding claim 10, Yong et al. teaches all of the limitations of claim 1 from which this claim depends.
Yong et al. is explicitly silent of disclosing wherein the substrate includes a logic substrate and a sensor substrate,
the sensor substrate is stacked on the logic substrate,
the electrode pad is on the logic substrate, and
the conductive portion is in a region from the electrode pad to a surface of the sensor substrate.
Mitsuhashi teaches wherein (Fig. 6), the substrate (100/200, para [0082]) includes a logic substrate (200) and a sensor substrate (100),
the sensor substrate (100) is stacked on the logic substrate (200),
the electrode pad (210P) is on the logic substrate (200), and
the conductive portion (401) is in a region from the electrode pad (210P) to a surface of the sensor substrate (100).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to apply the teaching as taught by Mitsuhashi, and replace the substrate of Yong et al., along with multilayered substrate comprising sensor/logic segments, in order to construct a solid-state imaging device (para [0006]).
Examiner’s Note
16. Applicant is reminded that the Examiner is entitled to give the broadest reasonable interpretation to the language of the claims. Furthermore, the Examiner is not limited to Applicants' definition which is not specifically set forth in the claims. See MPEP 2111, 2123, 2125, 2141.02 VI, and 2182.
Examiner has cited particular paragraphs and/or columns/lines in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner. See MPEP 2141.02 VI.
In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Reasons for Indicating Allowable Subject Matter
17. Claims 11-13 are allowed.
18. The following is an examiner’s statement of reasons for allowance: the prior art of record alone or in combination neither teaches nor makes obvious a method for manufacturing a semiconductor device, comprising:
….
curing the conductive paste, wherein applying the conductive paste and curing the conductive paste are repeated until the conductive paste becomes electrically connectable to a wiring on the surface of the substrate;
19. The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure: prior art, Yong et al. (US 2003/0173667 A1) shows semiconductor device in Fig. 3, that depicts electrode pad at a certain depth from the surface of the substrate, but does not show manufacturing steps of the semiconductor device as claimed. Therefore, either by itself or in combination with other arts does not teach the above quoted limitations in section 18.
Response to Arguments
20. It has been acknowledged that the applicant amended claims 1-13, per the response dated on 09/17/2025.
Applicant’s arguments in pages 9-10 of the remarks section, with respect to the amended limitations have been reviewed, however, the previously cited prior art reference, Yong et al. (US 2003/0173667 A1) is still applicable to reject the claims as presented in the current office action above. Therefore, it has been suggested to amend the claim (s) per the structure of the invention that would differentiate from the prior art (s).
Conclusion
21. Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
22. Any inquiry concerning this communication or earlier communications from the examiner should be directed to DIDARUL MAZUMDER whose telephone number is (571)272-8823. The examiner can normally be reached M-F 9-5.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
23. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Partridge can be reached at 571-270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DIDARUL A MAZUMDER/Primary Examiner, Art Unit 2812