Prosecution Insights
Last updated: April 19, 2026
Application No. 18/005,264

SEMICONDUCTOR DEVICE, AND PRODUCTION METHOD FOR SEMICONDUCTOR DEVICE

Final Rejection §103
Filed
Jan 12, 2023
Examiner
DYKES, LAURA M
Art Unit
2892
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Rohm Co. Ltd.
OA Round
2 (Final)
65%
Grant Probability
Moderate
3-4
OA Rounds
2y 10m
To Grant
92%
With Interview

Examiner Intelligence

Grants 65% of resolved cases
65%
Career Allow Rate
321 granted / 497 resolved
-3.4% vs TC avg
Strong +28% interview lift
Without
With
+27.9%
Interview Lift
resolved cases with interview
Typical timeline
2y 10m
Avg Prosecution
42 currently pending
Career history
539
Total Applications
across all art units

Statute-Specific Performance

§103
50.9%
+10.9% vs TC avg
§102
25.7%
-14.3% vs TC avg
§112
16.4%
-23.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 497 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . This OA is in response to the amendment filled on 12/02/2025 that has been entered, wherein claims 1-20 are pending. Information Disclosure Statement The information disclosure statement (IDS) submitted on 10/21/2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Specification The objection to the tittle is withdrawn in light of Applicant’s amendment of 12/2/2025. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-4, 9-14 and 17-20 are rejected under 35 U.S.C. 103 as being unpatentable over Kanazawa et al. (US 2010/0289127 A1) of record in view of Muto et al. (US 2015/0060940 A1) of record and Kasem et al. (US 2006/0110856 A1) as evidenced by Ogawa et al. (US 2018/0053737 A1) of record . Regarding claim 1, Kanazawa teaches a semiconductor device(Fig. 43) comprising: a metal portion(TAB2, ¶0069) that has an obverse surface facing in a thickness direction; a semiconductor element(5B, ¶0070) that has a first electrode(not illustrated, collector electrode, ¶0071) opposing the obverse surface, and a second electrode(6, ¶0126) and a third electrode(7, ¶0126) that are opposite to the first electrode(not illustrated, collector electrode, ¶0071) in the thickness direction and are spaced apart from each other, the first electrode(not illustrated, collector electrode, ¶0071) being electrically joined(¶0071) to the obverse surface; a first joining layer(4, ¶0071) that electrically joins the first electrode(not illustrated, collector electrode, ¶0071) and the obverse surface to each other; a first conductive member(29, ¶0126) electrically joined to the second electrode(6, ¶0126); and a second conductive member(11, ¶0126) electrically joined to the third electrode(7, ¶0126), wherein the third electrode(7, ¶0126) is smaller(Fig. 43) in area than the second electrode(6, ¶0126) as viewed along the thickness direction, and the second conductive member(11, ¶0126) is smaller in Young's modulus(¶0126, wherein the Al metal of wire 11 has a smaller Young's modulus then the Cu metal of clip 29, as evidenced by Ogawa ¶0036) than the first conductive member(29, ¶0126). Kanazawa is not relied on to teach a second joining layer that electrically joins the first conductive member(29, ¶0126) and the second electrode(6, ¶0126) to each other and a thickness of the first joining layer(4, ¶0071) is greater than a thickness of the second joining layer. Muto teaches a semiconductor device(Fig. 9) comprising a second joining layer(ADH2, ¶0121) that electrically joins the first conductive member(CLP, ¶0121) and the second electrode(EP, ¶0121) to each other. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Kanazawa, to include a second joining layer that electrically joins the first conductive member and the second electrode to each other, as taught by Muto, so that the first conductive member can occupy a large area which allow for large current to flow(¶0121) and so that the high-melting-point solder used in the semiconductor device PAC is not melted by the heat treatment (reflow) performed when the semiconductor device PAC and the wiring board are connected, thus preventing the formation of a crack in the resin with which the semiconductor device PAC is sealed due to the volume expansion resulting from the melting of the high-melting-point solder or the leakage of the molten solder to the outside(¶0134). Kanazawa and Muto are not relied on to teach a thickness of the first joining layer(4, ¶0071) is greater than a thickness of the second joining layer. Kasem teaches a semiconductor device(Fig. 5) wherein a thickness of the first joining layer(18, ¶0038) is greater(¶0038) than a thickness of the second joining layer(16, ¶0038). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device as taught by Kanazawa, so that a thickness of the first joining layer is greater than a thickness of the second joining layer, as taught by Kasem, so that the lower joining layer is s more rugged and is better able to withstand differential lateral expansion between semiconductor element and the elements of metal portion and so that the second joining layer can have a wider area of contact between semiconductor element and first conductive member thus increasing the strength of the second joining layer(¶0038). Regarding claim 2, Kanazawa teaches the semiconductor device according to claim 1, wherein the first joining layer(4, ¶0071) contains tin(Sn, ¶0070). Regarding claim 3, Kanazawa teaches the semiconductor device according to claim 2, but is not relied on to teach the second joining layer is made of a same material as the first joining layer(4, ¶0071). Muto teaches a semiconductor device(Fig. 9) wherein the second joining layer(ADH2, ¶0121) is made of a same material(high-melting-point solder, ¶0136) as the first joining layer(ADH1, ¶0129). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Kanazawa, so that the second joining layer is made of a same material as the first joining layer, as taught by Muto, so that the first conductive member can occupy a large area which allow for large current to flow(¶0121) and so that the high-melting-point solder used in the semiconductor device PAC is not melted by the heat treatment (reflow) performed when the semiconductor device PAC and the wiring board are connected, thus preventing the formation of a crack in the resin with which the semiconductor device PAC is sealed due to the volume expansion resulting from the melting of the high-melting-point solder or the leakage of the molten solder to the outside(¶0134). Regarding claim 4, Kanazawa teaches the semiconductor device according to claim 3, wherein the second conductive member(11, ¶0126) is greater in linear expansion coefficient(¶0126, wherein the Al metal of wire 11 has a greater linear expansion coefficient then the Cu metal of clip 29, as evidenced by Ogawa ¶0036) than the first conductive member(29, ¶0126). Regarding claim 9, Kanazawa teaches the semiconductor device according to claim 3, further comprising: a first lead(3(G2), ¶0068) that has a first joining surface(surface of 3(G2) contacting 29) facing a same side as the obverse surface in the thickness direction, the first lead(3(G2), ¶0068) being spaced apart from the metal portion(TAB2, ¶0069) in a first direction perpendicular to the thickness direction; wherein the first lead(3(G2), ¶0068) contains copper(Cu, ¶0067). Kanazawa is not relied on to teach a third joining layer that electrically joins the first conductive member(29, ¶0126) and the first joining surface(surface of 3(G2) contacting 29) to each other, and the third joining layer is made of a same material as the first joining layer(4, ¶0071). Muto teaches a semiconductor device(Fig. 9) comprising a third joining layer(ADH2, ¶0121) that electrically joins the first conductive member(CLP, ¶0121) and the first joining surface(surface of ET contacting ADH2) to each other, wherein the third joining layer(ADH2, ¶0121) is made of a same material(high-melting-point solder, ¶0136) as the first joining layer(ADH1, ¶0129). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Kanazawa, to include a third joining layer that electrically joins the first conductive member and the first joining surface to each other, and the third joining layer is made of a same material as the first joining layer, as taught by Muto, so that the first conductive member can occupy a large area which allow for large current to flow(¶0121) and so that the high-melting-point solder used in the semiconductor device PAC is not melted by the heat treatment (reflow) performed when the semiconductor device PAC and the wiring board are connected, thus preventing the formation of a crack in the resin with which the semiconductor device PAC is sealed due to the volume expansion resulting from the melting of the high-melting-point solder or the leakage of the molten solder to the outside(¶0134). Regarding claim 10, Kanazawa teaches the semiconductor device according to claim 9, wherein, in the thickness direction, the first joining surface(surface of 3(G2) contacting 29) is closer(Fig. 6) to the semiconductor element(5B, ¶0070) than to the obverse surface. Regarding claim 11, Kanazawa teaches the semiconductor device according to claim 10, but is not relied on to teach a thickness of the metal portion(TAB2, ¶0069) is greater than a maximum thickness of the first lead(3(G2), ¶0068). Muto teaches a semiconductor device(Fig. 9) wherein a thickness of the metal portion(TAB, ¶0118) is greater(¶0129) than a maximum thickness of the first lead(ET, ¶0129). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Kanazawa, so that a thickness of the metal portion is greater than a maximum thickness of the first lead, as taught by Muto, so that the metal portion can function as a heat spreader for enhancing a heat release efficiency(¶0118). Regarding claim 12, Kanazawa teaches the semiconductor device according to claim 9, further comprising a second lead(3(GND), ¶0068) that has a second joining surface(surface of 3(GND) contacting 11) facing a same side as the obverse surface in the thickness direction, the second lead(3(GND), ¶0068) being spaced apart from both the metal portion(TAB2, ¶0069) and the first lead(3(G2), ¶0068), wherein the second conductive member(11, ¶0126) is electrically joined(¶0081) to the second joining surface(surface of 3(GND) contacting 11). Regarding claim 13, Kanazawa teaches the semiconductor device according to claim 12, but is not relied on to teach in the thickness direction, the second joining surface(surface of 3(GND) contacting 11) is closer(Fig. 4) to the semiconductor element(5B, ¶0070) than to the obverse surface. Muto teaches a semiconductor device(Fig. 9) wherein in the thickness direction, the second joining surface(surface of SGT contacting W) is closer(Fig. 9B) to the semiconductor element(CHP1, ¶0119) than to the obverse surface. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Kanazawa, so that in the thickness direction, the second joining surface is closer to the semiconductor element than to the obverse surface, as taught by Muto, so that the metal portion can function as a heat spreader for enhancing a heat release efficiency(¶0118). Regarding claim 14, Kanazawa teaches the semiconductor device according to claim 1, further comprising a sealing resin(2A, ¶0067) that covers the semiconductor element(5B, ¶0070), the first conductive member(29, ¶0126), and the second conductive member(11, ¶0126), and a portion of the metal portion(TAB2, ¶0069), wherein the metal portion(TAB2, ¶0069) has a reverse surface opposite to the obverse surface in the thickness direction, and the reverse surface is exposed(Fig. 6, ¶0069) from the sealing resin(2A, ¶0067). Regarding claim 17, Kanazawa teaches the semiconductor device according to claim 1, wherein the semiconductor element(5B, ¶0070) includes a semiconductor substrate(5B, ¶0070) containing silicon carbide as a main material. Kanazawa does not explicitly state a semiconductor substrate(5B, ¶0070) containing silicon carbide as a main material. Kanazawa does teach the semiconductor substrate(5B, ¶0070) is an IGBT(¶0070). Silicon carbide is well known in the art(as evidenced by Ogawa, ¶0060) as a as a main material for an IGBT semiconductor substrate(5B, ¶0070) . It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the materials of silicon carbide as a main material for a semiconductor substrate since it has been held to be within the general skill of a worker in the art to select a known material on the base of its suitability, for its intended use involves only ordinary skill in the art. MPEP 2144.07 Regarding claim 18, Kanazawa teaches the semiconductor device according to claim 1, wherein the first conductive member(29, ¶0126) is joined to the second electrode(6, ¶0126) at an extremity(top) thereof. Regarding claim 19, Kanazawa teaches the semiconductor device according to claim 12, further comprising a third lead(3(COM), ¶0071) formed integral with the metal portion(TAB2, ¶0069), wherein an entirety of the third lead(3(COM), ¶0071) extends in parallel to the first direction as viewed in the thickness direction(Fig. 43). Regarding claim 20, Kanazawa teaches the semiconductor device according to claim 19, wherein the third lead(3(COM), ¶0071) includes a base portion adjacent to the metal portion(TAB2, ¶0069), and an elongated terminal portion connected to the base portion and having a smaller width than the base portion as viewed in the thickness direction(Fig. 43). Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Kanazawa et al. (US 2010/0289127 A1), of record, Muto et al. (US 2015/0060940 A1) and of record and Kasem et al. (US 2006/0110856 A1) as applied to claim 4 above, further in view of Harnden et al. (US 2003/0062601 A1) of record as evidenced by Ogawa et al. (US 2018/0053737 A1) of record. Regarding claim 8, Kanazawa, in view of Muto and Kasem, teaches the semiconductor device according to any one of claim 4. Kanazawa, in view of Muto and Kasem, does not explicitly state an area of the semiconductor element(5B, ¶0070) is 40% or less of an area of the obverse surface as viewed along the thickness direction. Harnden teaches a semiconductor device(Fig. 6H) wherein the semiconductor element(608, ¶0180) is 40%(¶0180, Table 4) or less of an area of the obverse surface(obverse surface of 606) as viewed along the thickness direction. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Kanazawa, so that the semiconductor element is 40% or less of an area of the obverse surface as viewed along the thickness direction, as taught by Harnden, in order to have improved area efficiency(¶0180) and so that leads can successfully conduct large amounts of heat away from the operating die through the metal portion and out of the package. External portions of the integral leads may then permit excess heat to be dissipated into the environment, and especially to be conducted into the printed circuit board where the heat can be spread over a larger area and subsequently radiated or drawn by convection into the air(¶0183). Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Kanazawa et al. (US 2010/0289127 A1) of record in view of Sato et al. (US 2010/0123240 A1) of record and Kasem et al. (US 2006/0110856 A1) of record as evidenced by Ogawa et al. (US 2018/0053737 A1) of record. Regarding claim 15, Kanazawa teaches a method of manufacturing a semiconductor device(Fig. 43) comprising: disposing a conductive joining material(4, ¶0071) on a metal portion(TAB2, ¶0069) that has an obverse surface facing in a thickness direction; disposing a semiconductor element(5B, ¶0070) on the joining material(4, ¶0071), the semiconductor element(5B, ¶0070) including a first electrode(not illustrated, collector electrode, ¶0071), a second electrode(6, ¶0126) and a third electrode(7, ¶0126), the first electrode(not illustrated, collector electrode, ¶0071) and the second electrode(6, ¶0126) being opposite to each other in the thickness direction, the third electrode(7, ¶0126) being disposed on a same side as the second electrode(6, ¶0126) in the thickness direction and spaced apart from the second electrode(6, ¶0126), the first electrode(not illustrated, collector electrode, ¶0071) facing the joining material(4, ¶0071); electrically joining the first electrode(not illustrated, collector electrode, ¶0071) to the obverse surface by the joining material(4, ¶0071) thereby forming a first joining layer(4, ¶0071) via which the first electrode(not illustrated, collector electrode, ¶0071) and the obverse surface are joined to each other; electrically joining the first conductive member(29, ¶0126) to the second electrode(6, ¶0126); and electrically joining the second conductive member(11, ¶0126) to the third electrode(7, ¶0126), wherein the third electrode(7, ¶0126) is smaller(Fig. 43) in area than the second electrode(6, ¶0126) as viewed along the thickness direction, and the second conductive member(11, ¶0126) is smaller in Young's modulus(¶0126, wherein the Al metal of wire 11 has a smaller Young's modulus then the Cu metal of clip 29, as evidenced by Ogawa ¶0036) than the first conductive member(29, ¶0126). Kanazawa is not relied on to teach electrically joining the first electrode(not illustrated, collector electrode, ¶0071) to the obverse surface by melting and solidifying the joining material(4, ¶0071), electrically joining the first conductive member(29, ¶0126) to the second electrode(6, ¶0126) via a second joining layer and a thickness of the first joining layer(4, ¶0071) is greater than a thickness of the second joining layer. Sato teaches a method of manufacturing a semiconductor device(Fig. 17) comprising electrically joining the first electrode(3d, ¶0134) to the obverse surface by melting and solidifying the joining material(11d, ¶0135), electrically joining the first conductive member(6, ¶01340) to the second electrode(3s, ¶0134) via a second joining layer(11b, ¶0134). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Kanazawa, electrically joining the first electrode to the obverse surface by melting and solidifying the joining material and electrically joining the first conductive member to the second electrode via a second joining layer, as taught by Sato, so that the joining material penetrates and expands through and over the back surface of the semiconductor element, which improves the bonding force between the semiconductor element and the obverse surface by the joining material resulting in the semiconductor element be securely fixed to the obverse surface(¶0135) and the first conductive member(¶0137). Kanazawa and Sato are not relied on to teach a thickness of the first joining layer(4, ¶0071) is greater than a thickness of the second joining layer. Kasem teaches a semiconductor device(Fig. 5) wherein a thickness of the first joining layer(18, ¶0038) is greater(¶0038) than a thickness of the second joining layer(16, ¶0038). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device as taught by Kanazawa, so that a thickness of the first joining layer is greater than a thickness of the second joining layer, as taught by Kasem, so that the lower joining layer is s more rugged and is better able to withstand differential lateral expansion between semiconductor element and the elements of metal portion and so that the second joining layer can have a wider area of contact between semiconductor element and first conductive member thus increasing the strength of the second joining layer(¶0038). Allowable Subject Matter Claim 16 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: Regarding dependent claim 16, the prior art of record neither anticipates nor renders obvious the claimed subject matter of the instant application as a whole either taken alone or in combination, in particular, prior art of record does not teach “ the outer portion is greater in size in the first direction than the semiconductor element”. Response to Arguments Applicant’s arguments with respect to claim 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to LAURA DYKES whose telephone number is (571)270-3161. The examiner can normally be reached M-F 9:30 am-5 pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, N. Drew Richards can be reached at 571-272-1736. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /LAURA M DYKES/Examiner, Art Unit 2892 /NORMAN D RICHARDS/Supervisory Patent Examiner, Art Unit 2892
Read full office action

Prosecution Timeline

Jan 12, 2023
Application Filed
Aug 30, 2025
Non-Final Rejection — §103
Dec 02, 2025
Response Filed
Mar 06, 2026
Final Rejection — §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12604567
DRIVING SUBSTRATE, MICRO LED TRANSFER DEVICE AND MICRO LED TRANSFER METHOD
2y 5m to grant Granted Apr 14, 2026
Patent 12604635
DISPLAY SCREEN, ELECTRONIC DEVICE AND MANUFACTURING METHOD
2y 5m to grant Granted Apr 14, 2026
Patent 12604648
DISPLAY DEVICE, METHOD OF MANUFACTURING THE SAME, AND TILED DISPLAY DEVICE
2y 5m to grant Granted Apr 14, 2026
Patent 12599024
DISPLAY MODULE AND SUBSTRATE THEREOF HAVING IMPROVED BINDING RELIABILITY OF SUBSTRATE AND FLEXIBLE CIRCUIT BOARD
2y 5m to grant Granted Apr 07, 2026
Patent 12588376
Substrate Arrangement and Manufacturing Method for a Micro Display
2y 5m to grant Granted Mar 24, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

AI Strategy Recommendation

Get an AI-powered prosecution strategy using examiner precedents, rejection analysis, and claim mapping.
Powered by AI — typically takes 5-10 seconds

Prosecution Projections

3-4
Expected OA Rounds
65%
Grant Probability
92%
With Interview (+27.9%)
2y 10m
Median Time to Grant
Moderate
PTA Risk
Based on 497 resolved cases by this examiner. Grant probability derived from career allow rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month