DETAILED ACTION
Claims 1, 5, and 7-10 have been examined.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Objections
Claim 1 is objected to because of the following informalities:
In the 2nd and 3rd to last lines, it appears that applicant omitted “of the plurality of single-bit registers” after each instance of “register”.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1, 5, and 7-10 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Referring to claim 1, applicant now claims that data input ends and data output ends are connected in parallel to each other. The examiner cannot find original support for connecting inputs to outputs. It would seem that there is support for parallel input and parallel outputs, but not for connecting inputs and outputs in parallel together.
Further referring to claim 7, applicant now claims that the clock buffer provides a clock signal for each single-bit register of the plurality of single-bit registers, including a single bit-register that is adjacent to the clock buffer, through multiple respective paths, including via another single-bit register (from claims 1 and 4 combined). However, there is no original support for sending a clock signal, for example, from clock buffer 420 in FIG.4, both directly adjacent to 410-7, but also to 410-7 through another register (e.g. 410-5, 410-4, 410-2, 410-1, etc.). In short, the examiner has not found support for sending adjacent registers a clock signal along multiple paths in FIG.4.
All dependent claims are rejected due to their dependence on a claim lacking adequate written description.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 5, and 7-10 are rejected under 35 U.S.C. 103 as being unpatentable over Koana, JP 4044083 (herein referred to as ‘083), a translation of which was previously provided, in view of the examiner’s taking of Official Notice.
Referring to claim 1, ‘083 has taught a multi-bit register (FIG.14) comprising: a plurality of single-bit registers (see FIG.14, at least portions of at least some of the flip flops (F/F), which store/register a single bit, as is known. A flip-flop is a single-bit register), each of which is configured to store a single bit of data (the purpose of a flip-flop is to store a single bit of data, as is known); and a clock buffer configured to provide a clock signal for the plurality of single-bit registers (see FIG.10 and the first paragraph under “(Second Embodiment)” (of the translation). A clock buffer comprising two inverters (15a, 15b) is in F/F1a. The buffer takes as input a clock signal (CLKIN) and provides a buffered clock signal (CLKOUT)), wherein:
the plurality of single-bit registers and the clock buffer are arranged into a matrix-like configuration (see FIG.14), and the clock buffer is arranged at an intervening position of the matrix-like configuration (from FIGs.10 and 14, the clock buffer is within F/F1a and F/F1a is in the middle of the matrix and in between other flop-flops), and
in the matrix-like configuration, clock signal wires are connected between the clock buffer and clock input ends of the plurality of single-bit registers, so that the clock buffer provides a clock signal for each single-bit register of the plurality of single-bit registers through multiple respective paths that are connected between the clock buffer and each single-bit register (see FIG.14, which shows bold clock signal wires between the clock buffer in F/F1a and clock input ends of other flip-flops such that the clock buffer provides a clock signal for each of the flip-flops through multiple connected paths. For instance, flip-flops c, g, and e in FIG.14 do not have a direct connection to the clock buffer in F/F1a. However, there are multiple paths to each of these flip-flops from the clock buffer (e.g. F/F1g has a clock path including F/F1a and F/F1h, and another clock path including F/F1a and F/F1f)), the multiple respective paths including a path from the clock buffer to each single-bit register via another single-bit register of the plurality of single-bit registers (again, the multiple paths between F/F1a (clock buffer) and F/F1g include a path that involves another FF, i.e., F/F1f or F/F1h. Similar paths exist between F/F1a and F/F1e, and between F/F1a and F/F1c).
‘083, as modified, has not taught that data input ends and data output ends of the plurality of single-bit registers being connected in parallel to each other. However, Official Notice is taken that multiple parallel inputs and multiple parallel outputs for a multi-bit register were well known in the art before applicant’s invention. Parallel inputs allow multiple bits to be written to the multi-bit register at the same time, while parallel output allow multiple bits to be read from a multi-bit register at the same time, thereby speeding up reading/writing via higher throughput. As a result, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify ‘083 such that data input ends and data output ends of the plurality of single-bit registers being connected in parallel to each other.
With respect to the limitation of the clock buffer arranged outside the plurality of single-bit registers, this is not patentable for multiple reasons:
First, F/F1a may be considered separate from the claimed plurality of single-bit registers. In other words, the plurality of single-bit registers could include at least some of F/F1b-h, but not F/F1a. Under this interpretation, the clock buffer in F/F1a is outside of F/F1b-h.
Secondly, and alternatively, a given single-bit register can be interpreted as the storage portion of a FF that actually stores/registers a bit. This would be circuitry that is separate from the clock buffer circuitry whose purpose is only to propagate a clock signal, as shown in FIG.10. Under this interpretation, ‘083 has taught the limitation in question because the clock buffer circuitry shown would be outside of other circuitry in the FF that actually stores a bit.
Thirdly, and alternatively, if the single-bit register must be interpreted as the entire FF, which the examiner believes is too narrow of an interpretation, then ‘083 has not taught the limitation in question because FIG.10 shows the clock buffer inside of the FF. However, rearranging parts and/or separating components are deemed routine expedients, not patentable distinctions (see MPEP 2144.04, including sections V(C) and VI(C)). In this case, applicant has not demonstrated the criticality of the clock buffer being outside of the single-bit registers. As a result, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify ‘083 such that the clock circuitry is simply moved outside of the FF in FIG.10 with no modification of device operation. The clock flow would still be the same throughout the matrix, but the buffer itself could be separate from the FFs.
Referring to claim 5, ‘083, as modified, has taught the multi-bit register according to claim 1, wherein the clock buffer is arranged at a substantially middle position of the matrix-like configuration (again, see FIGs.10 and 14, where the clock buffer is in F/F1a (or, as optionally modified, just outside of F/F1a. Either way, this corresponds to a position that is substantially in the middle of the matrix configuration).
Referring to claim 7, ‘083, as modified, has taught the multi-bit register according to claim 1, wherein in the matrix-like configuration, a clock signal wire is directly connected between the clock buffer and any one of the plurality of single-bit registers that is adjacent to the clock buffer (see FIGs.10 and 14. The clock buffer is directly connected to adjected circuits F/F1b,d,f,h), and a clock signal wire is directly connected between any adjacent two of the single-bit registers (see FIG.14. Any two adjacent register circuits (F/Fs) have a clock signal therebetween).
Referring to claim 8, ‘083, as modified, has taught the multi-bit register according to claim 1, wherein a ratio of the number of rows to the number of columns of the matrix-like configuration is greater than or equal to 0.5 and less than or equal to 3 (in FIG.14, there are three rows and three columns, giving a row-to-column ratio of 1).
Referring to claim 9, ‘083, as modified, has taught a chip comprising the multi-bit register according to claim 1 (see the section titled “ADVANTAGEOUS-EFFECTS” in the translation, under which is stated “the area of the semiconductor chip is reduced”).
Referring to claim 10, ‘083, as modified, has taught the chip according to claim 9, but has not taught that the chip is comprised by a computing apparatus. However, Official Notice is taken that a register file was well known in the art before the effective filing date of the claimed invention. Specifically, a register file comprising individual registers is included on a processor chip so as to form an overall computing apparatus where the processor can process program instructions and retrieve and store data from/to the registers as part of the processing to generate results. As such, in order to realize a system usable for executing programs, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify ‘083 such that the chip containing the register is part of a computing apparatus.
Response to Arguments
On page 5 of applicant’s response submitted on November 26, 2025 (hereafter “the response”), applicant notes that applicant didn’t submit NPL, but instead submitted a copy of a foreign office action (and its translation) for the examiner’s convenience.
The examiner notes that these documents are labeled as NPL in the official record. If applicant wants the examiner to consider this action/translation (which the examiner presumes based on the submission thereof), then they must be cited on an IDS as NPL.
Based on the amendments and persuasive arguments pertaining to Sood, the examiner has withdrawn the Sood rejection.
On page 12 of the response, applicant argues that it is unreasonable to interpret the lines shown in FIG.14 of ‘083 to be both clock signal lines and data signal lines.
The examiner is not taking such an interpretation. From FIG.10, it can be seen that a FF includes a clock buffer, which sends a clock signal to a neighboring FF. Thus, the lines shown in FIG.14 correspond to clock signal lines. A flip-flop, which is a ubiquitous component in the computing/electronics arts, has a separate data line to store data input thereto.
On page 12 of the response, applicant argues that FIG.10 shows the clock buffer within a flip-flop (single-bit register) and thus does not teach the clock buffer being arranged outside the plurality of single-bit registers.
The claim is worded broadly enough that ‘083 does teach this limitation (see rejection of claim 1). However, it would alternatively be obvious to modify ‘083 to render this limitation unpatentable (again see the rejection of claim 1).
On pages 12-13 of the response, applicant makes arguments with reference to FIGs.1, 3, and 13 of ‘083.
These arguments are not persuasive because they appear to be different embodiments than the examiner is relying on in the rejection. The examiner is relying on FIGs.10 and 14.
Conclusion
The following prior art previously or currently made of record and not relied upon is considered pertinent to applicant's disclosure:
Oshiyama, 2016/0154049, has taught transmitting a clock over two separate paths. If one path fails, the other can be selected to provide the clock (see FIG.8 and paragraphs 208-213, along with FIG.7 and the description thereof (e.g. in paragraphs 201-205)).
This document is deemed to be particularly relevant to applicant’s claims and applicant is encouraged to review and tailor any amendments to ensure distinction from this document, and any previously-cited documents.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to David J. Huisman whose telephone number is 571-272-4168. The examiner can normally be reached on Monday-Friday, 9:00 am-5:30 pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta, can be reached at 571-270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/David J. Huisman/Primary Examiner, Art Unit 2183