DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 01/13/2026 has been entered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 5-6, and 10 are rejected under 35 U.S.C. 103 as being unpatentable over US 2021/0376089 to Vellianitis et al. (hereinafter Vellianitis) in view of Baeck et al. (US 2020/0176603, hereinafter Baeck), Hong et al. (US Patent 9,171,960, hereinafter Hong), Zhou et al. (US 2019/0172954, hereinafter Zhou), and Yamazaki et al. (US 2013/0009219, hereinafter Yamazaki) (the reference US 2016/0247934 by Hanaoka is presented as evidence).
With respect to claim 1, Vellianitis discloses a thin film transistor (Vellianitis, Figs. 1-6, ¶0002, ¶0026-¶0036) comprising:
a substrate (100) (Vellianitis, Figs. 1-6, ¶0022);
an insulating layer (120) (Vellianitis, Figs. 1-6, ¶0023) formed on the substrate (100);
an active layer (130/140) (Vellianitis, Figs. 1-6, ¶0024) formed on the insulating layer (120); and
a source electrode layer (e.g., contact terminal 160) (Vellianitis, Figs. 1-6, ¶0031) and a drain electrode layer (160) which are formed on the active layer (130/140) to be spaced apart from each other,
wherein the active layer (130/140) comprises:
a first oxide semiconductor layer (e.g., 130, IGZO) (Vellianitis, Figs. 1-6, ¶0024) including indium (ln), gallium (Ga), and oxygen (O); and
a second oxide semiconductor layer (e.g., binary oxide layer 140 including zinc oxide) (Vellianitis, Figs. 1-6, ¶0024) formed on the first oxide semiconductor layer (130) and consisting of zinc (Zn) and O.
Further, Vellianitis does not specifically disclose that (1) a first oxide semiconductor layer consisting of indium (ln), gallium (Ga), and oxygen (O); (2) wherein the first oxide semiconductor layer is represented by In1-xGaxO1.5, wherein x is 0.3 or less; (3) wherein the second oxide semiconductor layer has a thickness of 1.5 nm to 3 nm.
Regarding (1), Vellianitis discloses that a first oxide semiconductor layer (130) (Vellianitis, Figs. 1-6, ¶0024) includes IGZO or similar conducting oxide semiconductor layer material such as an indium tin oxide (ITO) or indium zinc oxide (IZO).
Further, Baeck teaches forming a thin-film transistor (100) (Baeck, Fig. 1, ¶0001, ¶0008-¶0009, ¶0044-¶0050) on a substrate (110) including an insulating layer (121), wherein a first oxide semiconductor layer (131) includes gallium oxide having great film stability because gallium forms a stabilized bonding to oxygen, and the first oxide semiconductor layer (131) includes an IGZO film (indium gallium zinc oxide, InGaZnO) or an IGO (indium gallium oxide, InGaO), to provide good film stability.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the thin film transistor of Vellianitis by forming a first oxide semiconductor including indium gallium oxide (IGO) as taught by Baeck to have the thin film transistor, wherein the active layer comprises: a first oxide semiconductor layer consisting of indium (ln), gallium (Ga), and oxygen (O), in order to provide an oxide semiconductor layer having improves film stability and good mechanical properties (Baeck, ¶0001, ¶0008-¶0009, ¶0050).
Regarding (2), Hong teaches forming an oxide semiconductor TFT (Hong, Fig. 6, Col. 1, lines 7-9; Col. 4, lines 53-67; Col. 5, lines 23-35; Col. 10, lines 31-43; Col. 14, lines 1-53; Col. 15, lines 24-54; Col. 16, lines 22-26; Col. 17, lines 32-67; Col. 18, lines 17-67; Col. 19, lines 1-20) comprising an oxide semiconductor layer by atomic layer deposition (ALD) to precisely control composition and stoichiometry to produce a high mobility region near interface between the semiconductor layer and the gate insulator and highly stable region near the back of the channel surface. The oxide semiconductor layer includes several sequences of at least two metal oxides to form indium gallium oxide (IGO) (Hong, Fig. 6, Col. 16, lines 22-26; Col. 17, lines 32-67; Col. 18, lines 17-67; Col. 19, lines 1-20), wherein the first metal oxide includes gallium oxide at the concentration of about 20% at the lower surface and about 80% at the upper surface, and indium oxide at the concentration of about 80% at the lower surface and about 20% at the upper surface the second metal oxide includes indium oxide. A region of high electron mobility is formed at the lower surface with about 20% of gallium oxide and about 80% of indium oxide to increase electric characteristics of the TFT device.
Further, Zhou teaches forming metal oxide semiconductor TFT (Zhou, Fig. 1, ¶0009, ¶0025-¶0028, ¶0032, ¶0067, ¶0075) comprising oxide semiconductor active layer (40) including indium gallium oxide region (41) with oxygen content OX1, where X1 is between 1 and 10, and indium gallium oxide region (42/43) with reduced content of oxygen OX2, where X2 is less than 1, to provide a channel region (41) having semiconductor properties and source/drain contact regions (42/43) having conductive metal properties to improve working stability of the oxide semiconductor TFT.
Further, it is well-known in the art of oxide semiconductor transistor (e.g., as evidenced by Hanaoka, ¶0148) that in an oxide semiconductor, the s orbital of heavy metal mainly contributes to carrier transfer, and when the proportion of In in the oxide semiconductor is increased, overlap of the s orbitals is likely to be increased. Thus, an oxide having a composition in which the proportion of In is higher than that of Ga has higher mobility than an oxide having a composition in which the proportion of In is equal to or lower than that of Ga.
Thus, Hong recognizes that the concentrations of two metal oxides in the deposition of the oxide semiconductor layer impact electron mobility of the oxide semiconductor layer. Further, Hanaoka recognizes that proportion of In with respect Ga in oxide composition impacts carrier transfer (mobility). Further, Zhou recognizes that the concentration of oxygen impacts semiconductor/metallic properties of the oxide semiconductor layer. Thus, the concentrations of two metal oxides and oxygen, and specifically proportion of In with respect Ga are result-effective variables.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to vary, through routine optimization, the concentrations of two metal oxides and oxygen, and proportion of In with respect Ga as Hong, Hanaoka, and Zhou have identified the concentrations of two metal oxides and oxygen, and proportion of In with respect Ga as result-effective variables. Further, a person of ordinary skill in the art would have had a reasonable expectation of success to arrive at specific concentrations of two metal oxides and oxygen, and proportion of In with respect Ga to have the first oxide semiconductor layer is represented by In1-xGaxO1.5, wherein x is 0.3 or less, in order to provide oxide semiconductor having high electron mobility to increase electric characteristics and to improve working stability of the oxide semiconductor TFT as taught by Hong (Col. 16, lines 22-26; Col. 18, lines 17-67; Col. 19, lines 1-20) and Zhou (¶0009, ¶0025, ¶0032, ¶0076), and evidenced by Hanaoka (¶0148) ( (MPEP 2144.05).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the thin film transistor of Vellianitis by optimizing composition of the first oxide semiconductor by forming sequence of the two metal oxides with controlled composition and stoichiometry as taught by Hong, and optimizing proportion of In with respect Ga in the oxide semiconductor (as evidenced by Hanaoka), wherein the first oxide semiconductor includes specific content of oxygen in the channel region as taught by Zhou to have the thin film transistor, wherein the first oxide semiconductor layer is represented by In1-xGaxO1.5, wherein x is 0.3 or less, in order to provide oxide semiconductor layer with high electron mobility to increase electric characteristics of TFT; and to improve working stability of the oxide semiconductor TFT (Hong, Col. 1, lines 7-9; Col. 4, lines 53-67; Col. 5, lines 23-35; Col. 16, lines 22-26; Col. 18, lines 17-67; Col. 19, lines 1-20; Hanaoka, ¶0148; Zhou, ¶0009, ¶0025, ¶0032, ¶0076).
Regarding (3), Vellianitis discloses the thin film transistor, wherein the second oxide semiconductor layer (140) (Vellianitis, Figs. 1-6, ¶0024) has a thickness of 5 nm or less.
Further, Yamazaki teaches forming a thin film transistor (Yamazaki, Figs. 1A-1B, ¶0008-¶0009, ¶0012, ¶0022-¶0023, ¶0078, ¶0089-¶0091, ¶0128- ¶0130) comprising stacked oxide semiconductor layers (101/102) having different energy gaps to provide increased on-state characteristics (e.g., on-state current and field-effect mobility) to achieve high-speed response and high-speed operation for a higher performance semiconductor device by adjusting electric characteristics of the transistor. The stacked oxide semiconductor layers (101/102) comprise oxide semiconductor materials including one-component metal oxide (e.g., zinc oxide (Zn-O)) and two-component metal oxide (e.g., In-Ga-based oxide), wherein a thickness of an oxide semiconductor layer (Yamazaki, Figs. 1A-1B, ¶0089-¶0091, ¶0128-¶0130) is equal to or greater than 1 nm and equal to or less than 10 nm.
Thus, Yamazaki teaches forming one-component metal oxide (e.g., zinc oxide (Zn-O)) having a thickness equal to 1 nm (Yamazaki, Figs. 1A-1B, ¶0128). Note that a specific example in the prior art which is within a claimed range anticipates the range (M.P.E.P. §2131.03).
Thus, Yamazaki recognizes that using oxide semiconductor layers having different energy gaps and a specific thickness impacts operation characteristics (e.g., on-state state characteristics including on-state current and field-effect mobility) for a higher performance semiconductor device. Thus, the compositions and thicknesses of the stacked oxide semiconductor layers are result-effective variables.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to vary, through routine optimization, the compositions and thicknesses of the stacked oxide semiconductor layers as Yamazaki has identified the compositions and thicknesses of the stacked oxide semiconductor layers as result-effective variables. Further, a person of ordinary skill in the art would have had a reasonable expectation of success to arrive at specific compositions and thicknesses of the stacked oxide semiconductor layers to have the second oxide semiconductor layer having a thickness of 1.5 nm to 3 nm, in order to adjust electric characteristics (e.g., on-state current and field-effect mobility0 of the oxide semiconductor transistor with higher accuracy to provide oxide semiconductor transistor with appropriate electrical characteristics including high-speed response and high-speed operation for a higher performance semiconductor device as taught by Yamazaki (¶0008, ¶0012, ¶0015, ¶0022-¶0023, ¶0107, ¶0128-¶0130) ( (MPEP 2144.05).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the thin film transistor of Vellianitis by optimizing a thickness of the second oxide semiconductor layer (within a specific range of Yamazaki) of the stacked oxide semiconductor layers having different energy gaps as taught by Yamazaki to have the thin film transistor, wherein the second oxide semiconductor layer has a thickness of 1.5 nm to 3 nm, in order to adjust electric characteristics of the oxide semiconductor transistor with higher accuracy to provide oxide semiconductor transistor with appropriate electrical characteristics (e.g., increased on-state current and field-effect mobility) to achieve high-speed response and high-speed operation for a higher performance semiconductor device as taught by Yamazaki (¶0008, ¶0012, ¶0015, ¶0022-¶0023, ¶0107, ¶0128-¶0130).
With respect to claim 5, Vellianitis discloses a method for manufacturing a thin film transistor (Vellianitis, Figs. 10-15, ¶0002, ¶0026-¶0036, ¶0044-¶0055), the method comprising:
providing a substrate (300) (Vellianitis, Figs. 10-15, ¶0045);
forming a first oxide semiconductor layer (e.g., 330, IGZO) (Vellianitis, Figs. 10-15, ¶0045-¶0048) including indium (ln), gallium (Ga), and oxygen (O) on the substrate (300);
forming a second oxide semiconductor layer (e.g., binary oxide layer 340 including zinc oxide) (Vellianitis, Figs. 10-15, ¶0045-¶0048) consisting of zinc (Zn) and O on the first oxide semiconductor layer (330); and
forming a source electrode layer (e.g., contact terminal 360) (Vellianitis, Figs. 10-15, ¶0052-¶0053) and a gate electrode layer (311) to be spaced apart from each other on the second oxide semiconductor layer (340).
Further, Vellianitis does not specifically disclose (1) forming an insulating layer on the substrate; forming a first oxide semiconductor layer consisting of indium (ln), gallium (Ga), and oxygen (O) on the insulating layer; (2) wherein the first oxide semiconductor layer is represented by In1-xGaxO1.5, wherein x is 0.3 or less; (3) wherein the second oxide semiconductor layer has a thickness of 1.5 nm to 3 nm.
Regarding (1), Vellianitis discloses that a first oxide semiconductor layer (330) (Vellianitis, Figs. 10-15, ¶0046) includes IGZO or similar conducting oxide semiconductor layer material such as an indium tin oxide (ITO) or indium zinc oxide (IZO).
Further, Baeck teaches forming a thin-film transistor (100) (Baeck, Fig. 1, ¶0001, ¶0008-¶0009, ¶0044-¶0050) on a substrate (110) including an insulating layer (e.g., the buffer layer 121), wherein a first oxide semiconductor layer (131) includes gallium oxide having great film stability because gallium forms a stabilized bonding to oxygen, and the first oxide semiconductor layer (131) includes an IGZO film (indium gallium zinc oxide, InGaZnO) or an IGO (indium gallium oxide, InGaO) such that a first oxide semiconductor layer (131) consisting of indium (ln), gallium (Ga), and oxygen (O) is formed on the insulating layer (121), to provide good film stability (Baeck, Fig. 1, ¶0050). The insulating layer (e.g., the buffer layer 121) has good insulating properties ad good planarization properties and is formed to protect the semiconductor layer (130) (Baeck, Fig. 1, ¶0046).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the method of Vellianitis by forming a first oxide semiconductor including gallium on the buffer layer as taught by Baeck to have the method comprising: forming an insulating layer on the substrate; forming a first oxide semiconductor layer consisting of indium (ln), gallium (Ga), and oxygen (O) on the insulating layer, in order to protect an oxide semiconductor layer, and to provide the oxide semiconductor layer having improved film stability and good mechanical properties (Baeck, ¶0001, ¶0008-¶0009, ¶0046, ¶0050).
Regarding (2), Hong teaches forming an oxide semiconductor TFT (Hong, Fig. 6, Col. 1, lines 7-9; Col. 4, lines 53-67; Col. 5, lines 23-35; Col. 10, lines 31-43; Col. 14, lines 1-53; Col. 15, lines 24-54; Col. 16, lines 22-26; Col. 17, lines 32-67; Col. 18, lines 17-67; Col. 19, lines 1-20) comprising an oxide semiconductor layer by atomic layer deposition (ALD) to precisely control composition and stoichiometry to produce a high mobility region near interface between the semiconductor layer and the gate insulator and highly stable region near the back of the channel surface. The oxide semiconductor layer includes several sequences of at least two metal oxides to form indium gallium oxide (IGO) (Hong, Fig. 6, Col. 16, lines 22-26; Col. 17, lines 32-67; Col. 18, lines 17-67; Col. 19, lines 1-20), wherein the first metal oxide includes gallium oxide at the concentration of about 20% at the lower surface and about 80% at the upper surface, and indium oxide at the concentration of about 80% at the lower surface and about 20% at the upper surface the second metal oxide includes indium oxide. A region of high electron mobility is formed at the lower surface with about 20% of gallium oxide and about 80% of indium oxide to increase electric characteristics of the TFT device.
Further, Zhou teaches forming metal oxide semiconductor TFT (Zhou, Fig. 1, ¶0009, ¶0025-¶0028, ¶0032, ¶0067, ¶0075) comprising oxide semiconductor active layer (40) including indium gallium oxide region (41) with oxygen content OX1, where X1 is between 1 and 10, and indium gallium oxide region (42/43) with reduced content of oxygen OX2, where X2 is less than 1, to provide a channel region (41) having semiconductor properties and source/drain contact regions (42/43) having conductive metal properties to improve working stability of the oxide semiconductor TFT.
Further, it is well-known in the art of oxide semiconductor transistor (e.g., as evidenced by Hanaoka, ¶0148) that in an oxide semiconductor, the s orbital of heavy metal mainly contributes to carrier transfer, and when the proportion of In in the oxide semiconductor is increased, overlap of the s orbitals is likely to be increased. Thus, an oxide having a composition in which the proportion of In is higher than that of Ga has higher mobility than an oxide having a composition in which the proportion of In is equal to or lower than that of Ga.
Thus, Hong recognizes that the concentrations of two metal oxides in the deposition of the oxide semiconductor layer impact electron mobility of the oxide semiconductor layer. Further, Hanaoka recognizes that proportion of In with respect Ga in oxide composition impacts carrier transfer (mobility). Further, Zhou recognizes that the concentration of oxygen impacts semiconductor/metallic properties of the oxide semiconductor layer. Thus, the concentrations of two metal oxides and oxygen, and specifically proportion of In with respect Ga are result-effective variables.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to vary, through routine optimization, the concentrations of two metal oxides and oxygen, and proportion of In with respect Ga as Hong, Hanaoka, and Zhou have identified the concentrations of two metal oxides and oxygen, and proportion of In with respect Ga as result-effective variables. Further, a person of ordinary skill in the art would have had a reasonable expectation of success to arrive at specific concentrations of two metal oxides and oxygen, and proportion of In with respect Ga to have the first oxide semiconductor layer is represented by In1-xGaxO1.5, wherein x is 0.3 or less, in order to provide oxide semiconductor having high electron mobility to increase electric characteristics and to improve working stability of the oxide semiconductor TFT as taught by Hong (Col. 16, lines 22-26; Col. 18, lines 17-67; Col. 19, lines 1-20) and Zhou (¶0009, ¶0025, ¶0032, ¶0076), and evidenced by Hanaoka (¶0148) ( (MPEP 2144.05).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the method of Vellianitis by optimizing composition of the first oxide semiconductor by forming sequence of the two metal oxides with controlled composition and stoichiometry as taught by Hong, and optimizing proportion of In with respect Ga in the oxide semiconductor (as evidenced by Hanaoka), wherein the first oxide semiconductor includes specific content of oxygen in the channel region as taught by Zhou to have the method, wherein the first oxide semiconductor layer is represented by In1-xGaxO1.5, wherein x is 0.3 or less, in order to provide oxide semiconductor layer with high electron mobility to increase electric characteristics of TFT; and to improve working stability of the oxide semiconductor TFT (Hong, Col. 1, lines 7-9; Col. 4, lines 53-67; Col. 5, lines 23-35; Col. 16, lines 22-26; Col. 18, lines 17-67; Col. 19, lines 1-20; Hanaoka, ¶0148; Zhou, ¶0009, ¶0025, ¶0032, ¶0076).
Regarding (3), Vellianitis discloses the thin film transistor, wherein the second oxide semiconductor layer (140) (Vellianitis, Figs. 1-6, ¶0024) has a thickness of 5 nm or less.
Further, Yamazaki teaches forming a thin film transistor (Yamazaki, Figs. 1A-1B, ¶0008-¶0009, ¶0012, ¶0022-¶0023, ¶0078, ¶0089-¶0091, ¶0128- ¶0130) comprising stacked oxide semiconductor layers (101/102) having different energy gaps to provide increased on-state characteristics (e.g., on-state current and field-effect mobility) to achieve high-speed response and high-speed operation for a higher performance semiconductor device by adjusting electric characteristics of the transistor. The stacked oxide semiconductor layers (101/102) comprise oxide semiconductor materials including one-component metal oxide (e.g., zinc oxide (Zn-O)) and two-component metal oxide (e.g., In-Ga-based oxide), wherein a thickness of an oxide semiconductor layer (Yamazaki, Figs. 1A-1B, ¶0089-¶0091, ¶0128-¶0130) is equal to or greater than 1 nm and equal to or less than 10 nm.
Thus, Yamazaki teaches forming one-component metal oxide (e.g., zinc oxide (Zn-O)) having a thickness equal to 1 nm (Yamazaki, Figs. 1A-1B, ¶0128). Note that a specific example in the prior art which is within a claimed range anticipates the range (M.P.E.P. §2131.03).
Thus, Yamazaki recognizes that using oxide semiconductor layers having different energy gaps and a specific thickness impacts operation characteristics (e.g., on-state state characteristics including on-state current and field-effect mobility) for a higher performance semiconductor device. Thus, the compositions and thicknesses of the stacked oxide semiconductor layers are result-effective variables.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to vary, through routine optimization, the compositions and thicknesses of the stacked oxide semiconductor layers as Yamazaki has identified the compositions and thicknesses of the stacked oxide semiconductor layers as result-effective variables. Further, a person of ordinary skill in the art would have had a reasonable expectation of success to arrive at specific compositions and thicknesses of the stacked oxide semiconductor layers to have the second oxide semiconductor layer having a thickness of 1.5 nm to 3 nm, in order to adjust electric characteristics (e.g., on-state current and field-effect mobility0 of the oxide semiconductor transistor with higher accuracy to provide oxide semiconductor transistor with appropriate electrical characteristics including high-speed response and high-speed operation for a higher performance semiconductor device as taught by Yamazaki (¶0008, ¶0012, ¶0015, ¶0022-¶0023, ¶0107, ¶0128-¶0130) ( (MPEP 2144.05).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the method of Vellianitis by optimizing a thickness of the second oxide semiconductor layer (within a specific range of Yamazaki) of the stacked oxide semiconductor layers having different energy gaps as taught by Yamazaki to have the thin film transistor, wherein the second oxide semiconductor layer has a thickness of 1.5 nm to 3 nm, in order to adjust electric characteristics of the oxide semiconductor transistor with higher accuracy to provide oxide semiconductor transistor with appropriate electrical characteristics (e.g., increased on-state current and field-effect mobility) to achieve high-speed response and high-speed operation for a higher performance semiconductor device as taught by Yamazaki (¶0008, ¶0012, ¶0015, ¶0022-¶0023, ¶0107, ¶0128-¶0130).
Regarding claim 6, Vellianitis in view of Baeck, Hong, Zhou, and Yamazaki discloses the method of claim 5. Further, Vellianitis discloses the method, wherein at least one of the first and second oxide semiconductors (330/340) (Vellianitis, Figs. 10-15, ¶0024, ¶0046) is formed through atomic layer deposition (ALD).
Regarding claim 10, Vellianitis in view of Baeck, Hong, Zhou, and Yamazaki discloses the thin film transistor of claim 1. Further, Vellianitis does not specifically disclose a display device comprising the thin film transistor of claim 1.
However, Baeck teaches forming a display device comprising the thin film transistor including a first oxide semiconductor having great film stability and good mechanical properties (Baeck, Fig. 1, ¶0001, ¶0008-¶0009, ¶0044-¶0050).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the thin film transistor of Vellianitis/Baeck/Hong/Zhou/
Yamazaki by forming a display device comprising the first oxide semiconductor including gallium as taught by Baeck to have a display device comprising the thin film transistor of claim 1, in order to provide a display device having improved performance characteristics (Baeck, ¶0001, ¶0008-¶0009, ¶0046, ¶0050).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over US 2021/0376089 to Vellianitis in view of Baeck (US 2020/0176603), Hong (US Patent 9,171,960), Zhou (US 2019/0172954) and Yamazaki (US 2013/0009219) as applied to claim 1, and further in view of Yamazaki et al. (US 2021/0151569, hereinafter Yamazaki’569).
Regarding claim 4, Vellianitis in view of Baeck, Hong, Zhou, and Yamazaki discloses the thin film transistor of claim 1. Further, Vellianitis does not specifically disclose that the thin film transistor has an electron mobility of 60 cm2/Vs or more.
However, Yamazaki’569 teaches forming a thin film transistor (Yamazaki’569, ¶0007, ¶0018, ¶0165-¶0168, ¶0183-¶0198) comprising an oxide semiconductor with controlled content of indium to provide improved field effect mobility and reliability, wherein an electron mobility is between 100 cm2/Vs and 200 cm2/Vs. Specifically, the oxide semiconductor is formed by sputtering or atomic layer deposition (ALD) (Yamazaki’569, ¶0183-¶0198, ¶0221) at specific temperature of the substrate that influences the electrical properties of the oxide semiconductor.
Further, it is well-known in the art of oxide semiconductor transistor (e.g., as evidenced by Hanaoka, ¶0148) that in an oxide semiconductor, the s orbital of heavy metal mainly contributes to carrier transfer, and when the proportion of In in the oxide semiconductor is increased, overlap of the s orbitals is likely to be increased. Thus, an oxide having a composition in which the proportion of In is higher than that of Ga has higher mobility than an oxide having a composition in which the proportion of In is equal to or lower than that of Ga.
Thus, Yamazaki’569 recognizes that the concentrations of indium and temperature of the substrate impact electron mobility of the oxide semiconductor layer. Further, Hanaoka recognizes that proportion of In with respect to Ga in oxide composition impact carrier mobility. Thus, the concentrations of indium and temperature of the substrate are result-effective variables.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to vary, through routine optimization, the concentrations of indium and temperature of the substrate, and specifically proportion of In with respect to Ga as Yamazaki’569 and Hanaoka have identified the concentrations of indium and temperature of the substrate as result-effective variables. Further, a person of ordinary skill in the art would have had a reasonable expectation of success to arrive at an electron mobility of 60 cm2/Vs or more, in order to provide improved field effect mobility and reliability as taught by Yamazaki’569 (¶0007, ¶0018, ¶0165-¶0168, ¶0183-¶0198), and evidenced by Hanaoka (¶0148) (MPEP 2144.05).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the thin film transistor of Vellianitis/Baeck/Hong/Zhou/ Yamazaki by optimizing the concentrations of indium and temperature of the substrate as taught by Yamazaki’569, and proportion of In with respect to Ga (as evidenced by Hanaoka) to have the thin film transistor, wherein the thin film transistor has an electron mobility of 60 cm2/Vs or more, in order to provide improved field effect mobility and reliability (Yamazaki’569, ¶0007, ¶0018, ¶0165-¶0168, ¶0183-¶0198; Hanaoka, ¶0148).
Claims 7 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over US 2021/0376089 to Vellianitis in view of Baeck (US 2020/0176603), Hong (US Patent 9,171,960), Zhou (US 2019/0172954), and Yamazaki (US 2013/0009219) as applied to claim 6, and further in view of Hong (US Patent No. 9,171,960).
Regarding claim 7, Vellianitis in view of Baeck, Hong, Zhou, and Yamazaki discloses the method of claim 6. Further, Vellianitis does not specifically disclose the method, wherein a temperature of the substrate is maintained in a range of 200°C to 300°C during the process of the ALD.
However, Hong teaches forming an oxide semiconductor TFT (Hong, Fig. 6, Col. 1, lines 7-9; Col. 4, lines 53-67; Col. Col. 5, lines 23-35; Col. 10, lines 31-43; Col. 14, lines 153; Col. 15, lines 24-54; Col. 16, lines 22-26; Col. 17, lines 32-67; Col. 18, lines 17-67; Col. 19, lines 1-20) comprising an oxide semiconductor layer by atomic layer deposition (ALD) to precisely control composition and stoichiometry to produce a high mobility region near interface between the semiconductor layer and the gate insulator and highly stable region near the back of the channel surface. The temperature of the substrate is maintained in a range of 20°C to 600°C (Hong, Fig. 6, Col. 13, lines 29-46) during the process of the ALD, specifically, ALD processing temperature for a glass substrate is below 480°C to avoid high temperature related problems that can adversely impact underlying layers or the substrate.
The claimed rnage lies inside the range of Hong. In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists (M.P.E.P. §2144.05).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the method of Vellianitis/Baeck/Hong/Zhou/Yamazaki by forming an oxide semiconductor layer by ALD process at specific temperature as taught by Hong to have the method, wherein a temperature of the substrate is maintained in a range of 200°C to 300°C during the process of the ALD, in order to avoid high temperature related problems that can adversely impact underlying layers or the substrate, and to provide oxide semiconductor layer with high electron mobility to increase electric characteristics of TFT (Hong, Col. 1, lines 7-9; Col. 4, lines 53-67; Col. 5, lines 23-35; Col. 13, lines 43-46; Col. 16, lines 22-26; Col. 18, lines 17-67; Col. 19, lines 1-20).
Regarding claim 8, Vellianitis in view of Baeck, Hong, Zhou, and Yamazaki discloses the method of claim 6. Further, Vellianitis does not specifically disclose the method, wherein during the process of the ALD, an inflow rate of at least one of an indium source, a gallium source, and a zinc source is adjusted to control a composition and thickness of the oxide semiconductor layer to be manufactured.
However, Hong teaches forming an oxide semiconductor TFT (Hong, Fig. 6, Col. 1, lines 7-9; Col. 4, lines 53-67; Col. Col. 5, lines 23-35; Col. 10, lines 31-43; Col. 14, lines 153; Col. 15, lines 24-54; Col. 16, lines 22-26; Col. 17, lines 32-67; Col. 18, lines 17-67; Col. 19, lines 1-20) comprising an oxide semiconductor layer by atomic layer deposition (ALD) to precisely control composition and stoichiometry to produce a high mobility region near interface between the semiconductor layer and the gate insulator and highly stable region near the back of the channel surface. The oxide semiconductor layer includes several sequences of at least two metal oxides to form indium gallium oxide (IGO), indium zinc oxide (IZO), or indium gallium zinc oxide (IGZO) (Hong, Fig. 6, Col. 16, lines 22-26; Col. 17, lines 32-67; Col. 18, lines 17-67; Col. 19, lines 1-20), wherein the precursors of the at least two metal oxides alternately pulsed into reaction chamber with little to no overlap to form a film of suitable thickness and composition (Hong, Fig. 6, Col. 13, lines 29-67; Col. 14, lines 1-53; Col. 15, lines 26-67; Col. 16, lines 1-60; Col. 17, lines 32-67; Col. 18, lines 17-67; Col. 19, lines 1-20), wherein the first metal oxide includes gallium oxide at the concentration of about 20% at the lower surface and about 80% at the upper surface, and indium oxide at the concentration of about 80% at the lower surface and about 20% at the upper surface the second metal oxide includes indium oxide. A region of high electron mobility is formed at the lower surface with about 20% of gallium oxide and about 80% of indium oxide to increase electric characteristics of the TFT device.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the method of Vellianitis/Baeck/Hong/Zhou/Yamazaki by forming an oxide semiconductor layer by ALD process by alternately pulsed the precursors of the at least two metal oxides as taught by Hong to have the method, wherein during the process of the ALD, an inflow rate of at least one of an indium source, a gallium source, and a zinc source is adjusted to control a composition and thickness of the oxide semiconductor layer to be manufactured, in order to provide oxide semiconductor layer with high electron mobility region and highly stable region to obtain oxide semiconductor TFT with improved electrical characteristics (Hong, Col. 1, lines 7-9; Col. 4, lines 53-67; Col. 5, lines 23-35; Col. 13, lines 43-67; Col. 16, lines 22-26; Col. 18, lines 17-67; Col. 19, lines 1-20).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over US 2021/0376089 to Vellianitis in view of Baeck (US 2020/0176603), Hong (US Patent 9,171,960), Zhou (US 2019/0172954), and Yamazaki (US 2013/0009219) as applied to claim 6, and further in view of Ohnuki (US 2012/0286871) and Hong (US Patent No. 9,171,960).
Regarding claim 9, Vellianitis in view of Baeck, Hong, Zhou, and Yamazaki discloses the method of claim 6. Further, Vellianitis does not specifically disclose the method, further comprising: performing post-processing at a temperature of 300°C to 500°C after the process of the ALD.
However, Ohnuki teaches performing a heat treatment (Ohnuki, ¶0218-¶0227) of the formed oxide semiconductor layer to increase the ratio of the crystal regions to the amorphous portion to provide oxide semiconductor transistor having stable electric characteristics, wherein the heat treatment is performed at the temperature higher than 200°C or higher than 400°C and lower than a temperature at which the semiconductor substrate is changed in quality or deformed.
Further, Hong teaches that the ALD processing temperature for a glass substrate is below 480°C to avoid high temperature related problems that can adversely impact underlying layers or the substrate (Hong, Fig. 6, Col. 13, lines 29-46).
The claimed rnage overlaps the range of Ohnuki. In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists (M.P.E.P. §2144.05).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the method of Vellianitis/Baeck/Hong/Zhou/Yamazaki by performing a heat treatment process on the oxide semiconductor layer at specific temperature as taught by Ohnuki, wherein the temperature is selected for the specific substrate material as taught by Ohnuki and Hong to have the method, further comprising: performing post-processing at a temperature of 300°C to 500°C after the process of the ALD, in order to increase the ratio of the crystal regions to the amorphous portion to provide oxide semiconductor transistor having stable electric characteristics, and to avoid high temperature related problems that can adversely impact underlying layers or the substrate (Ohnuki, ¶0218-¶0227; Hong, Col. 1, lines 7-9; Col. 4, lines 53-67; Col. 5, lines 23-35; Col. 13, lines 43-46; Col. 16, lines 22-26; Col. 18, lines 17-67; Col. 19, lines 1-20).
Response to Arguments
Applicant's arguments filed 01/13/2026 have been fully considered but they are not persuasive.
In response to Applicant's argument that “[b]andgap value decreases as the fraction of In increases and that a bandgap value increases as the thickness of the ZnO layer becomes thinner, it was confirmed that, when the ratio of In is increased while adjusting the thickness of the ZnO layer to 1.5 to 3 nm so as to enlarge a bandgap difference between the IGO layer and the ZnO layer, electron transfer from the ZnO layer to the IGO layer can be effectively enhanced”, the examiner submits that newly discovered prior art by Yamazaki teaches forming a thin film transistor (Yamazaki, Figs. 1A-1B, ¶0008-¶0009, ¶0012, ¶0022-¶0023, ¶0078, ¶0089-¶0091, ¶0128- ¶0130) comprising stacked oxide semiconductor layers (101/102) having different energy gaps to provide increased on-state characteristics (e.g., on-state current and field-effect mobility) for a higher performance semiconductor device by adjusting electric characteristics of the transistor. The stacked oxide semiconductor layers having different energy gaps comprise oxide semiconductor materials including one-component metal oxide (e.g., zinc oxide (Zn-O)) and two-component metal oxide (e.g., In-Ga-based oxide), wherein a thickness of an oxide semiconductor layer (Yamazaki, Figs. 1A-1B, ¶0089-¶0091, ¶0128-¶0130) is equal to 1 nm that is in the claimed thickness range of the second oxide semiconductor layer.
In response to Applicant's argument against the references individually that “[V]ellianitis and Baeck do not disclose at all the feature in which x in In1-xGaxO1.5 is adjusted to 0.3 or less, or the effects achieved thereby. Further, Zhou, Ohnuki and Yamazaki also fail to disclose the feature of using In1-xGaxO1.5 with x being 0.3 or less as a first oxide semiconductor layer to greatly improve transfer characteristics and stability. In addition, Hong merely discloses a concentration change of gallium oxide on an upper or lower surface of an oxide semiconductor layer including IGZO, and does not disclose at all that x in In1-xGaxO1.5 can be adjusted to 0.3 or less. Further, Vellianitis merely discloses that a binary oxide material layer may have a thickness of approximately 5 nm or less (see para. [0024] of Vellianitis), and Hong merely discloses that the thickness of an oxide semiconductor layer may be less than about 100 A (i.e., 10 nm) (see para. [0028] of Hong), but neither Vellianitis nor Hong recognizes any change in electron mobility depending on the thickness of the binary oxide material layer”, the examiner submits that one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references.
In the instance case, it would be within ordinary skill in the art to optimize the compositions and thicknesses of the stacked oxide semiconductor layers having different energy gaps to have the claimed thickness of the second oxide semiconductor layer and the composition of the first oxide semiconductor layer, in order to have increased on-state characteristics (e.g., on-state current and field-effect mobility) for a higher performance semiconductor device.
Also, in response to applicant's argument that the references fail to show certain features of the invention (e.g., “using In1-xGaxO1.5 with x being 0.3 or less as a first oxide semiconductor layer to greatly improve transfer characteristics and stability”, and “any change in electron mobility depending on the thickness of the binary oxide material layer”), it is noted that the features upon which applicant relies (i.e., “to greatly improve transfer characteristics and stability” and “change in electron mobility depending on the thickness of the binary oxide material layer”) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
Thus, the above applicant’s arguments are not persuasive, and the rejection of claim 1 (claim 5) under 35 USC 103 is maintained.
Regarding dependent claims 4 and 6-10 which depend on the independent claims 1 and 5, the examiner respectfully submits that the applicant’s arguments with respect to dependent claims are not persuasive for the above reasons, thus, the rejections of the dependent claims are sustained.
Conclusion
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/NATALIA A GONDARENKO/Primary Examiner, Art Unit 2891