DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Species A (FIG. 2a), with claims 1-4, 6, 8-9, 11-15, 17-18, 20 and 22-26 thereon, in the reply filed on 02/02/2026, is acknowledged. The traversal is not found persuasive.
Applicant contends that Species A-C share a common distinguishing technical feature recited in claim 1 and that a single search can cover all species. However, Applicant has not distinctly and specifically pointed out the supposed errors in the restriction requirement as required by MPEP § 818.01(a). The fact that all three species fall within the scope of generic claim 1 does not establish that they are obvious variants of each other. See MPEP § 806.04(f). Species A (FIG. 2a), B (FIG. 2b), and C (FIG. 2c) each comprise a distinct structural arrangement of the display regions, requiring different fields of search and likely raising different prior art issues.
Accordingly, claims 1-4, 6, 8-9, 11-15, 17-18, 20, and 22-26 have been fully considered in examination.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-4, 6, 8-9, 11-15, 17-18, 20, and 22-26 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
In In claim 1, the scope of "at least partially surrounding" is unclear. The claim does not define the minimum degree of surrounding required for the first display region to "at least partially surround" the second display region, and for the second display region to "at least partially surround" the third display region.
In claim 4, the scope of "approximately equal value" is unclear. The claim provides no numerical range or tolerance for the permissible deviation among ΔS values, and the specification at paragraph [0097] provides only a circular definition based on what a person of ordinary skill in the art would consider acceptable.
Claims 2-4, 6, 8-9, 11-15, 17-18, 20, and 22-26 are also rejected being dependent on rejected claim 1.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 6, 8-9, 11-15, 17-18, 20, and 22-26 are rejected under 35 U.S.C. 103 as being unpatentable over Hu (CN112151591A), and further in view of Youn (US11737322B2).
Regarding claim 1, Hu teaches a display panel having a first display region, at least one second display region and a third display region (a display panel comprising a first display area 11, a second display area 12, and a third display area 13, wherein the third display area is a normal display area and the first display area is located around the camera, paragraphs [0031]-[0035]); the at least one second display region being located between the first display region and the third display region (the second display area 12 is located between the first display area 11 and the third display area 13, paragraph [0033]); the first display region at least partially surrounding the at least one second display region, and the at least one second display region at least partially surrounding the third display region (the third display area 13 surrounds the second display area 12, and the second display area 12 surrounds the first display area 11, as shown in Figs. 3-4, paragraph [0034]);
wherein the first display region, the at least one second display region and the third display region are each provided with openings of the plurality of openings, and aperture ratios of the first display region, the at least one second display region and the third display region sequentially decrease (a plurality of display pixels Pix are distributed in each of the first display area, the second display area, and the third display area; the aperture ratios of the display pixels in the second display area gradually increase in the direction from the first display area toward the third display area, thereby establishing that aperture ratios sequentially decrease from the third display area toward the first display area, thereby establishing that aperture ratios sequentially decrease from the third display area toward the first display area, i.e., from the first display region toward the third display region of claim 1, paragraphs [0036]-[0042]).
Hu does not explicitly teach a substrate, an anode layer disposed on the substrate including a plurality of anodes, and a pixel definition layer disposed on a side of the anode layer away from the substrate, the pixel definition layer being provided with a plurality of openings therein, an opening corresponding to an anode, and the opening exposing at least a portion of the anode corresponding thereto.
However, Youn teaches the display panel (display panel 10, Figs. 3-5) comprising:
a substrate (base substrate 100);
an anode layer disposed on the substrate including a plurality of anodes (anode electrode AE disposed on the substrate corresponding to each sub-pixel, Figs. 3-5, paragraph [0051]); and
a pixel definition layer disposed on a side of the anode layer away from the substrate, the pixel definition layer being provided with a plurality of openings therein, an opening corresponding to an anode, and the opening exposing at least a portion of the anode corresponding thereto (pixel defining layer PDL disposed on a side of the anode electrode away from the substrate, the pixel defining layer having an opening OP corresponding to the anode electrode and exposing at least a portion of the anode electrode, Figs. 3-5, paragraphs [0056]-[0058]).
It would have been obvious to a person having ordinary skill in the art to implement the display panel of Hu using the substrate, anode layer, and pixel definition layer structure taught by Youn Both references are directed to OLED display panels for under-display camera applications, and a person of ordinary skill in the art would have been motivated to combine the teachings of these references to achieve a fully functional OLED under-display camera panel with improved light transmittance. See KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398 (2007).
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Regarding claim 2, Hu in view of Youn teaches the display panel of claim 1, wherein the display panel comprises a plurality of second display regions that are sequentially nested (Hu, Figs. 3-4, a plurality of second display areas disposed as sequentially nested rings between the first display area and the third display area);
aperture ratios of the plurality of second display regions sequentially decrease in a direction from the first display region to the third display region (Hu, paragraph [0042], the aperture ratios of the display pixels in the plurality of second display areas gradually vary such that aperture ratios sequentially decrease in the direction from the third display area toward the first display area, establishing a sequential decrease from the first display region to the third display region).
Regarding claim 3, Hu in view of Youn teaches the display panel of claim 1, wherein the display panel comprises a plurality of sub-pixels capable of emitting light of a plurality of colors, and the opening is used for defining a light-emitting region of a sub-pixel (Hu, paragraph [0031], display pixels comprising sub-pixels of a plurality of colors; Youn, paragraph [0051], openings in the pixel definition layer defining light-emitting regions of respective sub-pixels);
the plurality of openings of the pixel definition layer include first openings, second openings and third openings, the first openings are disposed in the first display region, the second openings are disposed in the at least one second display region, and the third openings are disposed in the third display region (Hu in view of Youn, openings disposed in each of the first, second, and third display areas corresponding to sub-pixels in those regions);
areas of orthogonal projections, on the substrate, of a first opening, a second opening and a third opening that are corresponding to sub-pixels emitting light of a same color sequentially decrease (Hu, paragraphs [0038]-[0042], areas of the display pixels in the second display area gradually decrease from the third display area toward the first display area; Youn, Figs. 3-5, opening areas corresponding to anodes of respective sub-pixels, establishing that opening areas of same-color sub-pixels sequentially decrease across the three regions).
Regarding claim 4, Hu in view of Youn teaches the display panel of claim 3, wherein the display panel comprises a plurality of second display regions that are sequentially nested; in the second openings disposed in the plurality of second display regions, areas of orthogonal projections, on the substrate, of second openings corresponding to sub-pixels emitting light of a same color sequentially decrease in a direction from the first display region to the third display region (Hu, paragraphs [0038]-[0042], areas of display pixels in the plurality of nested second display areas gradually decrease in the direction from the third display area toward the first display area, establishing sequential decrease of same-color opening areas across nested second display regions); and/or
in a plurality of display regions consisting of the first display region and the third display region, a difference between areas of orthogonal projections, on the substrate, of openings that are respectively located in every two adjacent display regions and correspond to sub-pixels emitting light of a same color is ΔS, and each ΔS has an approximately equal value (Hu does not explicitly teach equal ΔS values between adjacent regions).
Hu does not teach that each ΔS has an approximately equal value.
However, it would have been obvious to a person having ordinary skill in the art to design equal ΔS values, as uniform step sizes are a routine design choice for achieving smooth luminance transitions. See In re Aller, 220 F.2d 454 (CCPA 1955).
Regarding claim 6, Hu in view of Youn teaches the display panel of claim 1, wherein a distribution density of the openings in the first display region, a distribution density of the openings in the at least one second display region and a distribution density of the openings in the third display region sequentially decrease (Hu, paragraph [0036], the pixel density of the display pixels in the second display area gradually decreases in the first direction, establishing that distribution densities of the openings sequentially decrease from the third display area toward the first display area); and/or
the display panel comprises a plurality of second display regions that are sequentially nested, distribution densities of openings respectively disposed in the plurality of second display regions sequentially decrease in a direction from the first display region to the third display region (Hu, Figs. 3-4, sequentially nested second display areas with gradually decreasing pixel density toward the first display area).
Regarding claim 8, Hu in view of Youn teaches the display panel of claim 1, further comprising a plurality of pixel circuits disposed between the substrate and the anode layer, a pixel circuit being electrically connected to at least one anode (Youn, Figs. 3-5, pixel circuits disposed between the substrate and the anode layer, each pixel circuit electrically connected to at least one anode via a connection electrode); the plurality of pixel circuits including first pixel circuits, second pixel circuits and third pixel circuits; the first pixel circuits being each electrically connected to at least one anode disposed in the first display region, the second pixel circuits being each electrically connected to anode disposed in the at least one second display region, and the third pixel circuits being each electrically connected to anodes disposed in the third display region (Youn, first circuit units electrically connected to first anodes in the normal display area, and second circuit units electrically connected to second anodes in the transition region, paragraphs [0045]-[0060]);
wherein the at least one second display region includes a setting second display region, a second pixel circuit electrically connected to anodes disposed in the setting second display region is a setting second pixel circuit; a number of the anodes electrically connected to the setting second pixel circuit is greater than a number of anodes electrically connected to a first pixel circuit, and is less than a number of anodes electrically connected to a third pixel circuit (Hu and Youn do not explicitly teach this three-level anode-count hierarchy for pixel circuits across the three regions).
Hu and Youn do not explicitly teach that the number of anodes connected to the setting second pixel circuit is greater than that of the first pixel circuit and less than that of the third pixel circuit.
However, it would have been obvious to a person having ordinary skill in the art to implement a graduated anode-per-circuit hierarchy across the three display regions, as such an arrangement predictably reduces metal wiring density in the camera region and thereby increases light transmittance, consistent with the design goals of both references. See KSR, 550 U.S. 398.
Regarding claim 9, Hu in view of Youn teaches the display panel of claim 8, wherein the first pixel circuit is electrically connected to one anode, the setting second pixel circuit is electrically connected to two or three anodes, and the third pixel circuit is electrically connected to at least three anodes (Youn, paragraph [0055], first-type pixel circuits each connected to one first anode, and second-type pixel circuits each connected to a plurality of second anodes, establishing a graduated anode-per-circuit structure across the display regions); and/or
the at least one second display region further includes a general second display region, the general second display region is located between the first display region and the setting second display region, a second pixel circuit electrically connected to at least one anode disposed in the general second display region is a general second pixel circuit, a number of anodes electrically connected to the general second pixel circuit is equal to the number of anodes electrically connected to the first pixel circuit (Youn, paragraph [0055], first-type pixel circuits in the general second display region connected to the same number of anodes as the first pixel circuits in the first display region).
Regarding claim 11, Hu in view of Youn teaches the display panel of claim 8, wherein the display panel comprises a plurality of sub-pixels capable of emitting light of a plurality of colors, a sub-pixel includes a single anode; sub-pixels to which the anodes electrically connected to the setting second pixel circuit respectively belong emit light of a same color; and/or
sub-pixels to which the anodes electrically connected to the third pixel circuit respectively belong emit light of a same color (Youn, paragraph [0057], anodes connected to the same pixel circuit correspond to sub-pixels of the same color, ensuring color uniformity in the transition and camera regions).
Regarding claim 12, Hu in view of Youn teaches the display panel of claim 11, wherein the setting second pixel circuit is electrically connected to two anodes respectively included in two sub-pixels that are adjacent in a first direction and emit the light of the same color (Youn, Figs. 6-9, setting second pixel circuit connected to two same-color anodes adjacent in the row direction);
the third pixel circuit is electrically connected to four anodes respectively included in four sub-pixels that are adjacent and emit the light of the same color, and the four anodes are arranged in two columns in the first direction, and are arranged in two rows in a second direction (Youn, Figs. 6-9, third pixel circuit connected to four same-color anodes arranged in a 2×2 configuration);
wherein the first direction is perpendicular to the second direction (Youn, Figs. 6-9, row and column directions are perpendicular).
Regarding claim 13, Hu in view of Youn teaches the display panel of claim 1, wherein the display panel comprises a plurality of second display regions that are sequentially nested;
the display panel further comprises a plurality of pixel circuits that are disposed between the substrate and the anode layer;
the plurality of pixel circuits are disposed in the first display region; or
the plurality of pixel circuits are disposed in the first display region and at least one second display region of the plurality of second display regions;
wherein at least one second display region of the plurality of second display regions provided with pixel circuits is closer to the first display region than another at least one second display region of the plurality of second display regions provided with no pixel circuit (Youn, Figs. 3-5, pixel circuits disposed in the normal display area and the portion of the transition area closer to the normal display area, while the portion closer to the camera area contains no pixel circuits, establishing that the second display region with pixel circuits is closer to the first display region).
Regarding claim 14, Hu in view of Youn teaches the display panel of claim 13, wherein in a plurality of display regions consisting of the first display region, the at least one second display region and the third display region, a display region provided with pixel circuits of the plurality of pixel circuits is a first transmittance region, and a display region provided with no pixel circuit is a second transmittance region (Youn, Figs. 3-5, display regions with pixel circuits constitute the first transmittance region; regions without pixel circuits constitute the second transmittance region);
the display panel further comprises:
at least one connection layer disposed between the plurality of pixel circuits and the anode layer, the at least one connection layer including a plurality of first connection patterns and a plurality of first connection lines (Youn, Figs. 6-9, at least one connection layer disposed between pixel circuits and the anode layer, comprising connection patterns and connection lines);
wherein the plurality of anodes include a plurality of first anodes and a plurality of second anodes, the plurality of first anodes are disposed in the first transmittance region, and the plurality of second anodes are disposed in the second transmittance region; a first anode is electrically connected to a respective pixel circuit via at least one first connection pattern, and a second anode is electrically connected to a respective pixel circuit via at least one first connection line (Youn, Figs. 6-9, first anodes in the first transmittance region connected to pixel circuits via connection patterns, and second anodes in the second transmittance region connected to pixel circuits via connection lines extending from the first transmittance region, paragraphs [0062]-[0070]).
Regarding claim 15, Hu in view of Youn teaches the display panel of claim 14, wherein the display panel comprises a plurality of connection layers; the first anode is electrically connected to the respective pixel circuit via first connection patterns of the plurality of first connection patterns, and the first connection patterns of the plurality of first connection patterns are respectively located in the plurality of connection layers; orthographic projections, on the substrate, of any two adjacent first connection patterns, that are adjacent in a direction parallel to a thickness direction of the substrate, of the first connection patterns of the plurality of first connection patterns at least partially overlap (Youn, Figs. 8-9, plurality of connection layers wherein adjacent first connection patterns in different layers have orthographic projections that at least partially overlap on the substrate); and/or
the at least one connection layer includes a first connection layer and a second connection layer, and the first connection layer is farther away from the substrate than the second connection layer; the first connection line used for being electrically connected to the second anode and the respective pixel circuit is located in the first connection layer; and the second connection layer includes a second connection pattern, and the first connection line is electrically connected to the respective pixel circuit via the second connection pattern (Youn, Figs. 8-9, first connection layer farther from the substrate containing the first connection lines for second anodes, and second connection layer containing second connection patterns through which the first connection lines connect to the pixel circuits, paragraph [0072]).
Regarding claim 17, Hu in view of Youn teaches the display panel of claim 14, wherein each of at least one pixel circuit is electrically connected to at least two anodes of the plurality of anodes;
the at least one connection layer further includes a plurality of second connection lines, at least two anodes electrically connected to a same pixel circuit are electrically connected to each other via at least one second connection line, and one of the at least two anodes electrically connected to the same pixel circuit is electrically connected to a respective pixel circuit via a first connection pattern or a first connection line (Youn, Figs. 9-12, at least two anodes connected to the same pixel circuit are interconnected via second connection lines, and one of the anodes is connected to the pixel circuit via a first connection pattern or first connection line, paragraph [0075]).
Regarding claim 18, Hu in view of Youn teaches the display panel of claim 17, wherein the at least one connection layer further includes at least two third connection patterns, and the at least two anodes electrically connected to the same pixel circuit are electrically connected to the at least two third connection patterns, respectively; the second connection line used for being electrically connected to the at least two anodes is disposed in a same connection layer as the at least two third connection patterns, and is electrically connected to the at least two third connection patterns (Youn, Figs. 10-12, third connection patterns and second connection lines disposed in the same connection layer, with the second connection lines electrically connected to the third connection patterns, paragraph [0078]); and/or
the display panel comprises a plurality of connection layers, and the plurality of first connection lines and the plurality of second connection lines are located in different connection layers (Youn, Figs. 10-12, first connection lines and second connection lines located in different connection layers, paragraph [0079]).
Regarding claim 20, Hu in view of Youn teaches the display panel of claim 14, wherein the plurality of pixel circuits include a plurality of circuit units, and a circuit unit includes a plurality of first-type pixel circuits and a second-type pixel circuit that are sequentially arranged in a second direction; a first-type pixel circuit is electrically connected to at least one first anode, and the second-type pixel circuit is electrically connected to second anodes of the plurality of second anodes (Youn, Figs. 6-9, circuit units each comprising a plurality of first-type pixel circuits connected to first anodes and a second-type pixel circuit connected to second anodes, arranged sequentially in the column direction, paragraph [0055]); or
the plurality of pixel circuits include a plurality of circuit units, a circuit unit includes a plurality of first-type pixel circuits and a second-type pixel circuit that are sequentially arranged in a second direction, a first-type pixel circuit is electrically connected to at least one first anode, and the second-type pixel circuit is electrically connected to second anodes of the plurality of second anodes; the display panel further comprises a second initialization signal line and a third initialization signal line, wherein
in the circuit unit, the plurality of first-type pixel circuits are electrically connected to the second initialization signal line, and the second-type pixel circuit is electrically connected to the third initialization signal line (Youn, Figs. 13-16, first-type pixel circuits connected to the second initialization signal line and the second-type pixel circuit connected to a separate third initialization signal line within each circuit unit, paragraph [0085]).
Regarding claim 22, Hu in view of Youn teaches the display panel of claim 3, wherein orthogonal projections, on the substrate, of the first openings are each in a shape of a polygon; orthogonal projections, on the substrate, of the second openings are each in a shape of a polygon, a circle or an ellipse; orthogonal projections, on the substrate, of the third openings are each in a shape of a circle or an ellipse (Hu, Figs. 4-6, sub-pixel openings in the normal display area are polygonal, openings in the transition area transition from polygonal to circular or elliptical shapes, and openings in the camera area are circular or elliptical to minimize diffraction effects on the camera, paragraph [0045]).
Regarding claim 23, Hu in view of Youn teaches the display panel of claim 4, wherein the display panel comprises two second display regions that are nested (Hu, Figs. 3-4, a display panel comprising two sequentially nested second area disposed between the first display area and the third display area);
in openings corresponding to the sub-pixels emitting the light of the same color, a ratio of areas of the first opening, a second opening disposed in a second display region closer to the first display region, a second opening disposed in a second display region farther away from the first display region, and the third opening is in a range from 1:0.8:0.6:0.5 to 1:0.9:0.8:0.5 (Hu. Figs. 3-4, the areas of the display pixels in the two nested second display areas gradually decrease in a stepwise manner from the third display area toward the first display area, which corresponds to a sequential decrease from the first display region toward the third display region as recited in claim 1, establishing a four-level sequential decrease in opening areas across the two nested second display regions).
But, Hu does not explicitly teach that the area ratio falls within the range of 1:0.8:0.6:0.5 to 1:0.9:0.8:0.5.
However, it would have been obvious to a person having ordinary skill in the art to optimize the opening area ratios to fall within this range, as selecting specific numerical values for smooth luminance transitions involves only routine experimentation. See In re Aller, 220 F.2d 454 (CCPA 1955).
Regarding claim 24, Hu in view of Youn teaches the display panel of claim 1, further comprising a pixel circuit layer disposed between the substrate and the anode layer, wherein the pixel circuit layer includes an active layer, a first gate conductive layer and a second gate conductive layer that are arranged in sequence in a third direction; the third direction is parallel to a thickness direction of the substrate, and is from the substrate to the anode layer (Youn, Figs. 3-5, pixel circuit layer comprising an active layer, first gate conductive layer, and second gate conductive layer sequentially arranged in the thickness direction from the substrate toward the anode layer, paragraph [0042]);
the pixel circuit layer includes a plurality of pixel circuits, at least one pixel circuit includes a compensation transistor; the compensation transistor includes a semiconductor pattern disposed in the active layer and two gates disposed in the first gate conductive layer (Youn, Figs. 3-5, compensation transistor comprising a semiconductor pattern in the active layer and two gates in the first gate conductive layer, paragraph [0044]); the semiconductor pattern includes first portions and a second portion, orthographic projections of the first portions on the substrate overlap with orthographic projections of the two gates of the compensation transistor on the substrate, respectively; an orthographic projection of the second portion on the substrate is located between the orthographic projections of the two gates of the compensation transistor on the substrate (Youn, Figs. 3-5, semiconductor pattern having first portions overlapping with the two gates and a second portion located between the two gates in orthographic projection, paragraph [0044]); and
the second gate conductive layer includes a first initialization signal line, a light shielding pattern and a connection portion; the connection portion is connected to the first initialization signal line and the light shielding pattern, and an orthographic projection of the light shielding pattern on the substrate overlaps with the orthographic projection of the second portion of the semiconductor pattern on the substrate (Youn, Figs. 3-5, second gate conductive layer comprising a first initialization signal line, a light shielding pattern overlapping the second portion of the semiconductor pattern, and a connection portion connecting the two, paragraph [0046]).
Regarding claim 25, Hu in view of Youn teaches the display panel of claim 24, wherein the pixel circuit further includes a first reset transistor, and the first reset transistor includes two gates disposed in the first gate conductive layer (Youn, Figs. 3-5, first reset transistor comprising two gates in the first gate conductive layer, paragraph [0048]);
each of at least one anode includes a main body portion, and two protruding portions respectively located on two sides of the main body portion in a second direction; an orthographic projection of the main body portion on the substrate is located between orthographic projections of first reset transistors of two pixel circuits arranged in the second direction on the substrate (Youn, Figs. 6-9, anode main body portion positioned between the first reset transistors of adjacent pixel circuits in orthographic projection, paragraph [0062]); in the protruding portion and the first reset transistor that are located on a same side of the main body portion, an orthographic projection of the protruding portion on the substrate at least partially overlaps with orthographic projections of the two gates of the first reset transistor on the substrate (Youn, Figs. 6-9, protruding portions of the anode overlapping with the two gates of the first reset transistor in orthographic projection on the substrate, paragraph [0063]).
Regarding claim 26, Hu in view of Youn teaches the display apparatus of claim 26 for the same reasons set forth above with respect to claim 1.
Conclusion
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/FERNANDO L TOLEDO/Supervisory Patent Examiner, Art Unit 2897
/JAHAE KIM/Examiner, Art Unit 2897
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