Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 1/30/2026 has been entered.
Response to Arguments
Applicant's arguments directed to the newly amended claims filed January 30, 2026, have been fully considered but they are not persuasive.
The rejection of claims 1 and 3–6 under 35 U.S.C. § 103 is maintained for the following reasons:1. The "Storage Node" Limitation is Inherently Disclosed
The Applicant argues that the "undercut" in Lee et al. is located in an "element isolation region," whereas the claimed "overhang" is specifically positioned at a lower part of a storage node. However, the physical structure in Lee et al. demonstrates that the two locations are one and the same:
Lee et al. discloses a buried gate electrode (word line WL) disposed in a trench.
This gate structure is physically positioned beneath a buried contact (BC) and a landing pad (LP), which connect the active region to a lower electrode 171 of a capacitor.
In the semiconductor art, the combination of the lower electrode, dielectric, and upper electrode (171, 172, 173) constitutes the storage node.
Because Lee et al. discloses a word line trench with an expanded width (undercut) situated physically below these storage components, the structural limitation of an overhang "positioned at a lower part of a storage node" is inherently present in the prior art. The fact that Lee et al. may not explicitly label the region for "shielding" is not relevant, as the physical structure would non the less provide that result, as like structures are anticipated to hare like results1
2. "Passing Word Line" vs. "Gate Line" is a Design Choice
The Applicant further argues that Lee et al. focuses on "gate formation" rather than a "passing word line".
This distinction is not persuasive because a "passing word line" is structurally identical to an active "word line" or "gate electrode" in the context of a buried trench. Lee et al. explicitly identifies the buried gate electrodes (130) as word lines (WL). In the layout of a standard DRAM cell, some word lines will naturally "pass" through unit cells without acting as a gate for that specific cell. It would have been obvious to a Person of Ordinary Skill in the Art (POSITA) to apply the etching techniques of Lee et al. to any buried word line in the array to achieve the predictable structural benefits of improved insulation and width.
3. Functional Limitations and Intended Use
The Applicant relies on the intended purpose of "suppressing electric-field and coupling effects". Under established patent law, the patentability of an apparatus or method is determined by its physical structure, not by its intended use or the "intent" of the inventor. Since Lee et al. discloses the same multi-step etching process to create a widened trench base (undercut/overhang) at the same physical level in a DRAM cell, the claimed invention is rendered at least obvious.
The addition of the "lower part of a storage node" limitation to Claim 1 does not distinguish the invention from Lee et al., as the storage components in Lee et al. are located in the same spatial relationship to the trench. The rejection is maintained.
Prior Art of Record
The applicant's attention is directed to additional pertinent prior art cited in the accompanying PTO-892 Notice of References Cited, which, however, may not be currently applied as a basis for the following rejections. While these references were considered during the examination of this application and are deemed relevant to the claimed subject matter, they are not presently being applied as a basis for rejection in this Office action. The pertinence of these documents, however, may be revisited, and they may be applied in subsequent Office actions, particularly in light of any amendments or further clarification of the claimed invention.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s)1, 3-6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 20210257374 A1).
CLAIM 1. Lee et al. disclose a manufacturing method of a semiconductor device, the method comprising: preparing a substrate on which a unit cell is formed; forming a mask M for forming a passing word-line on the substrate (Lee et al. Fig. 24 – Note: The term "passing wordline" in the claim is ambiguous. "Passing" may merely describe an intended function or standard operation of a typical wordline during normal use, failing to provide a clear structural distinction. In some DRAM architectures, an adjacent, unselected wordline might function simply as a bypass path for active circuits.
However, based on the applicant's remarks filed on 11/17/2025, the claimed "passing wordline" is defined by a specific physical structure: an "overhang within a trench structure." This unique configuration is created by two specific etching steps and subsequently filled with an insulating material where the wordline is positioned.
As addressed below, Lee et al. discloses an analogous structure. That prior art reference performs similar steps to form a comparable opening in a substrate and provides a dielectric material to insulate a wordline within the opening, which also has an analogous overhang (Lee et al. Figs. 13, 24, 33 & 34). Thus, Lee et al. teaches the specific structure intended to be defined by the applicant's filed remarks.);
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performing a first etching for a vertical trench T1, which is deeper than a lower end of the unit cell (e.g. wodline 130 in fig. 13 not withing trench.), to be formed at the substrate on which the mask M is formed (Lee et al. Fig. 24);
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performing a second etching T3 so as to have an overhang structure at a lower end area of the vertical trench (Lee et al. Fig. 33);
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forming an insulation layer at the trench with the overhang structure (Lee et al. Fig. 34 – 110 & Fig. 13 – 510 – Note: Figs 24-34 demonstrate the method of forming the structure as shown in Fig. 13.); and
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forming a passing word-line (PWL) by filling a conductive material in the trench such that the insulation layer is between the conductive material and the substrate (Lee et al. Fig. 13); and
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wherein the performing the second etching comprises, performing an etching of a side surface area of the vertical trench so that the overhang structure is positioned at a lower part of a storage node [i.e. gate structure is physically positioned beneath a buried contact (BC) and a landing pad (LP), which connect the active region to a lower electrode 171 of a capacitor.] in the unit cell (Lee et al. Fig. 33, 35, & 13).
The device structure shown in Figure 13 of Lee et al. meets the scope of the applicant's definition of a "passing word line." Furthermore, Lee et al. demonstrates means for forming these various structures throughout the document. The overhang structure depicted in Figure 13 is understood to be formed by the process shown in Figures 24-34 and their corresponding text.
As such, a person of ordinary skill in the art (POSITA) at the time of the invention would find it obvious to form the structure of Figure 13 using the standard processing techniques demonstrated within the document, even if not explicitly stated relative to that specific figure. The individual parts having the required shapes would be expected to incorporate the process steps disclosed to form those particular shapes. Therefore, it would be obvious to a POSITA to select these known methods when forming a passing wordline as shown in Figure 13 of Lee et al.
The legal basis for this obviousness rejection is established under MPEP § 2144.04, which permits using established rationales for combining references when the outcome is predictable. Specifically, this case relies on the rationales of "combining prior art elements according to known methods to yield predictable results" and "applying a known technique to a known device." Lee et al. provides both the structure (Figure 13) and the known manufacturing methods (Figures 24-34) separately within the same reference, meaning combining these known steps results in a predictable structure. Applying a known etching and deposition technique from the reference (Figures 24-34) to a known structural goal (the wordline in Figure 13) yields a predictable outcome that is well within the ordinary skill of a Person of Ordinary Skill in the Art (POSITA).
CLAIM 3. Lee et al. disclose a et al. disclose a method of claim 1, wherein the overhang structure has an inclined structure that is extended in width in the unit cell direction from a pre-set center area to a lower end of the vertical trench (Lee et al. Fig. 33, 35, & 13).
CLAIM 4. Lee et al. disclose a method of claim 3, wherein the pre-set center area of the vertical trench is a storage node (SN) junction area (Lee et al. Fig. 33, 35, & 13 Note: This limitation is not understood to provide any further manipulative distinction in the method claim, as it merely describes intended use/operation)..
CLAIM 5. Lee et al. disclose a method of claim 1, wherein the forming the insulation layer comprises, filling the second etched area with an insulation material (Lee et al. Fig. 33, 35, & 13).
CLAIM 6. Lee et al. disclose a method of claim 1, wherein the unit cell is a transistor of a saddle fin structure (Lee et al. Fig. 33, 35, & 13 Note: This limitation is not understood to provide any further manipulative distinction in the method claim, as it merely describes intended use/operation and/or structure).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JARRETT J STARK whose telephone number is (571)272-6005. The examiner can normally be reached 8-4 M-F.
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JARRETT J. STARK
Primary Examiner
Art Unit 2822
2/27/2026
/JARRETT J STARK/Primary Examiner, Art Unit 2898
1 MPEP ¶2112.01 I. “ PRODUCT AND APPARATUS CLAIMS — WHEN THE STRUCTURE RECITED IN THE REFERENCE IS SUBSTANTIALLY IDENTICAL TO THAT OF THE CLAIMS, CLAIMED PROPERTIES OR FUNCTIONS ARE PRESUMED TO BE INHERENT”