Prosecution Insights
Last updated: August 16, 2026
Application No. 18/005,831

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR

Final Rejection §103
Filed
Jan 17, 2023
Priority
Aug 18, 2020 — RE 10-2020-0103025 +1 more
Examiner
STARK, JARRETT J
Art Unit
2898
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Industry-academic Cooperation Foundation Gyeongsang National University
OA Round
4 (Final)
70%
Grant Probability
Favorable
5-6
OA Rounds
0m
Est. Remaining
82%
With Interview

Examiner Intelligence

Grants 70% — above average
70%
Career Allowance Rate
907 granted / 1287 resolved
+2.5% vs TC avg
Moderate +11% lift
Without
With
+11.3%
Interview Lift
resolved cases with interview
Typical timeline
2y 8m
Avg Prosecution
60 currently pending
Career history
1346
Total Applications
across all art units

Statute-Specific Performance

§101
2.7%
-37.3% vs TC avg
§103
62.8%
+22.8% vs TC avg
§102
16.3%
-23.7% vs TC avg
§112
8.8%
-31.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1287 resolved cases

Office Action

§103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Response to Arguments Applicant's arguments directed to the newly amended claims filed 7/1/2026, have been fully considered but they are not persuasive. The rejection of claims 1 and 5–6 under 35 U.S.C. § 103 is maintained for the following reasons: The arguments that the cited reference Lee fails to disclose the claimed "inclined structure" because Lee shows a "square shape" undercut structure are not persuasive. Specifically, Lee explicitly discloses a fabrication process in ¶171 where a "second insulating film 192" is formed along the side walls of a first trench, portions are removed to expose a lower part of the first trench, and the process then involves "etching the exposed side walls and the bottom surface of the first trench to form a second trench [undercut structure T3]". Although Lee does not explicitly use the term "isotropic," this etching behavior is inherently and implicitly understood. Because the "second insulating film 192" acts as a mask covering the upper portion of the trench, a strictly vertical or directional (anisotropic) etch would not remove material laterally beneath the mask. Achieving the lateral expansion of the "exposed side walls" to form the wider "undercut structure" physically requires lateral under-etching, which is a form of isotropic etching. It is a well-established physical reality of semiconductor fabrication that isotropic under-etching beneath a mask boundary cannot produce mathematically perfect, 90-degree "square" corners. As the etchant front propagates laterally and vertically under the second insulating film 192, it inherently produces a rounded, curved transition. This rounded, curved boundary physically and structurally constitutes an "inclined" shape because its non-vertical, sloping profile exhibits a width that continuously and gradually increases along the vertical axis, precisely matching the claimed requirement of an inclined shape whose width is extended to a lower end of the trench. Because a curved transition is mathematically comprised of a continuous series of sloped or inclined tangent vectors, the physical boundary of the rounded under-edge inherently forms the very incline the applicant's claim language requires. PNG media_image1.png 468 468 media_image1.png Greyscale This physical, sloped profile is directly reflected in Lee’s drawings. While some figures schematically illustrate the undercut as block-like, Figures 33 and 34 explicitly illustrate the physical, rounded edges and sloped transitions of the active regions and trench walls during and after the under-etching process. Accordingly, the claimed "inclined structure" is physically inherent in the wet or chemical isotropic etching used to form the "undercut structure" of Lee. The difference is merely one of schematic illustration versus the actual physical profile, which does not patentably distinguish the claimed structure from the prior art. Prior Art of Record The applicant's attention is directed to additional pertinent prior art cited in the accompanying PTO-892 Notice of References Cited, which, however, may not be currently applied as a basis for the following rejections. While these references were considered during the examination of this application and are deemed relevant to the claimed subject matter, they are not presently being applied as a basis for rejection in this Office action. The pertinence of these documents, however, may be revisited, and they may be applied in subsequent Office actions, particularly in light of any amendments or further clarification of the claimed invention. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s)1, 5-6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 20210257374 A1). CLAIM 1. Lee et al. disclose a manufacturing method of a semiconductor device, the method comprising: preparing a substrate on which a unit cell is formed; forming a mask M for forming a passing word-line on the substrate (Lee et al. Fig. 24 – Note: The term "passing wordline" in the claim is ambiguous. "Passing" may merely describe an intended function or standard operation of a typical wordline during normal use, failing to provide a clear structural distinction. In some DRAM architectures, an adjacent, unselected wordline might function simply as a bypass path for active circuits. However, based on the applicant's remarks filed on 11/17/2025, the claimed "passing wordline" is defined by a specific physical structure: an "overhang within a trench structure." This unique configuration is created by two specific etching steps and subsequently filled with an insulating material where the wordline is positioned. As addressed below, Lee et al. discloses an analogous structure. That prior art reference performs similar steps to form a comparable opening in a substrate and provides a dielectric material to insulate a wordline within the opening, which also has an analogous overhang (Lee et al. Figs. 13, 24, 33 & 34). Thus, Lee et al. teaches the specific structure intended to be defined by the applicant's filed remarks.); PNG media_image2.png 693 1071 media_image2.png Greyscale performing a first etching for a vertical trench T1, which is deeper than a lower end of the unit cell (e.g. wodline 130 in fig. 13 not withing trench.), to be formed at the substrate on which the mask M is formed (Lee et al. Fig. 24); PNG media_image3.png 462 414 media_image3.png Greyscale performing a second etching T3 so as to have an overhang structure at a lower end area of the vertical trench (Lee et al. Fig. 33); PNG media_image4.png 484 494 media_image4.png Greyscale forming an insulation layer at the trench with the overhang structure (Lee et al. Fig. 34 – 110 & Fig. 13 – 510 – Note: Figs 24-34 demonstrate the method of forming the structure as shown in Fig. 13.); and PNG media_image5.png 458 470 media_image5.png Greyscale PNG media_image6.png 664 439 media_image6.png Greyscale forming a passing word-line (PWL) by filling a conductive material in the trench such that the insulation layer is between the conductive material and the substrate (Lee et al. Fig. 13); and PNG media_image7.png 664 721 media_image7.png Greyscale wherein the performing the second etching comprises, performing an etching of a side surface area of the vertical trench so that the overhang structure is positioned at a lower part of a storage node [i.e. gate structure is physically positioned beneath a buried contact (BC) and a landing pad (LP), which connect the active region to a lower electrode 171 of a capacitor.] in the unit cell (Lee et al. Fig. 33, 35, & 13). The device structure shown in Figure 13 of Lee et al. meets the scope of the applicant's definition of a "passing word line." Furthermore, Lee et al. demonstrates means for forming these various structures throughout the document. The overhang structure depicted in Figure 13 is understood to be formed by the process shown in Figures 24-34 and their corresponding text. As such, a person of ordinary skill in the art (POSITA) at the time of the invention would find it obvious to form the structure of Figure 13 using the standard processing techniques demonstrated within the document, even if not explicitly stated relative to that specific figure. The individual parts having the required shapes would be expected to incorporate the process steps disclosed to form those particular shapes. Therefore, it would be obvious to a POSITA to select these known methods when forming a passing wordline as shown in Figure 13 of Lee et al. The legal basis for this obviousness rejection is established under MPEP § 2144.04, which permits using established rationales for combining references when the outcome is predictable. Specifically, this case relies on the rationales of "combining prior art elements according to known methods to yield predictable results" and "applying a known technique to a known device." Lee et al. provides both the structure (Figure 13) and the known manufacturing methods (Figures 24-34) separately within the same reference, meaning combining these known steps results in a predictable structure. Applying a known etching and deposition technique from the reference (Figures 24-34) to a known structural goal (the wordline in Figure 13) yields a predictable outcome that is well within the ordinary skill of a Person of Ordinary Skill in the Art (POSITA). Lee further teaches, wherein the overhang structure has an inclined structure that is extended in width in the unit cell direction from a pre-set center area to a lower end of the vertical trench (Lee et al. Fig. 33, 35, & 13); and wherein the pre-set center area of the vertical trench is a storage node (SN) junction area (Lee et al. Fig. 33, 35, & 13 Note: This limitation is not understood to provide any further manipulative distinction in the method claim, as it merely describes intended use/operation).. CLAIM 5. Lee et al. disclose a method of claim 1, wherein the forming the insulation layer comprises, filling the second etched area with an insulation material (Lee et al. Fig. 33, 35, & 13). CLAIM 6. Lee et al. disclose a method of claim 1, wherein the unit cell is a transistor of a saddle fin structure (Lee et al. Fig. 33, 35, & 13 Note: This limitation is not understood to provide any further manipulative distinction in the method claim, as it merely describes intended use/operation and/or structure). Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to JARRETT J STARK whose telephone number is (571)272-6005. The examiner can normally be reached 8-4 M-F. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached at 571-272-2339. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. JARRETT J. STARK Primary Examiner Art Unit 2822 7/16/2026 /JARRETT J STARK/Primary Examiner, Art Unit 2898
Read full office action

Prosecution Timeline

Show 1 earlier event
Aug 15, 2025
Non-Final Rejection mailed — §103
Nov 17, 2025
Response Filed
Dec 05, 2025
Final Rejection mailed — §103
Jan 30, 2026
Request for Continued Examination
Feb 10, 2026
Response after Non-Final Action
Mar 03, 2026
Non-Final Rejection mailed — §103
Jul 01, 2026
Response Filed
Jul 20, 2026
Final Rejection mailed — §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12707920
PROCESSING CONDITION SPECIFYING METHOD, SUBSTRATE PROCESSING METHOD, SUBSTRATE PRODUCT PRODUCTION METHOD, COMPUTER PROGRAM, STORAGE MEDIUM, PROCESSING CONDITION SPECIFYING DEVICE, AND SUBSTRATE PROCESSING APPARATUS
4y 0m to grant Granted Aug 11, 2026
Patent 12696654
LIGHT-EMITTING SUBSTRATE, DISPLAY PANEL AND DISPLAY DEVICE
2y 9m to grant Granted Jul 28, 2026
Patent 12684818
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THEREOF
3y 5m to grant Granted Jul 14, 2026
Patent 12685081
METHOD FOR TRANSPORTING WAFERS
2y 0m to grant Granted Jul 14, 2026
Patent 12677555
DISPLAY APPARATUS
2y 11m to grant Granted Jul 07, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

5-6
Expected OA Rounds
70%
Grant Probability
82%
With Interview (+11.3%)
2y 8m (~0m remaining)
Median Time to Grant
High
PTA Risk
Based on 1287 resolved cases by this examiner. Grant probability derived from career allowance rate.

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