DETAILED ACTION
AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Withdrawal of Indicated Allowable Subject Matter
In light of prior art reference Ishimatsu, the indicated allowability of claims 1-3, 5-15, and 17 is withdrawn. Applicant is advised that the Notice of Allowance mailed 21 OCT 2025 is vacated. If the issue fee has already been paid, applicant may request a refund or request that the fee be credited to a deposit account. However, applicant may wait until the application is either found allowable or held abandoned. If allowed, upon receipt of a new Notice of Allowance, applicant may request that the previously submitted issue fee be applied. If abandoned, applicant may request refund or credit to a specified Deposit Account.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 10 DEC 2025 was filed after the mailing date of the Notice of Allowance on 21 OCT 2025. The submission follows the provisions of 37 CFR 1.97. Accordingly, the IDS is being considered by the examiner.
New Grounds of Rejection
A new ground of rejection, prior art reference Ishimatsu (WO 2019235267), appears below.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all
obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103(a) are summarized as follows (Graham Factors):
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-3, 5-15, and 17 are rejected under 35 U.S.C. 103 as obvious over Mihashi (JP H0884057; below, “Mihashi” – previously cited 27 JAN 2023 IDS noted reference) with evidence from and/or in view of Ishimatsu (WO 2019235267; below, “Ishimatsu” – 10 DEC 2025 IDS noted reference). At least “combining prior art elements”, “simple substitution”, “obvious to try”, and “applying a known technique to a known device” rationales support a conclusion of obviousness. MPEP § 2143(A)-(G).
RE 1, Mihashi, in Figures 7, 8, and related text, e.g., paragraphs [0067] to [0085], discloses a semiconductor device (Example 4) comprising:
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a first semiconductor element (6 - N-type MOS transistor for pull-up) configured to receive a first driving signal (signal a) inputted thereto and to switch between an electrical communication state and a blocked state in accordance with the first driving signal (signal a);
a first control element (14 - inverter, 27 - NOR gate) configured to receive a first input signal (signal c) inputted thereto and to generate the first driving signal (signal a) based on the first input signal (signal c) and outputs the first driving signal (signal a) to the first semiconductor element (6);
a second semiconductor element (3 - N-type MOS transistor for pull-down) configured to receive a second driving signal (signal b) inputted thereto and to switch between an electrical communication state and a blocked state in accordance with the second driving signal (signal b);
a second control element (13 - inverter, 26 - NOR gate) configured to receive a second input signal (signal d) inputted thereto and to generate the second driving signal (signal b) based on the second input signal (signal d) and outputs the second driving signal (signal b) to the second semiconductor element (3):
(see Ishimatsu for: a first lead that includes a first terminal portion for inputting the first input signal and a second lead that includes a second terminal portion for inputting the second input signal),
wherein the first control element (14, 27) is configured to receive the second input signal (signal d) inputted thereto, and when determining, based on the second input signal (signal d), that the second semiconductor element (3) is in the electrical communication state, the first control element (14, 27) delays switching (Td1 - prevents simultaneous-on of transistors 3 and 6 - see Figure 8 timing chart) of the first semiconductor element (6) from the blocked state to the electrical communication state (see Figures 7, 8, and written opinion of the International Searching Authority (ISR submitted 27 JAN 2023)),
(see Ishimatsu for: the first lead is in electrical communication with the first control element (14, 27) and the second control element (13, 26), and the second lead is in electrical communication with the second control element (13, 26)).
Mihashi is silent regarding: a first lead that includes a first terminal portion for inputting the first input signal and a second lead that includes a second terminal portion for inputting the second input signal; and the first lead is in electrical communication with the first control element and the second control element, and the second lead is in electrical communication with the second control element.
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Ishimatsu, in FIG. 2 and related text, e.g., paragraphs [0042] to [0062], teaches a first lead (frames 33U, 33V, 33W) that includes a first terminal portion for inputting a first input signal and a second lead (frames 34U, 34V, 34W) that includes a second terminal portion for inputting a second input signal; and the first lead (frames 33U, 33V, 33W) is in electrical communication (wires 62) with a first control element (25H – substitute for 14) and the second control element (25L – substitute for 13, 26), and the second lead (frames 34U, 34V, 34W) is in electrical communication (wires 62) with the second control element (25L).
Mihashi and Ishimatsu are analogous art from the same field of endeavor as the claimed invention. It would have been obvious to a person having ordinary skill in the art before the effective filing date of the instant application to modify Mihashi as taught by Ishimatsu because: 1. element mounting structures are realized that dissipate heat and provide electrical connections; and 2. all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, and the combination would have yielded predictable results to one of ordinary skill in the art at the time of the invention. KSR International Co. v. Teleflex Inc. (KSR), 550 U.S. 398 (2007).
RE 2, modified Mihashi discloses the semiconductor device according to claim 1, wherein the second input signal (signal d) is a rectangular pulse wave that has an on-level and an off-level, the first control element (14, 27) does not switch the first semiconductor element (6) to the electrical communication state until a first period elapses after the second input signal (signal d) has been switched from the on-level to the off-level, and the first period is set based on a first transition time that starts when the second driving signal (signal b) is output from the second control element (13, 26) to the second semiconductor element (3) in order to switch the second semiconductor element (3) from the electrical communication state to the blocked state and terminates when the second semiconductor element (3) is switched from the electrical communication state to the blocked state (see Figures 7, 8, and ISR submitted 27 JAN 2023).
RE 3, modified Mihashi discloses the semiconductor device according to claim 2, wherein the first period is equal to or longer than the first transition time, and the first semiconductor element (6) is switched from the blocked state to the electrical communication state based on the first driving signal (signal a) after the first period has
elapsed (e.g., [0085] - see Figures 7, 8, and ISR submitted 27 JAN 2023).
RE 5, modified Mihashi discloses the semiconductor device according to claim 1, further including a first connection member (62) connected to the first control element (Ishimatsu’s 25L in lieu of 14), wherein the first connection member (62) is in electrical communication with the second lead (frames 34U, 34V, 34W).
RE 6, modified Mihashi discloses the semiconductor device according to claim 5, wherein the second control element (13, 26) receives the first input signal inputted thereto and when determining, based on the first input signal, that the first semiconductor element (6) is in the electrical communication state, the second control element (13, 26) delays switching (see Figure 8 timing chart) of the second semiconductor element (3) from the blocked state to the electrical communication state.
RE 7, modified Mihashi discloses the semiconductor device according to claim 6, wherein the first input signal (signal c) is a rectangular pulse wave that has an on-level and an off-level (see Figure 8 timing chart), the second control element (13, 26) does not switch the second semiconductor element (3) to the electrical communication state until a second period elapses after the first input signal (signal c) has been switched from the on-level to the off-level, and the second period is set based on a second transition time that starts when the first driving signal (signal a) is output from the first control element (14, 27) to the first semiconductor element (6) in order to switch the first semiconductor element (6) from the electrical communication state to the blocked state and terminates when the first semiconductor element (6) is switched from the electrical communication state to the blocked state.
RE 8, modified Mihashi discloses the semiconductor device according to claim 7,
wherein the second period is equal to or longer than the second transition time, and the second control element (13, 26) generates the second driving signal (signal b) in order to switch the second semiconductor element (3) from the blocked state to the electrical communication state after the second period has elapsed.
RE 9, modified Mihashi is silent regarding the semiconductor device according to claim 7, wherein the second input signal (signal d) is an inverted signal obtained by inverting the first input signal (signal c). Regarding the underlined portion of claim 9, the Office understands applicant’s desire to use broad method language instead of claim terms limited to a particular structural embodiment. Applicants are reminded that the method of forming a device is not germane to the issue of patentability of the device itself. "[E]ven though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process." In re Thorpe, 777 F.2d 695,698,227 USPQ 964, 966 (Fed. Cir. 1985).
RE 10, modified Mihashi discloses the semiconductor device according to claim 6, further including a second connection member (62) connected to the second control element (Ishimatsu’s 25H in lieu of 13), wherein the second connection member (62) is
in electrical communication with the first lead (frames 33U, 33V, 33W).
RE 11, modified Mihashi discloses the semiconductor device according to claim 10, further including:
a substrate (40) having a first surface; and
a wiring pattern (beneath 50) made of a conductive material that is formed on the first surface, wherein the wiring pattern (beneath 50) includes a first wiring portion that is in electrical communication with the first lead (Ishimatsu’s 33U, 33V, 33W), and a second wiring portion that is in electrical communication with the second lead (Ishimatsu’s 34U, 34V, 34W), the first connection member is connected to the second wiring portion, and the second connection member is connected to the first wiring portion.
RE 12, modified Mihashi discloses the semiconductor device according to claim 11, wherein the wiring pattern (beneath 50) includes a third wiring portion to which at least one of the first control element (14, 27) and the second control element (13, 26) is joined.
RE 13, modified Mihashi discloses the semiconductor device according to claim 10, wherein the first lead (Ishimatsu’s 33U, 33V, 33W) includes a first conductive portion that is electrically connected to the first terminal portion, the second lead (Ishimatsu’s 34U, 34V, 34W) includes a second conductive portion that is electrically connected to the second terminal portion, the first connection member is connected to the second conductive portion, and the second connection member is connected to the first conductive portion.
RE 14, modified Mihashi discloses the semiconductor device according to claim 13, further including a third lead (Ishimatsu’s 34A, 34B, 34C, 34D) to which at least one of the first control element (14, 27) and the second control element (13, 26) is joined.
RE 15, Mihashi, in Figures 7, 8, and related text, e.g., paragraphs [0067] to [0085], discloses a semiconductor device (Example 4) comprising:
a first semiconductor element (6 - N-type MOS transistor for pull-up) configured to receive a first driving signal (signal a) inputted thereto and to switch between an electrical communication state and a blocked state in accordance with the first driving signal (signal a);
a first control element (14 - inverter, 27 - NOR gate) configured to receive a first input signal (signal c) inputted thereto and to generate the first driving signal (signal a) based on the first input signal (signal c) and outputs the first driving signal (signal a) to the first semiconductor element (6);
a second semiconductor element (3 - N-type MOS transistor for pull-down) configured to receive a second driving signal (signal b) inputted thereto and to switch between an electrical communication state and a blocked state in accordance with the second driving signal (signal b); and
a second control element (13 - inverter, 26 - NOR gate) configured to receive a
second input signal (signal d) inputted thereto and to generate the second driving signal (signal b) based on the second input signal (signal d) and outputs the second driving signal (signal b) to the second semiconductor element (3),
wherein the first control element (14, 27) is configured to receive the second input signal (signal d) inputted thereto, and when determining, based on the second input signal (signal d), that the second semiconductor element (3) is in the electrical communication state, the first control element (14, 27) delays switching (Td1 - prevents simultaneous-on of transistors 3 and 6 - see Figure 8 timing chart) of the first semiconductor element (6) from the blocked state to the electrical communication state (see Figures 7, 8, and written opinion of the International Searching Authority (ISR
submitted 27 JAN 2023)),
wherein the first semiconductor element (6) includes a first electrode (e.g., drain), a second electrode (e.g., source), and a third electrode (e.g., gate), and the first driving signal (signal a) is input to the third electrode (gate) to switch between a state in which the first electrode (drain) and the second electrode (source) are in electrical communication with each other and a state in which these electrodes are blocked from each other, and the second semiconductor element (3) includes a fourth electrode (e.g., drain), a fifth electrode (e.g., source), and a sixth electrode (e.g., gate), and the second driving signal (signal b) is input to the sixth electrode (gate) to switch between a state in which the fourth electrode (drain) and the fifth electrode (source) are in electrical communication with each other and a state in which these electrodes are blocked from each other (see Figures 7, 8, and ISR submitted 27 JAN 2023), the semiconductor device further including:
(see Ishimatsu for: a fourth lead on which the first semiconductor element is mounted and that is in electrical communication with the first electrode (drain); a fifth lead on which the second semiconductor element is mounted and that is in electrical communication with the fourth electrode (drain) and the second electrode (source); and a sixth lead that is in electrical communication with the fifth electrode (source)).
Mihashi is silent regarding a fourth lead on which the first semiconductor element is mounted and that is in electrical communication with the first electrode (drain); a fifth lead on which the second semiconductor element is mounted and that is in electrical communication with the fourth electrode (drain) and the second electrode (source); and a sixth lead that is in electrical communication with the fifth electrode
(source).
Ishimatsu, in FIG. 2 and related text, e.g., paragraphs [0042] to [0062], teaches a fourth lead (e.g., 31) on which the first semiconductor element (11U, 11V, 11W in lieu of 6) is mounted and that is in electrical communication (wires 62) with the first electrode (drain); a fifth lead (e.g., 32U, 32V, 32W) on which the second semiconductor element (12U, 12V, 12W in lieu of 3) is mounted and that is in electrical communication with the fourth electrode (drain) and the second electrode (source); and a sixth lead (e.g., 35U, 35V, 35W) that is in electrical communication (wires 62) with the fifth electrode (source).
Mihashi and Ishimatsu are analogous art from the same field of endeavor as the claimed invention. It would have been obvious to a person having ordinary skill in the art before the effective filing date of the instant application to modify Mihashi as taught by Ishimatsu because: 1. element mounting structures are realized that dissipate heat and provide electrical connections; and 2. all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, and the combination would have yielded predictable results to one of ordinary skill in the art at the time of the invention. KSR International Co. v. Teleflex Inc. (KSR), 550 U.S. 398 (2007).
RE 17, modified Mihashi discloses the semiconductor device according to claim 15, wherein a DC voltage is applied between the fourth lead (31) and the sixth lead (35U, 35V, 35W), the DC voltage is converted to an AC voltage by switching of the first semiconductor element (6) between the electrical communication state and the blocked state (e.g., Mihashi [0067]-[0074]) and switching of the second semiconductor element (3) between the electrical communication state and the blocked state, and the AC voltage is applied to the fifth lead (32U, 32V, 32W).
Claims 1-3, 5-15, and 17 are rejected.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Walter Swanson whose telephone number is (571) 270-3322. The examiner can normally be reached Monday to Thursday, 8:30 to 17:30 EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Joshua Benitez, can be reached on (571)270-1435. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300.
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/WALTER H SWANSON/Primary Examiner, Art Unit 2815