Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 4/1/2026 has been entered.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-5, 7-8, 10-12, and 14-15 are rejected under 35 U.S.C. 103 as being unpatentable over Mulaosmanovic et al. US 2020/0065647 and Nikonov et al. WO 2019/066959.
Re claim 1, Mulaosmanovic teaches a synaptic component for a neural network (fig2a or 2b), comprising:
a semiconducting layer (201, fig2a or 2b, [40]);
a source electrode (202 left, fig2a/b, [51]) connected to the semiconducting layer; and
a drain electrode (202 right, fig2a/b, [51]) connected to the semiconducting layer,
wherein the source electrode is spatially separated from the drain electrode (fig2a/b),
wherein the source electrode (metallic 202, fig2a/b, [51]) and the semiconducting layer form a first Schottky diode ([51]),
wherein the source electrode is separated from a first gate electrode (206, fig2a/b, [39]) by a layer of ferroelectric material (204, fig2a/b, [43]),
wherein the first gate electrode (206, fig2a/b, [39]) is located on a first side (top side of 204, fig2a) of the layer of ferroelectric material (204, fig2a/b, [43]) and the source electrode and/or the drain electrode (202 left, fig2a/b, [51]) are located on a second side (bottom side of 204, fig2a) of the layer of the ferroelectric material (204, fig2a/b, [43]) opposite the first side (top side of 204, fig2a).
Mulaosmanovic does not explicitly show wherein the layer of ferroelectric material overlaps respective regions of the source electrode and/or the drain electrode.
Nikonov teaches a double ferroelectric gate transistor as synapses (fig4) wherein the drain electrode (403, fig4, [30]) is separated from a second gate electrode (405b, fig4, [29]) by the ferroelectric material (404b, fig4, [29]), and wherein the first gate electrode (405a, fig4, [29]) is spatially separated from the second gate electrode (405b, fig4, [29]); wherein the layer of ferroelectric material (404a/b, fig4, [29]) overlaps respective regions of the source electrode (402, fig4, [30]) and/or the drain electrode (403, fig4, [30]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Mulaosmanovic and Nikonov to use a double ferroelectric gate structure as synapses and replace 204-206 of Mulaosmanovic of fig2a with 404a/b-405a/b of Nikonov in fig4. The motivation to do so is to increase device integration density and reduce number of transistors needed in the neural network (Nikonov, [15]).
Re claim 2, Mulaosmanovic modified above teaches the synaptic component according to claim1, wherein the drain electrode forms with the semiconducting layer a second Schottky diode (Mulaosmanovic, [51]).
Re claim 3, Mulaosmanovic does not explicitly show the synaptic component according to claim1, wherein the drain electrode is separated from a second gate electrode by the ferroelectric material, and wherein the first gate electrode is spatially separated from the second gate electrode.
Nikonov teaches a double ferroelectric gate transistor as synapses (fig4) wherein the drain electrode (403, fig4, [30]) is separated from a second gate electrode (405b, fig4, [29]) by the ferroelectric material (404b, fig4, [29]), and wherein the first gate electrode (405a, fig4, [29]) is spatially separated from the second gate electrode (405b, fig4, [29]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Mulaosmanovic and Nikonov to use a double ferroelectric gate structure as synapses and replace 204-206 of Mulaosmanovic of fig2a with 404a/b-405a/b of Nikonov in fig4. The motivation to do so is to increase device integration density and reduce number of transistors needed in the neural network (Nikonov, [15]).
Re claim 4, Mulaosmanovic modified above teaches the synaptic component according to claim3, wherein the source electrode and the drain electrode are located on one side of the semiconducting layer (Nikonov, 402/403 on top side of 401, fig4, [29]) and/or at opposite ends of the semiconducting layer.
Re claim 5, Mulaosmanovic modified above teaches the synaptic component according to claim1, wherein the semiconducting layer (Mulaosmanovic, 201, fig2a or 2b, [40]) is located above a substrate (Mulaosmanovic, 208, fig2b, [45]) or in that the semiconducting layer is the substrate (Mulaosmanovic, 201, fig2a, [40]).
Re claim 7, Mulaosmanovic modified above teaches the synaptic component according to claim1, wherein the ferroelectric material is present as a layer which is at least partially located on the semiconducting layer (Mulaosmanovic, 204 located on top surface of 201 replaced by 404a/b of Nikonov in fig4 , fig2a/6).
Re claim 8, Mulaosmanovic does not explicitly show the synaptic component according to claim1, wherein the ferroelectric material is present as a layer which is at least partially located on the source electrode and/or the drain electrode.
Nikonov teaches a double ferroelectric gate transistor as synapses (fig4) wherein ferroelectric material (404a/b, fig4, [29]) is present as a layer which is at least partially located on the source electrode and/or the drain electrode (402, 403, fig4, [30]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Mulaosmanovic and Nikonov to use a double ferroelectric gate structure as synapses and replace 204-206 of Mulaosmanovic of fig2a with 404a/b-405a/b of Nikonov in fig4. The motivation to do so is to increase device integration density and reduce number of transistors needed in the neural network (Nikonov, [15]).
Re claim 10, Mulaosmanovic does not explicitly show the synaptic component according to claim 1, further comprising a second gate electrode located on first side of the layer of ferroelectric layer.
Nikonov teaches a double ferroelectric gate transistor as synapses (fig4) wherein ferroelectric material is present as a layer (404a/b, fig4, [35]) and the first gate electrode and/or a second gate electrode (405a/b on top side of 404a/b, fig4, [29]) are located on one side of the ferroelectric layer and the source electrode and/or the drain electrode are located on the opposite side of the ferroelectric layer (402/403 located on bottom side of 404a/b, fig4, [29, 30]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Mulaosmanovic and Nikonov to use a double ferroelectric gate structure as synapses and replace 204-206 of Mulaosmanovic of fig2a with 404a/b-405a/b of Nikonov in fig4. The motivation to do so is to increase device integration density and reduce number of transistors needed in the neural network (Nikonov, [15]).
Re claim 11, Mulaosmanovic modified above teaches the synaptic component according to claim1, wherein the component is electrically connected to at least one further component in series or in parallel to form a crossbar structure (Mulaosmanovic, fig1a-c).
Re claim 12, Mulaosmanovic modified above teaches the synaptic component according to claim1, wherein the ferroelectric material (Mulaosmanovic, 204 replaced by 404a/b of Nikonov in fig4, fig2a/b, [43]) is selected from: doped HfO2 ferroelectric (Mulaosmanovic, [44]), a perovskite ferroelectric, an organic ferroelectric.
Re claim 14, Mulaosmanovic modified above teaches the synaptic component according to claim1, wherein the semiconducting layer (Mulaosmanovic, 201, fig2a, [40]) is partially covered with a layer of electrically insulating material (Mulaosmanovic, 203, fig2a, [37]).
Re claim 15, Mulaosmanovic modified above teaches a neural network (Mulaosmanovic, fig1a-c), comprising: the synaptic component according to claim1 (Mulaosmanovic, fig2a/b); and a neuron electrically connected to the synaptic component (Mulaosmanovic, fig1b).
Claim(s) 6 is rejected under 35 U.S.C. 103 as being unpatentable over Mulaosmanovic et al. US 2020/0065647 in view of Nikonov et al. WO 2019/066959 and Then et al. US 2016/0365435.
Re claim 6, Mulaosmanovic does not explicitly show the synaptic component according to claim1, wherein the semiconducting layer is a semiconductor heterostructure.
Then teaches transistor channel using a semiconductor heterostructure (107-106, fig1A, [40]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Mulaosmanovic modified above and Then to use a semiconductor heterostructure under the gate structure. The motivation to do so is to achieve high breakdown voltage (Then, [3]) improve power efficiency with steep sub-threshold slope swing (Then, [3, 24]).
Claim(s) 9 is rejected under 35 U.S.C. 103 as being unpatentable over Mulaosmanovic et al. US 2020/0065647 and Nikonov et al. WO 2019/066959 and Chen et al. US 2018/0158936.
Re claim 9, Mulaosmanovic does not explicitly show the synaptic component according to claim 8, wherein the ferroelectric material is present as a single layer which is located both at least partially on the source electrode and at least partially on the drain electrode.
Chen teaches a double gate Schottky FET (fig2) wherein the ferroelectric material (HfO2/Al2O3 between S/D 9/10 and gate 7/8, fig2, [38], 24]) is present as a single layer which is located both at least partially on the source electrode (9, fig2, [24]) and at least partially on the drain electrode (10, fig2, [24]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Mulaosmanovic in view of Nikonov and Chen to form a trenched gate with a single layer of ferro electric material formed between the two gates and S/D contacts as in Chen fig10-11. The motivation to do so is to tune working state of the device with the gate structure near the Schottky contact, utilize chip area, control on-state resistance, leakage current and on-state voltage drop with the trench gate (Chen, [25]).
Claim(s) 13 is rejected under 35 U.S.C. 103 as being unpatentable over Mulaosmanovic et al. US 2020/0065647 in view of Nikonov et al. WO 2019/066959 and Hou et al. US 2018/0151755.
Re claim 13, Mulaosmanovic does not explicitly show the synaptic component according to claim1, wherein the metal for a Schottky diode is selected from: Al, Ag, Au, Cu, Cr, Mo, Ni, Nb, Pt, Ti, Ni, TiN, TaN, or a metal semiconductor alloy such as silicides, germanides, metal-SiGeSn alloys.
Hou teaches the metal for a Schottky contact (32/34, fig3, [40]) is selected from: Al, Ag, Au, Cu, Mo, Nb, Ti, TiN, or a metal semiconductor alloy such as silicides ([40]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Mulaosmanovic in view of Nikonov and Hou to select a conductive material with suitable work function for the Schottky contact (Hou, [40]).
Claim(s) 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over Mulaosmanovic et al. US 2020/0065647 in view of Nikonov et al. WO 2019/066959 and Chen et al. US 2018/0158936.
Re claim 16, Mulaosmanovic teaches a method of operating a synaptic component according to claim1, an electric voltage is applied to the first gate electrode in a pulsed manner (fig1a-c and 2).
Mulaosmanovic does not explicitly show wherein the first Schottky diode is connected in reverse direction.
Chen teaches a double gate Schottky FET (fig2) wherein the first Schottky diode is connected in reverse direction (fig4, 5).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Mulaosmanovic in view of Nikonov and Chen to form a trenched gate with a single layer of ferroelectric material formed between the two gates and S/D contacts as in Chen fig10-11. The motivation to do so is to tune working state of the device with the gate structure near the Schottky contact, utilize chip area, control on-state resistance, leakage current and on-state voltage drop with the trench gate (Chen, [25]).
Re claim 17, Mulaosmanovic teaches the synaptic component according to claim 7, wherein the ferroelectric material is present as a single layer (204, fig2a/b, [43]).
Mulaosmanovic does not explicitly show wherein the ferroelectric material is present as a single layer which is located both at least partially on the source electrode and at least partially on the drain electrode.
Chen teaches a double gate Schottky FET (fig2) wherein the ferroelectric material (HfO2/Al2O3 between S/D 9/10 and gate 7/8, fig2, [38], 24]) present as a single layer which is located both at least partially on the source electrode and at least partially on the drain electrode (9/10, fig2, [24]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Mulaosmanovic in view of Nikonov and Chen to form a trenched gate with a single layer of ferroelectric material formed between the two gates and S/D contacts as in Chen fig10-11. The motivation to do so is to tune working state of the device with the gate structure near the Schottky contact, utilize chip area, control on-state resistance, leakage current and on-state voltage drop with the trench gate (Chen, [25]).
Conclusion
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/XIAOMING LIU/Examiner, Art Unit 2812
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