Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 10/14/2025 have been fully considered but they are not persuasive. Examiner thanks Applicant for Applicant’s cooperation in the prosecution process and for Applicant’s concise analysis of the prior Office Action 7/15/2025 (Prior Office Action) found in Applicant's Remarks. The Remarks assert that:
Mulaosmanovic does not teaches or suggest “the first gate electrode is located on a first side of the layer of ferroelectric material and the source electrode and/or the drain electrode are located on a second side of the layer of ferroelectric material opposite the first side”.
The Manual of Patent Examining Procedure (MPEP) states that “[d]uring patent examination, the pending claims must be ‘given their broadest reasonable interpretation consistent with the specification.’” MPEP §2111 [R-5] citing Phillips v. AWH Corp., 415 F.3d 1303, 75 USPQ2d 1321 (Fed. Cir. 2005). MPEP §2171 also states that the claims of an application “define the metes and bounds of the subject matter that will be protected....”
In regards to the above assertion, while the Remarks may assert a valid interpretation of the limitation of "the first gate electrode is located on a first side of the layer of ferroelectric material and the source electrode and/or the drain electrode are located on a second side of the layer of ferroelectric material opposite the first side", Examiner respectfully submits that the interpretation asserted by the Remarks is not the broadest reasonable interpretation. The broadest reasonable interpretation of the term "side" includes a place, space, or direction with respect to a center or to a line of division. Examiner respectfully submits that Mulaosmanovic teaches wherein the first gate electrode (206, fig2a/b, [39]) is located on a first side (top side of 204, fig2a) of the layer of ferroelectric material (204, fig2a/b, [43]) and the source electrode and/or the drain electrode (202 left, fig2a/b, [51]) are located on a second side (bottom side of 204, fig2a) of the layer of the ferroelectric material (204, fig2a/b, [43]) opposite the first side (top side of 204, fig2a). Examiner therefore respectfully submits that Mulaosmanovic anticipates the limitations of claim 1 and that claim 1 stands properly rejected.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-2, 5, 7, 11-12 and 15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Mulaosmanovic et al. US 2020/0065647.
Re claim 1, Mulaosmanovic teaches a synaptic component for a neural network (fig2a or 2b), comprising:
a semiconducting layer (201, fig2a or 2b, [40]);
a source electrode (202 left, fig2a/b, [51]) connected to the semiconducting layer; and
a drain electrode (202 right, fig2a/b, [51]) connected to the semiconducting layer,
wherein the source electrode is spatially separated from the drain electrode (fig2a/b),
wherein the source electrode (metallic 202, fig2a/b, [51]) and the semiconducting layer form a first Schottky diode ([51]),
wherein the source electrode is separated from a first gate electrode (206, fig2a/b, [39]) by a layer of ferroelectric material (204, fig2a/b, [43]),
wherein the first gate electrode (206, fig2a/b, [39]) is located on a first side (top side of 204, fig2a) of the layer of ferroelectric material (204, fig2a/b, [43]) and the source electrode and/or the drain electrode (202 left, fig2a/b, [51]) are located on a second side (bottom side of 204, fig2a) of the layer of the ferroelectric material (204, fig2a/b, [43]) opposite the first side (top side of 204, fig2a).
Re claim 2, Mulaosmanovic teaches the synaptic component according to claim1, wherein the drain electrode forms with the semiconducting layer a second Schottky diode ([51]).
Re claim 5, Mulaosmanovic teaches the synaptic component according to claim1, wherein the semiconducting layer (201, fig2a or 2b, [40]) is located above a substrate (208, fig2b, [45]) or in that the semiconducting layer is the substrate (201, fig2a, [40]).
Re claim 7, Mulaosmanovic teaches the synaptic component according to claim1, wherein the ferroelectric material is present as a layer which is at least partially located on the semiconducting layer (204 located on top surface of 201, fig2a/6).
Re claim 11, Mulaosmanovic teaches the synaptic component according to claim1, wherein the component is electrically connected to at least one further component in series or in parallel to form a crossbar structure (fig1a-c).
Re claim 12, Mulaosmanovic teaches the synaptic component according to claim1, wherein the ferroelectric material (204, fig2a/b, [43]) is selected from: doped HfO2 ferroelectric ([44]), a perovskite ferroelectric, an organic ferroelectric.
Re claim 14, Mulaosmanovic teaches the synaptic component according to claim1, wherein the semiconducting layer (201, fig2a, [40]) is partially covered with a layer of electrically insulating material (203, fig2a, [37]).
Re claim 15, Mulaosmanovic teaches a neural network (fig1a-c), comprising: the synaptic component according to claim1 (fig2a/b); and a neuron electrically connected to the synaptic component (fig1b).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 3-4, 8 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Mulaosmanovic et al. US 2020/0065647 and Nikonov et al. WO 2019/066959.
Re claim 3, Mulaosmanovic does not explicitly show the synaptic component according to claim1, wherein the drain electrode is separated from a second gate electrode by the ferroelectric material, and wherein the first gate electrode is spatially separated from the second gate electrode.
Nikonov teaches a double ferroelectric gate transistor as synapses (fig4) wherein the drain electrode (403, fig4, [30]) is separated from a second gate electrode (405b, fig4, [29]) by the ferroelectric material (404b, fig4, [29]), and wherein the first gate electrode (405a, fig4, [29]) is spatially separated from the second gate electrode (405b, fig4, [29]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Mulaosmanovic and Nikonov to use a double ferroelectric gate structure as synapses and replace 204-206 of Mulaosmanovic of fig2a with 404a/b-405a/b of Nikonov in fig4. The motivation to do so is to increase device integration density and reduce number of transistors needed in the neural network (Nikonov, [15]).
Re claim 4, Mulaosmanovic modified above teaches the synaptic component according to claim3, wherein the source electrode and the drain electrode are located on one side of the semiconducting layer (Nikonov, 402/403 on top side of 401, fig4, [29]) and/or at opposite ends of the semiconducting layer.
Re claim 8, Mulaosmanovic does not explicitly show the synaptic component according to claim1, wherein the ferroelectric material is present as a layer which is at least partially located on the source electrode and/or the drain electrode.
Nikonov teaches a double ferroelectric gate transistor as synapses (fig4) wherein ferroelectric material (404a/b, fig4, [29]) is present as a layer which is at least partially located on the source electrode and/or the drain electrode (402, 403, fig4, [30]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Mulaosmanovic and Nikonov to use a double ferroelectric gate structure as synapses and replace 204-206 of Mulaosmanovic of fig2a with 404a/b-405a/b of Nikonov in fig4. The motivation to do so is to increase device integration density and reduce number of transistors needed in the neural network (Nikonov, [15]).
Re claim 10, Mulaosmanovic does not explicitly show the synaptic component according to claim 1, further comprising a second gate electrode located on first side of the layer of ferroelectric layer.
Nikonov teaches a double ferroelectric gate transistor as synapses (fig4) wherein ferroelectric material is present as a layer (404a/b, fig4, [35]) and the first gate electrode and/or a second gate electrode (405a/b on top side of 404a/b, fig4, [29]) are located on one side of the ferroelectric layer and the source electrode and/or the drain electrode are located on the opposite side of the ferroelectric layer (402/403 located on bottom side of 404a/b, fig4, [29, 30]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Mulaosmanovic and Nikonov to use a double ferroelectric gate structure as synapses and replace 204-206 of Mulaosmanovic of fig2a with 404a/b-405a/b of Nikonov in fig4. The motivation to do so is to increase device integration density and reduce number of transistors needed in the neural network (Nikonov, [15]).
Claim(s) 6 is rejected under 35 U.S.C. 103 as being unpatentable over Mulaosmanovic et al. US 2020/0065647 in view of Then et al. US 2016/0365435.
Re claim 6, Mulaosmanovic does not explicitly show the synaptic component according to claim1, wherein the semiconducting layer is a semiconductor heterostructure.
Then teaches transistor channel using a semiconductor heterostructure (107-106, fig1A, [40]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Mulaosmanovic and Then to use a semiconductor heterostructure under the gate structure. The motivation to do so is to achieve high breakdown voltage (Then, [3]) improve power efficiency with steep sub-threshold slope swing (Then, [3, 24]).
Claim(s) 9 is rejected under 35 U.S.C. 103 as being unpatentable over Mulaosmanovic et al. US 2020/0065647 and Nikonov et al. WO 2019/066959 and Chen et al. US 2018/0158936.
Re claim 9, Mulaosmanovic does not explicitly show the synaptic component according to claim 8, wherein the ferroelectric material is present as a single layer which is located both at least partially on the source electrode and at least partially on the drain electrode.
Chen teaches a double gate Schottky FET (fig2) wherein the ferroelectric material (HfO2/Al2O3 between S/D 9/10 and gate 7/8, fig2, [38], 24]) is present as a single layer which is located both at least partially on the source electrode (9, fig2, [24]) and at least partially on the drain electrode (10, fig2, [24]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Mulaosmanovic in view of Nikonov and Chen to form a trenched gate with a single layer of ferro electric material formed between the two gates and S/D contacts as in Chen fig10-11. The motivation to do so is to tune working state of the device with the gate structure near the Schottky contact, utilize chip area, control on-state resistance, leakage current and on-state voltage drop with the trench gate (Chen, [25]).
Claim(s) 13 is rejected under 35 U.S.C. 103 as being unpatentable over Mulaosmanovic et al. US 2020/0065647 and Hou et al. US 2018/0151755.
Re claim 13, Mulaosmanovic does not explicitly show the synaptic component according to claim1, wherein the metal for a Schottky diode is selected from: Al, Ag, Au, Cu, Cr, Mo, Ni, Nb, Pt, Ti, Ni, TiN, TaN, or a metal semiconductor alloy such as silicides, germanides, metal-SiGeSn alloys.
Hou teaches the metal for a Schottky contact (32/34, fig3, [40]) is selected from: Al, Ag, Au, Cu, Mo, Nb, Ti, TiN, or a metal semiconductor alloy such as silicides ([40]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Mulaosmanovic and Hou select a conductive material with suitable work function for the Schottky contact (Hou, [40]).
Claim(s) 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over Mulaosmanovic et al. US 2020/0065647 and Chen et al. US 2018/0158936.
Re claim 16, Mulaosmanovic teaches a method of operating a synaptic component according to claim1, an electric voltage is applied to the first gate electrode in a pulsed manner (fig1a-c and 2).
Mulaosmanovic does not explicitly show wherein the first Schottky diode is connected in reverse direction.
Chen teaches a double gate Schottky FET (fig2) wherein the first Schottky diode is connected in reverse direction (fig4, 5).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Mulaosmanovic and Chen to form a trenched gate with a single layer of ferroelectric material formed between the two gates and S/D contacts as in Chen fig10-11. The motivation to do so is to tune working state of the device with the gate structure near the Schottky contact, utilize chip area, control on-state resistance, leakage current and on-state voltage drop with the trench gate (Chen, [25]).
Re claim 17, Mulaosmanovic teaches the synaptic component according to claim 7, wherein the ferroelectric material is present as a single layer (204, fig2a/b, [43]).
Mulaosmanovic does not explicitly show wherein the ferroelectric material is present as a single layer which is located both at least partially on the source electrode and at least partially on the drain electrode.
Chen teaches a double gate Schottky FET (fig2) wherein the ferroelectric material (HfO2/Al2O3 between S/D 9/10 and gate 7/8, fig2, [38], 24]) present as a single layer which is located both at least partially on the source electrode and at least partially on the drain electrode (9/10, fig2, [24]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Mulaosmanovic and Chen to form a trenched gate with a single layer of ferroelectric material formed between the two gates and S/D contacts as in Chen fig10-11. The motivation to do so is to tune working state of the device with the gate structure near the Schottky contact, utilize chip area, control on-state resistance, leakage current and on-state voltage drop with the trench gate (Chen, [25]).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to XIAOMING LIU whose telephone number is (571)270-0384. The examiner can normally be reached Monday-Friday, 9am-8pm, EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine S Kim can be reached at (571)272-8458. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/XIAOMING LIU/Examiner, Art Unit 2812