DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
IDS
The IDS document(s) filed on 12/02/2022, 04/25/2024, 09/20/2024, 12/03/2024, and 02/28/2025 have been considered. Copies of the PTO-1449 documents are herewith enclosed with this office action.
Election
Applicant's election with traverse of Group I, claims 1-17, in the reply filed on 06/25/2025 is acknowledged. The traversal is on the ground(s) that there is no serious burden on the Examiner to collectively examine the different claim Groups. Applicant’s arguments are found persuasive, claims 18-20 are rejoined.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-4, 7-8, 10, 13-15, and 17-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kamikawa et al. (WO 2018204916 A1), hereafter “Kamikawa”.
As to claim 1, Kamikawa teaches a method, comprising:
growing one or more epitaxial lateral overgrowth (ELO) layers (Page 5, Ln 10-12, 106, Fig. 2) and device layers (Page 5, Ln 24-25, 108) on a substrate (Page 5, Ln 5, 101) using a growth restrict mask (Page 5, Ln 5-6, 102);
fabricating one or more devices (Page 5, Ln 25-27, Page 6, Ln 1-3, 109-115) on or above the ELO layers and device layers;
isolating the ELO layers and device layers on the growth restrict mask from the substrate (Page 6, Ln 23, Page 7, Ln 2; Page 17, Ln 3-5); and
transferring the isolated ELO layers and device layers to a carrier wafer (Page 7, Ln 8-10, 1001, Fig. 10).
As to claim 2, Kamikawa teaches wherein the isolating step includes a separating process that divides the ELO layers and device layers into the devices (Page 6, Ln 15-17).
As to claim 3, Kamikawa teaches wherein the transferring step includes a bonding process without a solder (Page 16, Ln 4-5).
As to claim 4, Kamikawa teaches wherein the transferring step includes a bonding process with a solder (Page 7, Ln 8-10, Fig. 10).
As to claim 7, Kamikawa teaches wherein the fabricating step is conducted after the transferring step (Fig. 15, steps 1507+1508 are the transfer steps and they are performed before the fabricating steps of 1509+1510+1511, Page 21 Ln 3-20).
As to claim 8, Kamikawa teaches wherein the isolated ELO layers (106) and device layers (108) remain on the growth restrict mask (102) (Page 6, Ln 23, Page 7, Ln 2; Page 17, Ln 3-5).
As to claim 10, Kamikawa teaches further comprising removing the ELO layers and device layers from the substrate (Page 16, Ln 24-25).
As to claim 13, Kamikawa teaches (Page 1, Ln 14-15 wherein the substrate is a semiconducting substrate (Page 5, Ln 5, 101, “GaN-based substrate”).
As to claim 14, Kamikawa teaches wherein the semiconducting substrate is independent of crystal orientations (Page 5, Ln 5-9; Page 8, Ln 5-6; Page 22, Ln 6-8).
As to claim 15, Kamikawa teaches wherein the carrier wafer has one or more cladding layers, distributed Bragg reflector (DBR) layers, or heatsinks, for the devices (Page 5, Ln 25-26, “cladding layer 109”).
As to claim 17, Kamikawa teaches wherein the growth restrict mask comprises a multi-layer structure (Page 9, Ln 3-5).
As to claim 18, Kamikawa teaches a device fabricated by the method of claim 1 (see claim 1 rejection).
As to claim 19, Kamikawa teaches a device, comprising:
one or more epitaxial lateral overgrowth (ELO) layers (Page 5, Ln 10-12, 106, Fig. 2) and device layers (Page 5, Ln 24-25, 108) grown on a substrate using a growth restrict mask (Page 5, Ln 5-6, 102), wherein:
one or more devices are fabricated on or above the ELO layers and device layers (Page 5, Ln 25-27, Page 6, Ln 1-3, 109-115);
the ELO layers and device layers are isolated on the growth restrict mask from the substrate (Page 6, Ln 23, Page 7, Ln 2; Page 17, Ln 3-5); and
the isolated ELO layers and device layers are transferred to a carrier wafer (Page 7, Ln 8-10, 1001, Fig. 10).
As to claim 20, Kamikawa teaches wherein the device comprises a micro-sized light-emitting diode (pLED), edge-emitting laser, or vertical-cavity surface-emitting laser (VCSEL) (Page 8, Ln 20-25).
Claim Rejections - 35 U.S.C. § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 5 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Kamikawa, and further in view of Kamikawa et al. (WO 2019055936 A1), hereafter “Kamikawa ‘936”.
As to claim 5, Kamikawa teaches wherein the transferring step integrates the ELO layers (106) and device layers (108) onto the carrier wafer (1001) (Page 21, Ln 3-6, Fig. 11).
Kamikawa fails to teach the carrier wafer is larger than the substrate.
Kamikawa ‘936 also teaches a method removing a substrate wherein a large wafer may be adopted into the method (Page 39, Ln 25-26, “>2 inches”).
It would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the large wafer taught by Kamikawa ‘936 into the method of Kamikawa for the benefit of a large-area semiconductor device can be easily realized (Page 39, Ln 19-20).
As to claim 16, Kamikawa fails to teach wherein the carrier wafer has one or more epitaxial distributed Bragg reflector (DBR) layers for the devices.
Kamikawa ‘936 also teaches a method removing a substrate wherein a device (VSCEL, Fig. 14) utilizes a DBR (1402+1408) (Page 29, Ln 25-28, Page 30 Ln 1).
It would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the DBR layers of Kamikawa ‘936 into the method of Kamikawa in order to avoid large optical loss (Page 30, Ln 2-3).
Claims 6 is rejected under 35 U.S.C. 103 as being unpatentable over Kamikawa, and further in view of Boone, Jr. et al. (US 2015/0036468 A1), hereafter “Boone”.
As to claim 6, Kamikawa fails to teach wherein the transferred ELO layers and device layers are integrated onto a photonic integration circuit.
Boone teaches a method including the removal of formed layers from a substrate (⁋ [0019]) and integrating those layers onto a photonic integration circuit (⁋ [0048]).
It would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the photonic integration circuit of Boone into the method of Kamikawa in order to generate and direct heat (⁋ [0027]).
Claims 9, and 11-12 are rejected under 35 U.S.C. 103 as being unpatentable over Kamikawa, and further in view of Gandrothula. et al. (WO 2019232230 A1), hereafter “Gandrothula”.
As to claim 9, Kamikawa teaches wherein the isolated ELO layers (106) and device layers (108) remain on the growth restrict mask (102) (Page 6, Ln 23-27, Page 7, Ln 1-2, Fig. 9).
Kamikawa fails to teach the ELO layers and devices layers remaining with assistance from a secured hook layer.
Gandrothula also teaches a method of removing a substrate wherein a film (Page 42, Ln 2-6, 601, Fig. 31a) is utilized in a hook method to secure the ELO layers (Page 57, Ln 25, Page 58 Ln 1-3, 109, Fig. 31b).
It would have been obvious to one of ordinary skill in the art before the effective filing date that the hook technique utilized by Gandrothula could be incorporated into the method of Kamikawa, specifically securing the layers with assistance, because the island layers can then be handled individually or in a bitch using a vacuum chuck or some industrially mature process (Page 44, Ln 3-7).
As to claim 11, Kamikawa fails to teach wherein the removing step is performed using a pick-and-place, a vacuum chuck, surface activation bonding, or bonding through an intermediate layer.
Gandrothula also teaches a method of removing a substrate wherein island layers (109) comprising ELO and device layers (Page 19, Ln 9-10, 105+106, Fig. 1(a)), are removed by a pick and place method (Page 26, Ln 1-6).
It would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the pick and place method of Gandrothula into the method of Kamikawa because the method is useful for mass-production, especially for micro-LEDS (Page 26, Ln 18-19).
As to claim 12, Kamikawa fails to teach wherein the removing step is performed selectively.
Gandrothula also teaches a method of removing a substrate wherein island layers (109) comprising ELO and device layers (Page 19, Ln 9-10, 105+106, Fig. 1(a)), are removed selectively (Page 57, Ln 14-16)
It would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the selective removal method of Gandrothula into the method of Kamikawa because this technique can obtain a 100% throughput with a less lead time in a cheaper way (Page 58, Ln 7-8).
Conclusion
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/CARNELL HUNTER III/Examiner, Art Unit 2893
/SUE A PURVIS/Supervisory Patent Examiner, Art Unit 2893