DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claims presented have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1 and 6 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 1, the limitation “being used to implement a string selection transistor or a ground selection transistor”, renders the claim indefinite. It is unclear what the applicant meant by “being used to implement a string selection transistor or a ground selection transistor”. Appropriate correction is required to clarify the language of the limitation. For purposes of compact prosecution, the examiner interprets the limitation “being used to implement a string selection transistor or a ground selection transistor” to mean that the at least one selection line may be used to either form a string selection transistor or a ground selection transistor.
Claims 2-4 are also rejected as they depend on claim 1.
Regarding claim 6, claim 6 recites “wherein a partial region of the channel layer, which corresponds to the GSL, is formed of silicon by using crystallized silicon of an upper surface of the substrate.” This language is unclear as the language, on its face, suggests to one having ordinary skill in the art that the crystallized silicon of the upper surface of the substrate is the portion of the channel which corresponds to the GSL. However, when looking closely at the Applicant’s drawings (specifically Figs. 13 and 14) and written description, the Examiner understands that Applicant’s invention to be that the crystallized silicon of the upper surface of the substrate is merely used in a process in which an epitaxial growth of single crystal silicon occurs, the grown single crystal silicon being the partial region of the channel layer. Appropriate correction is required to clarify the language. For purposes of compact prosecution, the Examiner interprets the language of “wherein a partial region of the channel layer, which corresponds to the GSL, is formed of silicon by using crystallized silicon of an upper surface of the substrate” to be where a partial region of the channel layer, which corresponds to the GSL, is formed in a process which utilizes a crystallized silicon upper surface of the substrate.
Regarding claim 6, claim 6 further recites a first limitation “wherein a partial region of the channel layer, which corresponds to the GSL, is formed of silicon by using crystallized silicon of an upper surface of the substrate” which states that a parti of the channel is formed using a crystallized silicon upper surface of the substrate and then a second limitation following the first limitation recites “and wherein the upper surface of the substrate is crystallized to single crystal silicon as a laser annealing technique is applied to poly-silicon forming the substrate” recites the formation of the crystallized upper surface of a poly silicon substrate. This language is confusing as the formation of the crystallized silicon upper surface of the polysilicon substrate is introduced in the claim after the crystallized silicon upper surface is utilized to form the partial region channel. Therefore, it is unclear whether the crystallized silicon of the upper surface recited in the first limitation is the same or different from the crystallized single crystal silicon upper surface of a poly silicon substate. Appropriate correction is required. For purposes of compact prosecution, the Examine interprets the crystallized silicon upper surface of the substrate of the first limitation to be the same structure as the crystallized single crystal silicon upper surface of the substrate.
Regarding claim 6, claim 6 further recites “and wherein the upper surface of the substrate is crystallized to single crystal silicon as a laser annealing technique is applied to poly-silicon forming the substrate”. However, as claim 6 is a product claim, and not a method, it is unclear whether the Applicant is attempting to claim a polysilicon substrate or a crystallized silicon substrate. For purposes of compact prosecution, the Examiner interprets the language to require a substrate having at least a crystallized silicon upper surface (See product process recitation in the art rejection of claim 6 below). Appropriate correction is required.
Claim 10 is also rejected as it depends on claim 6.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 6 and 11-13 are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Lee et al. (US20170047343A1).
Regarding claim 6, Fig.7 Lee teaches a three-dimensional flash memory to which a Cell on Peri (COP) structure is applied, comprising:
a plurality of word lines WL0-WL3 (Fig.3, para.0056) extended formed in a horizontal direction on a substrate 100 (para.0066) and sequentially stacked;
a ground selection line (GSL) GSL (Fig.3, para.0056) located under the plurality of word lines WL0-WL3; and
at least one string DS/VS (Fig.19, para.0115) extended and formed in a vertical direction on the substrate 100 to penetrate the plurality of word lines WL0-WL3 and the GSL, wherein the at least one string DS/VS includes a channel layer VS (pata.0062) extended and formed in the vertical direction and a charge storage layer DS (para.0115) extended and formed in the vertical direction to surround the channel layer VS,
wherein a partial region of the channel layer VS, which corresponds to the GSL, is formed of silicon by using crystallized silicon of an upper surface of the substrate 100 (para.0066 and 0074, wherein the lower semiconductor pattern LSP may be formed to have a single crystalline structure and corresponds to gate electrodes EL of the ground selection transistor GST), and
wherein the upper surface of the substrate 100 is crystallized to single crystal silicon as a laser annealing technique is applied to poly-silicon forming the substrate 100 (para.0074, the lower semiconductor pattern LSP may be an epitaxial pattern, which may be formed by an epitaxial process or a laser crystallization process using the horizontal semiconductor layer 100 as a seed semiconductor layer),
wherein the partial region of the channel layer VS (para.0074), which corresponds to the GSL, is formed of the single crystal silicon through epitaxial growth that is based on the crystallized silicon of the upper surface of the substrate 100, and
wherein a remaining region of the channel layer VS, which corresponds to the plurality of word lines WL0-WL3, is formed of poly-silicon (para.0072, 0074, wherein the upper semiconductor pattern USP may be formed to have one of polycrystalline structures).
The process limitations of “wherein a partial region of the channel layer, which corresponds to the GSL, is formed of silicon by using crystallized silicon of an upper surface of the substrate, and wherein the upper surface of the substrate is crystallized to single crystal silicon as a laser annealing technique is applied to poly-silicon forming the substrate, wherein the partial region of the channel layer, which corresponds to the GSL, is formed of the single crystal silicon through epitaxial growth that is based on the crystallized silicon of the upper surface of the substrate” found in product claim 6 invokes the product-by-process doctrine. Product-by-process claims are not limited to the manipulations of the recited steps, only the structure implied by the steps (MPEP § 2113). Anticipation of claim 6 does not require that the channel region is formed by epitaxially growing crystalline silicon from the crystalline silicon upper surface of the substrate nor does it require that the crystalline upper surface of the substrate is formed by laser annealing of a polysilicon substrate, but simply that A) a partial region of the channel layer, which corresponds to the GSL, is formed of single crystal silicon, and B) where the upper surface of the substrate is single crystal silicon.
Regarding claim 11, Fig. 7 of Lee teaches a substrate to which a Cell on Peri (COP) structure used in a three-dimensional flash memory is applied, comprising:
an epitaxial seed region (para.0074, wherein the lower semiconductor pattern LSP may be an epitaxial pattern, which may be formed by an epitaxial process) used for epitaxial growth for forming a portion of a channel layer VS (pata.0062) included in the three-dimensional flash memory, wherein the portion of the channel layer VS corresponds to a ground selection line (GSL) EL (para.0056) and is formed with single crystal silicon (para.0074, wherein the lower semiconductor pattern LSP may be formed to have a single crystalline structure);
a peripheral circuit region PS (para.0081) in which a peripheral circuit 23/25/27/31/33 (para.0060) is embedded by the COP structure; and
a poly-silicon layer (para.0073, upper semiconductor pattern USP, which includes a polycrystalline structure is disposed on seed semiconductor layer 100) disposed on the epitaxial seed region,
wherein the poly-silicon layer includes:
at least one vertical hole (wherein vertical structures, which include lower semiconductor pattern LSP and upper semiconductor pattern USP, are formed in vertical holes) that is filled with the single crystal silicon formed through the epitaxial growth from the epitaxial seed region up to a portion corresponding to the GSL (para.0056 and 0074, wherein the lower semiconductor pattern LSP may be formed to have a single crystalline structure and corresponds to gate electrodes EL of the ground selection transistor GST), and is filled with poly-silicon in a remaining portion of the at least one vertical hole (para.0072, wherein the upper semiconductor pattern USP may be formed to have one of polycrystalline structures (para.0072,0074)).
Regarding claim 12, Lee further teaches the substrate claim 11, wherein the epitaxial seed region 100 (para.0074) and the peripheral circuit region PS (para.0081) form a pattern in which the epitaxial seed region 100 and the peripheral circuit region PS are disposed alternately and repeatedly on the substrate 10 (para.0059).
Regarding claim 13, Lee further teaches the substrate claim 11, wherein an epitaxial growth layer (para.0074) in which single crystal silicon formed through the epitaxial growth from the epitaxial seed region 100 (para.0074) is smoothed is disposed on an upper portion of the epitaxial seed region 100 and the peripheral circuit region PS (para.0081).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4 are rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (US20140038400A1) in view of Rabkin et al. (US20160149004A1).
Regarding claim 1, Fig.7A and 7B of Park teaches a three-dimensional flash memory comprising:
a string 110/140 (Fig.1G, para.0048) extended and formed in one direction on a substrate 190 (para.0052), wherein the string 110/140 includes a channel layer 110 (para.0052) extended and formed in the one direction and a charge storage layer 140 (para.0048) extended and formed in the one direction to surround the channel layer 110;
at least one selection line vertically connected with an uppermost end (para.0129, first and second steps S1 and S2 may be used to form string selection lines SSL; the ninth and tenth steps S9 and S10 may be used to form ground selection lines GSL; and the third to eighth steps S3 to S8 may be used to form word lines WL) or a lowermost of the string 110/140, the at least one selection line SSL (para.0129) being used to implement a string selection transistor (para.0008, cell transistor) or a ground selection transistor; and
a plurality of word lines WL (para.0129) located over or under the at least one selection line SSL (para.0129) and vertically connected with the string 110/140,
wherein a thickness of the at least one selection line SSL is less than a thickness of each of the plurality of word lines WL (para.0131, wherein sacrificial layers 103 of first and second steps S1 and S2, and/or sacrificial layers 103 of ninth and tenth steps S9 and S10 may be thinner than sacrificial layers 103 of the other steps S3 to S8, wherein first and second steps S1 and S2 may be used to form string selection lines SSL and the third to eighth steps S3 to S8 may be used to form word lines WL).
Park does not teach wherein the channel layer is formed of an oxide semiconductor material and wherein the thickness of the at least one selection line SSL is reduced due to a leakage current characteristic of the oxide semiconductor material forming the channel layer.
Fig.3B of Rabkin teaches a three-dimensional (3D) non-volatile storage device with vertically-oriented NAND strings with a channel that comprises an oxide semiconductor having a crystalline structure (para.0026).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the oxide semiconductor vertical channel of Rabkin in the teachings of Park because oxide semiconductor has an energy band gap that is wider than silicon and the wider the energy band gap, the higher the critical field. This means that breakdown voltage may be larger for the same size device, relative to silicon (Rabkin, [para.0027]).
Regarding claim 2, Rabkin further teaches the three-dimensional flash memory claim 1, wherein an entire channel layer 699 (para.0046) is formed of the oxide semiconductor material.
Regarding claim 3, the combination of Park and Rabkin teaches the three-dimensional flash memory claim 1, wherein a physical structure of the at least one selection line is determined based on the leakage current characteristic of the oxide semiconductor material forming the channel layer (Park, para.0037, at least one of the selection lines SSL and GSL may have a multi-layer structure. For example, the string selection line SSL may have a two-layer structure. In this case, the channel length of cells constituted by the string selection line SSL may be increased to improve leakage current characteristics).
Regarding claim 4, Park teaches the three-dimensional flash memory claim 3, wherein a number of the at least one selection line is adjusted based on the leakage current characteristic of the oxide semiconductor material forming the channel layer (para.0130, wherein thicker selection lines SSL and GSL formed by a gate replacement process results in an increased channel length which, in turn, improves performance relative to leakage current).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US20170047343A1) in view of Chowdhury et al. (US9397111B1).
Regarding claim 10, Lee does not teach wherein a remaining region of the substrate other than the upper surface is formed of poly-silicon.
Fig.11P of Chowdhury teaches wherein a remainder of the slit 1110 is filled with a conductive material 1128 in the stack 1100 and wherein if the conductive material 1124 is polysilicon, the top of the polysilicon may be cleaned and an additional conductive material 1128 is added. The additional conductive material may be metal or polysilicon (col.18, lines 5-11).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include a polysilicon in the remainder of the slit, as taught by Chowdhury, in order to provide contact above the crystalline silicon (Chowdhury [col.15, lines 39-42]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VINCENT KIPKEMOI RONO whose telephone number is (571)270-5977. The examiner can normally be reached Mon-Fri, 8am-5pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Landau can be reached at (571)272-1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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VINCENT KIPKEMOI. RONO
Examiner
Art Unit 2891
/V.K.R./Examiner, Art Unit 2891
/MATTHEW C LANDAU/Supervisory Patent Examiner, Art Unit 2891
Prosecution Insights