DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is in response to Amendment filed on February 5, 2026.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3, 13, 15 and 20 are rejected under 35 U.S.C. 102(a)(1) or (a)(2) as being anticipated by Lin et al. (US 2021/0098376, hereinafter Lin).
Regarding claim 1, Lin discloses for a semiconductor device, comprising that:
a semiconductor chip (integrated circuit (IC) device 200, Fig. 16) made of semiconductor material (silicon substrate 210, Fig. 16, [0015]) having a device forming surface on which a device structure (upper surface of substrate 210 of IC device 200, Fig. 16) is formed;
a first conductive layer (left via bulk material 330, Fig. 16) formed on the device forming surface of the semiconductor chip (surface of 210, Fig. 16);
a second conductive layer (left via bulk material 340, Fig. 16) formed on the first conductive layer (330, Fig. 16);
a first wire (conductive line 394A, Fig. 16) that is connected to the second conductive layer (left 340, Fig. 16) and that is made of a material composed mainly of copper, because “conductive lines 394A-394C include tungsten, ruthenium, cobalt, copper, aluminum, iridium, palladium, platinum, nickel, other low resistivity metal constituent, alloys thereof, or combinations thereof” (emphasis added, [0055]), and because Applicant does not specifically claim what dimensions the first wire have and/or what it looks like, the conductive line 394A of the metal layer (M1) by Lin can be made of copper and electrically connected to the via bulk material 340, therefore, the conductive line 394A can correspond to the first wire in the claimed invention;
a third conductive layer (left via barrier layer 335, Fig. 16) that is formed between the first conductive layer and the second conductive layer (between left 330 and left 340, Fig. 16) and that includes a material harder than copper, because “for example, via barrier layer 335 includes titanium, titanium alloy, tantalum, tantalum alloy, cobalt, cobalt alloy, ruthenium, ruthenium alloy, molybdenum, molybdenum alloy, tungsten, tungsten alloy…” (emphasis added, [0043]) and it is well-known in the art that these metals are generally harder than copper, and Applicant originally disclosed that “the third conductive layer 193 is made of, for example, a material that is harder than Cu (copper) and that includes at least one of Ti and W, and, in the present preferred embodiment, the third conductive layer 193 has a layered structure (Ti/TiN) in which Ti and TiN are laminated in order from a boundary between the third conductive layer 193 and the first conductive layer 191” (emphasis added, [0081] of the present application), therefore, the via barrier layer 335 can be made of the same material of the third conductive layer, such as Ti and W, as disclosed in the present application; and
an insulating film (interlayer dielectric (ILD) layer 254, Fig. 16) formed on the semiconductor chip (210, Fig. 16), wherein
a thickness of the second conductive layer (thickness of 340, i.e., = thickness t8 – thickness of 335, Fig. 17A) is smaller than a thickness of the first conductive layer (thickness of 330 = thickness t7, Fig. 17A), because Lin further discloses that “thickness t8 may be greater or less than thickness t7 depending on growth of via bulk material 330” (emphasis added, [0048]), therefore, when the thickness t8 is less than the thickness t7 (i.e., thickness of 330), the thickness of the via bulk material 340 is less than the thickness of the via bulk material 330,
a thickness of the third conductive layer (thickness of 335, i.e., thickness t3 and t4 in Fig. 9A, Fig. 17A) is smaller than both the thickness of the first conductive layer (thickness of 330, i.e., thickness t7, Fig. 17A) and the thickness of the second conductive layer (thickness of 340, Fig. 17A), because Lin further discloses that “thickness of t3 is about 4 nm to about 8 nm, and thickness t4 is about 1 nm to about 3 nm” ([0043]) and “thickness t8 is about 1 nm to about 50 nm” (emphasis added, [0048]), therefore, the thickness of via barrier layer 335 is less than the thicknesses of via bulk materials 330 and 340 (Fig. 17A),
the device structure (200, Fig. 16) includes a concave portion (opening portion 270A, see Fig. 3) formed at the semiconductor chip (210, Fig. 3) and an electroconductive embedded body (left contact bulk layer 286 of left source/drain contact 282A, Fig. 16) embedded in the concave portion (opening portion 270A, see Fig. 3),
the first conductive layer (left 330, Fig. 16) covers the concave portion (left 270A having 282A embedded, Fig. 16, also see Fig. 3), and
the concave portion (left 270A having 282A embedded, Fig. 16, also see Fig. 3) is formed at the semiconductor chip (210, Fig. 16), which is made of semiconductor material (silicon substrate 210, [0015]), through the insulating film as one groove (through ILD layer 254 as one opening 270A, Fig. 16, also see Fig. 3).
Regarding claim 2, Lin further discloses for the semiconductor device according to claim 1 that a fourth conductive layer (left contact barrier layer 284, Fig. 16) that is formed between the semiconductor chip (210, Fig. 16) and the first conductive layer (left 330, Fig. 16) and that includes a material harder than copper, because “contact barrier layer 284 includes titanium, titanium alloy, tantalum, tantalum alloy, cobalt, cobalt alloy, ruthenium, ruthenium alloy, molybdenum, molybdenum alloy, palladium, palladium alloy…” ([0030]) and it is well-known in the art that these metals are generally harder than copper.
Regarding claim 3, Lin further discloses for the semiconductor device according to claim 2 that the fourth conductive layer (left 284, Fig. 16) includes a same material as the third conductive layer (left 335, Fig. 16), because “for example, via barrier layer 335 includes titanium, titanium alloy, tantalum, tantalum alloy, cobalt, cobalt alloy, ruthenium, ruthenium alloy, molybdenum, molybdenum alloy, tungsten, tungsten alloy…” (emphasis added, [0043]) and “contact barrier layer 284 includes titanium, titanium alloy, tantalum, tantalum alloy, cobalt, cobalt alloy, ruthenium, ruthenium alloy, molybdenum, molybdenum alloy, palladium, palladium alloy…” (emphasis added, [0030]).
Regarding claim 13, Lin further discloses for the semiconductor device according to claim 1 that the third conductive layer (left 335, Fig. 16) includes at least one of Ti and W, because “for example, via barrier layer 335 includes titanium, titanium alloy, tantalum, tantalum alloy, cobalt, cobalt alloy, ruthenium, ruthenium alloy, molybdenum, molybdenum alloy, tungsten, tungsten alloy…” (emphasis added, [0043]).
Regarding claim 15, Lin further discloses for the semiconductor device according to claim 1 that the first conductive layer (left 330, Fig. 16) and the second conductive layer (left 340, Fig. 16) are made of a same material, because “Via bulk material 330 includes tungsten, tungsten alloy, ruthenium, ruthenium alloy, cobalt, cobalt alloy, copper, copper alloy, aluminum, aluminum alloy, iridium, iridium alloy, palladium, palladium alloy, platinum, platinum alloy, nickel, nickel alloy, other low resistivity metal constituent and/or alloys thereof, or combinations thereof” ([0041]) and “Via bulk material 340 includes tungsten, tungsten alloy, ruthenium, ruthenium alloy, cobalt, cobalt alloy, copper, copper alloy, aluminum, aluminum alloy, iridium, iridium alloy, palladium, palladium alloy, platinum, platinum alloy, nickel, nickel alloy, other low resistivity metal constituent and/or alloys thereof, or combinations thereof” ([0045]).
Regarding claim 20, Lin further discloses for the semiconductor device according to claim 1 that the concave portion (270A, Fig. 3) includes a first inner surface (bottom 276A, Fig. 3) formed of the semiconductor material of the semiconductor chip on a bottom side thereof, because the bottom surface 276A is a surface of the epitaxial source/drain feature 240 B, which is made of p-type or n-type doped semiconductor materials ([0021]) and a second inner surface (sidewall 272A or 274A, Fig. 3) formed of an insulating material of the insulating film (254, Fig. 3) on an opening side thereof (upper side of 270A, Fig. 3), and the first inner surface (276A, Fig. 3) and the second inner surface (272A or 274A, Fig. 3) are continuous with each other (Fig. 3).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4, 7, 9, 11, 16-17 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over by Lin et al. (US 2021/0098376, hereinafter Lin).
Regarding claim 4, Lin does not explicitly disclose that a thickness of the third conductive layer is equal to or less than a thickness of the fourth conductive layer.
However, Lin further discloses that a thickness of the via barrier layer 335 (i.e., thickness t3 and t4, Fig. 16) is about 4 nm to about 8 nm for t3 and is about 1 nm to about 3 nm for t4 ([0043]). Lin further discloses that “a thickness of contact barrier layer 284 varies along ILD layer 254” ([0037]). Therefore, Lin recognizes that the thicknesses of the via barrier layer and contact barrier layer impact the performance of the semiconductor device. The thickness of barrier layers is therefore a result-effective variable to be optimized by repeated experiments.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to vary, through routine optimization, thicknesses of barrier layers as Lin have identified the thicknesses as a result-effective variable. Further, one of ordinary skill in the art would have had a reasonable expectation of success to arrive at the fact that the thickness of the third conductive layer is equal to or less than the thickness of the fourth conductive layer, in order to achieve the desired contact resistance in the contact structure, as taught by Lin. Furthermore, the applicant has not presented persuasive evidence that the claimed thicknesses is for a particular purpose that is critical to the overall claimed invention (i.e., that the invention would not work without the specific claimed thicknesses).
Regarding claim 7, Lin further discloses for the semiconductor device according to claim 1 that the insulating film (254, Fig. 16) includes an interlayer insulating film (ILD layer 254, Fig. 16) formed between the semiconductor chip (210, Fig. 16) and the first conductive layer (330, Fig. 16);
the concave portion (left opening 270A having source/drain contact 282A, Fig. 16, also see Fig. 3) passes through the interlayer insulating film (254, Fig. 16) and reaches an intermediate position of the semiconductor chip (a position where a bottom surface of the contact barrier layer 284 is located, Fig. 16) in a thickness direction (vertical direction in Fig. 16) of the semiconductor chip;
a fourth conductive layer (left contact barrier layer 284, Fig. 16) is conformal to an inner surface of the concave portion (inner sidewall of the left opening 270A, Fig. 16) and includes a material harder than copper, because “contact barrier layer 284 includes titanium, titanium alloy, tantalum, tantalum alloy, cobalt, cobalt alloy, ruthenium, ruthenium alloy, molybdenum, molybdenum alloy, palladium, palladium alloy…” ([0030]) and it is well-known in the art that these metals are generally harder than copper; and
an electroconductive embedded body (left contact bulk layer 286 of left source/drain contact 282A, Fig. 16) is embedded in the concave portion (left 270A, Fig. 16, also see Fig. 3) with the fourth conductive layer (left 284, Fig. 16) between the embedded body (left 286, Fig. 16) and the concave portion (left 270A, Fig. 16, also see Fig. 3).
Lin does not explicitly disclose that a fourth conductive layer is conformal to an upper surface of the interlayer insulating film.
However, Lin further discloses that “contact barrier layer 284 may thus be formed by a conformal deposition process” ([0029]) and one of ordinary skill in the art would have understood that the conformal deposition process deposits the contact barrier layer 284 on all exposed surfaces of the structure, including the sidewalls and bottom of the via opening as well as exposed portions proximate to the edges of the via opening adjacent to the IDL layer 294 (Fig. 16). Examiner notes that Applicant does not specifically claim that the fourth conductive layer is conformal to an entire upper surface of the interlayer insulating film.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form a conductive barrier layer conformally within a via opening and an adjacent upper surface of an insulating layer, as disclosed by Lin, because conformal deposition is a well-known manufacturing technique that provides reliable coverage of exposed surfaces and facilitate fabrication of semiconductor devices.
Regarding claim 9, Lin further discloses for the semiconductor device according to claim 1 that a fifth conductive layer (right via bulk material 330’, Fig. 17A) that is formed on the device forming surface of the semiconductor chip (210, Fig. 17A) and that is separated from the first conductive layer (left 330’, Fig. 17A);
a sixth conductive layer (right via bulk material 340’, Fig. 17A) formed on the fifth conductive layer (right 330’, Fig. 17A);
a seventh conductive layer (right via barrier layer 335’, Fig. 17A) that is formed between the fifth conductive layer (right 330’, Fig. 17A) and the sixth conductive layer (right 340’, Fig. 17A) and that includes a material harder than copper, because “for example, via barrier layer 335 includes titanium, titanium alloy, tantalum, tantalum alloy, cobalt, cobalt alloy, ruthenium, ruthenium alloy, molybdenum, molybdenum alloy, tungsten, tungsten alloy…” (emphasis added, [0043]) and it is well-known in the art that these metals are generally harder than copper, and Applicant originally disclosed that “the third conductive layer 193 is made of, for example, a material that is harder than Cu (copper) and that includes at least one of Ti and W, and, in the present preferred embodiment, the third conductive layer 193 has a layered structure (Ti/TiN) in which Ti and TiN are laminated in order from a boundary between the third conductive layer 193 and the first conductive layer 191” (emphasis added, [0081] of the present application), therefore, the via barrier layer 335 can be made of the same material of the third conductive layer, such as Ti and W, as disclosed in the present application.
Lin does not explicitly disclose a second wire connected to the sixth conductive layer.
However, Lin further discloses that the conductive line 394B is disposed directly on the right via bulk material 340 (Fig. 16), and therefore, they are electrically connected each other. Because Applicant does not specifically claim what dimensions the second wire have and/or what it looks like, the conductive line 394B can correspond to the second wire in the claimed invention.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to dispose a conductive wire or line on contact plug, as disclosed by Lin, in order to electrically connect the semiconductor device with external circuitries or controllers.
Regarding claim 11, Lin further discloses for the semiconductor device according to claim 9 that the second wire (394B, Fig. 16) includes a wire made of a material composed mainly of copper, because “conductive lines 394A-394C include tungsten, ruthenium, cobalt, copper, aluminum, iridium, palladium, platinum, nickel, other low resistivity metal constituent, alloys thereof, or combinations thereof” (emphasis added, [0055]).
Regarding claim 16, Lin further discloses for the semiconductor device according to claim 15 that the first conductive layer (left 330, Fig. 16) and the second conductive layer (left 340, Fig. 16) include AlCu, because “Via bulk material 330 includes tungsten, tungsten alloy, ruthenium, ruthenium alloy, cobalt, cobalt alloy, copper, copper alloy, aluminum, aluminum alloy, iridium, iridium alloy, palladium, palladium alloy, platinum, platinum alloy, nickel, nickel alloy, other low resistivity metal constituent and/or alloys thereof, or combinations thereof” (emphasis added, [0041]) and “Via bulk material 340 includes tungsten, tungsten alloy, ruthenium, ruthenium alloy, cobalt, cobalt alloy, copper, copper alloy, aluminum, aluminum alloy, iridium, iridium alloy, palladium, palladium alloy, platinum, platinum alloy, nickel, nickel alloy, other low resistivity metal constituent and/or alloys thereof, or combinations thereof” (emphasis added, [0045]), therefore, it is obvious to one of ordinary skill in the art that AlCu is one of copper alloys or aluminum alloys and one would readily recognize that AlCu can be selected for the via bulk material 330 and 340 in Lin.
Regarding claim 17, Lin does not explicitly disclose that a thickness of the second conductive layer is not less than 2 µm and not more than 4.5 µm.
However, Lin further discloses that thickness t8 (Fig. 17A), which refers to a total thickness of the via barrier layer 335 and the via bulk material 340, is about 1 nm to about 50 nm, and Lin recognizes that the thickness of via bulk material 340, which corresponds to the thickness of the second conductive layer in the claimed invention, impacts the performance of a contact structure of the semiconductor device. The thickness is therefore a result-effective variable to be optimized by repeated experiments.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to vary, through routine optimization, a thickness of the via bulk material as Lin has identified the thickness as a result-effective variable. Further, one of ordinary skill in the art would have had a reasonable expectation of success to arrive at the thickness not less than 2 µm and not more than 4.5 µm, in order to achieve the desired contact resistance of the electrical contact structure, as taught by Lin. Furthermore, the applicant has not presented persuasive evidence that the claimed thickness is for a particular purpose that is critical to the overall claimed invention (i.e., that the invention would not work without the specific claimed thickness).
Regarding claim 19, Lin further discloses for the semiconductor device according to claim 1 that in a stacking direction (vertical direction in Fig. 16) of the first conductive layer (left 330, Fig. 16), the second conductive layer (left 340, Fig. 16), and the third conductive layer (left 335, Fig. 16), a bonding surface at which the first wire is connected to the second conductive layer (interface between left 340 and 394A, Fig. 16) covers a plurality of the concave portions (opening 270A, Fig. 16, also see Fig. 3), because an interface between the conductive line 394A and the via bulk material 340, which correspond to the first wire and the second conductive layer in the claimed invention, respectively, overlies the opening portion (270A, Fig. 3) in a plan view (i.e., vertical direction). Furthermore, it is obvious to one of ordinary skill in the art that Lin’s integrated circuit (IC) 200 would have been understood to include a plurality of repeated circuit structures across the device. As such, the opening 270A in Fig. 3 represents one of a plurality of similar openings formed throughout the integrated circuit. Therefore, it would have been obvious to one of ordinary skill in the art that the bonding surface between the conductive line and the via bulk material covers a plurality of openings, which correspond to the plurality of concave portions in the claimed invention.
Allowable Subject Matter
Claims 6, 10, 12 and 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/JAY C KIM/Primary Examiner, Art Unit 2815
/WOO K LEE/Examiner, Art Unit 2815
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