DETAILED ACTION
This Office action responds to the application filed on 12/07/2022.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for a rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Election/Restrictions
Applicant’s election without traverse of Species 1b, reading on figures 1-13 & 16, in the reply filed on October 20, 2025, is acknowledged. The applicant indicates that claims 1-8, 11-14, and 18-20 read on the elected species. The examiner agrees. Accordingly, claims 9-10 & 15-17 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-6, 11, 14, 18-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Uno (US 20130221520) in view of Fujimori (JP 2011003586).
Regarding Claim 1, Uno (see, e.g., fig. 1, fig. 3b, fig. 4) shows a semiconductor element SC comprising:
an element obverse surface (see, e.g., annotated figure 1)
and an element reverse surface (see, e.g., annotated figure 1) facing away from each other in a thickness direction (see, e.g., annotated figure 1);
a plurality of electrodes PAD disposed on the element obverse surface;
an insulating layer SLL disposed on the element obverse surface;
and a plurality of electrode terminals PIL, NIL, & SOL each being held in contact with one of the plurality of electrodes and partly overlapping with the insulating layer as viewed in the thickness direction,
wherein the insulating layer includes
a plurality of openings (see, e.g., fig. 4)
and a plurality of overlapping portions (see, e.g., fig. 4) adjoining the plurality of openings, respectively,
the plurality of openings exposing the plurality of electrodes, respectively,
the plurality of overlapping portions overlapping with the plurality of electrodes, respectively, as viewed in the thickness direction,
the plurality of electrode terminals are in contact with the plurality of electrodes, respectively, through the plurality of openings,
while also overlapping with the plurality of overlapping portions, respectively, as viewed in the thickness direction,
the plurality of electrode terminals include
a plurality of first electrode terminals that are densely arranged as viewed in the thickness direction (see, e.g., fig. 3b, para.0035, annotated figure 3b)
and a plurality of second electrode terminals that are sparsely arranged as viewed in the thickness direction,
wherein the element obverse surface includes (see, e.g., para.0035)
a first region in which the plurality of first electrode terminals are arranged
and a second region in which the plurality of second electrode terminals are arranged,
while also including a first edge and a second edge spaced apart from each other in a first direction perpendicular to the thickness direction,
the first region is located on a side of the element obverse surface closer to the first edge, and the second region is located on a side of the element obverse surface closer to the second edge (see, e.g., annotated figure 1).
Uno, however, fails to show,
and each of the overlapping portions that overlaps with one of the plurality of first electrode terminals has a greater dimension in the thickness direction than each of the overlapping portions that overlaps with one of the plurality of second electrode terminals
Fujimori (see, e.g., figs. 1-2, para.0029-0032, para.0035-0036, para.0116) teaches each of the overlapping portions that overlaps with one of the plurality of first electrode terminals has a greater dimension in the thickness direction than each of the overlapping portions that overlaps with one of the plurality of second electrode terminals would relieve stress in the region of the plurality of second electrode terminals. The surrounding end portion of Fujimori would correspond to the first portion of Uno and would have a greater dimension in the thickness direction than the central thinner portion second portion of Uno.
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to use the configuration of Fujimori, in the device of Uno, to relieve stress in the region of the plurality of second electrode terminals.
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Regarding Claim 2, Uno (see, e.g., fig. 4, para.0036), in view of Fujimori, shows the semiconductor element according to claim 1,
wherein each of the plurality of electrode terminals includes a pillar portion being held in contact with a relevant one of the plurality of electrodes PAD
and containing Cu.
Regarding Claim 3, Uno (see, e.g., fig. 4. annotated figure 4, para.0038), in view of Fujimori, shows the semiconductor element according to claim 2,
wherein the pillar portion includes an end surface (see, e.g., annotated figure 4) opposite form the relevant electrode,
and the end surface includes
a peripheral portion
and a central portion recessed from the peripheral portion (see, e.g., para.0038).
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Regarding Claim 4, Uno (see, e.g., fig. 4, para.0037), in view of Fujimori, shows the semiconductor element according to claim 2,
wherein the pillar portion includes a seed layer SEED in contact with the relevant electrode
and a plating layer PIL & NIL disposed on the seed layer.
Regarding Claim 5, Uno (see, e.g., para.0038-0039), in view of Fujimori, shows the semiconductor element according to claim 4,
wherein the plating layer includes a first plating layer made of Cu PIL
and a second plating layer made of Ni NIL.
Regarding Claim 6, Uno (see, e.g., fig. 4, para.0036), in view of Fujimori, shows the semiconductor element according to claim 2,
wherein each of the electrode terminals includes a solder portion SOL in contact with the pillar portion.
Regarding Claim 11, Uno (see, e.g., fig. 3b), in view of Fujimori, shows the semiconductor element according to claim 1,
wherein each of the plurality of first electrode terminals is elliptical as viewed in thickness direction,
and each of the plurality of second electrode terminals is circular as viewed in thickness direction.
Regarding Claim 14, Uno (see, e.g., fig. 1, para.0033), in view of Fujimori, shows a semiconductor device SD comprising: a semiconductor element according to claim 1;
and a sealing resin UFR covering the semiconductor element.
Regarding Claim 18, Uno (see, e.g., fig. 4, para.0037), in view of Fujimori, shows the semiconductor element according to claim 3,
wherein the pillar portion includes a seed layer SEED in contact with the relevant electrode and a plating layer PIL & NIL disposed on the seed layer.
Regarding Claim 19, Uno (see, e.g., fig. 4, para.0036), in view of Fujimori, shows the semiconductor element according to claim 3,
wherein each of the electrode terminals includes a solder portion SOL in contact with the pillar portion.
Regarding Claim 20, Uno (see, e.g., fig. 4, para.0036), in view of Fujimori, shows the semiconductor element according to claim 4,
wherein each of the electrode terminals includes a solder portion SOL in contact with the pillar portion.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Uno (US 20130221520), in view of Fujimori (JP 2011003586) and further in view of Yanagida (JP 2019186345).
Regarding Claim 7, Uno, in view of Fujimori, shows the semiconductor element according to claim 1,
Uno, in view of Fujimori, however, fails to show
wherein the insulating layer contains a phenolic resin.
Yanagida (see, e.g., fig. 2, para.0027), in a similar device to Uno, in view of Fujimori, teaches that an insulating layer containing a phenolic resin would be a suitable material for the insulating layer.
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to use the phenolic resin of Yanagida, in the device of Uno, in view of Fujimori, as a suitable material for the insulating layer.
Claims 12 & 13 are rejected under 35 U.S.C. 103 as being unpatentable over Uno (US 20130221520), in view of Fujimori (JP 2011003586) and further in view of Doge (JP 2013166998).
Regarding Claim 12, Uno, in view of Fujimori, shows the semiconductor element according to claim 1,
Uno, in view of Fujimori, however, fails to show
wherein each of the plurality of electrodes contains Cu.
Doge (see, e.g., para.0009, para.0018-0020), in a similar device to Uno, in view of Fujimori, teaches a configuration wherein the plurality of electrodes contains Cu that would be more resistant to the generation of cracks and warpage.
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to use the configuration wherein the plurality of electrodes contains Cu of Doge, in the device of Uno, in view of Fujimori, to be more resistant to the generation of cracks and warpage.
Regarding Claim 13, Uno, in view of Fujimori, shows the semiconductor element according to claim 1,
Uno, in view of Fujimori, however, fails to show
wherein each of the plurality of electrodes includes
a first layer made of Cu,
a second layer made of Ni.
and a third layer made of Pd.
Doge (see, e.g., para.0009, para.0018-0020), in a similar device to Uno, in view of Fujimori, teaches a configuration wherein each of the plurality of electrodes includes a first layer made of Cu, a second layer made of Ni, a third layer made of Pd that would be more resistant to the generation of cracks and warpage.
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to use the configuration wherein each of the plurality of electrodes includes a first layer made of Cu, a second layer made of Ni, a third layer made of Pd of Doge, in the device of Uno, in view of Fujimori, to be more resistant to the generation of cracks and warpage.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FERNANDO JOSE RAMOS-DIAZ whose telephone number is (571) 270-5855. The examiner can normally be reached Mon-Fri 8am-5pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven Loke can be reached on 571-272-1657. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/FERNANDO JOSE RAMOS-DIAZ/Examiner, Art Unit 2818 /STEVEN H LOKE/Supervisory Patent Examiner, Art Unit 2818
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