Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
A request for continued examination (RCE) under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action mailed on 09/30/2025 ("09-30-25 Final OA") has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 11/13/2025 ("11-13-25 Submission") in an after-final response has been entered when the RCE was filed on 12/23/2025.
In the 11-13-25 Submission, the Applicant substantively amended claims 1, 3, 6-8 and 11.
Currently, claims 1-3 and 5-11 are pending and are examined below.
Response to Arguments
Applicant’s amendments to claims 1, 3 and 11 have overcome the 35 U.S.C. 112(b) rejection of claims 1-3 and 5-11 as set forth starting on page 3 under line item number 1 of the 09-30-25 Final OA.
Applicant’s amendments to the independent claims 1, 3 and 11 have overcome (i) the 35 U.S.C. 102(a)(1) rejection of claims 1-3, 7, 8, 10 and 11 as being anticipated by Romero as set forth starting on page 5 under line item number 2 of the 09-30-25 Final OA, (ii) the 35 U.S.C. 103 rejection of claims 5 and 6 as being unpatentable over Romero as set forth staring on page 10 under line item number 3 of the 09-30-25 Final and (ii) the 35 U.S.C. 103 rejection of claim 9 as being unpatentable over Romero and further in view of Takada as set forth starting on page 12 under line item number 4 of the 09-30-25 Final OA.
Substantively amendments to the independent claims 1, 3 and 11 required further consideration and search. New grounds of rejection are provided below.
A. Prior-art rejections based on Lee
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 3, 5, 7, 10 and 11 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Pub. No. US 2021/0375759 A1 to Lee et al. (“Lee”).
Fig. 2 of Lee has been provided to support the rejections below:
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Regarding independent claim 1, Lee teaches a connection structure of vias (see Fig. 1; see also Fig. 2), comprising:
multiple vias Via1, 45B, Via2, 45C (para [0027] - “…a plurality of second middle interconnections 45B, a plurality of third middle interconnections 45C, and a plurality of fourth middle interconnections 45D. The plurality of middle plugs 47 may include a plurality of first middle plugs 47A, a plurality of second middle plugs 47B, and a plurality of third middle plugs 47C”) disposed within an insulating layer 40 (para [0018] - “an interlayer insulating layer 40”),
wherein the multiple vias Via1, 45B, Via2, 45C comprise a first via Via1, 45B (para [0027] - “a plurality of second middle interconnections 45B”) and two or more second vias Via2, 45C (para [0027] - “a plurality of third middle interconnections 45C”) disposed in a vertically stacked relationship,
wherein the first via Via1, 45B and the two or more second vias Via2, 45C are configured to meet at a common surface (interface of Via2 and the plurality of middle interconnections 45B),
wherein the first via Via1, 45B comprises a first via hole (volume occupied by Via1) and a first via pad 45B connected to each other,
wherein the two or more second vias Via2, 45C are each disposed on the first via pad 45B in contact with the first via hole, and
wherein the two or more second vias Via2, 45C are arranged per one first via Via1, 45B (for every two first vias, there are four second vias = 2 to 1 ratio.) and are in contact with the first via pad 45B.
Regarding independent claim 3, Lee teaches a substrate (see Fig. 1; see also Fig. 2), comprising:
a through hole (occupied by a through electrode 39) extending through the substrate in a thickness direction;
a core substrate 21 or 21, 30 (para [0018] - “substrate 21, a lower insulating layer 30”) in which the through hole is formed;
a rewiring layer Via1, 45B, Via2, 45C, 47C, 45D, 40 (para [0027] - “…a plurality of second middle interconnections 45B, a plurality of third middle interconnections 45C, and a plurality of fourth middle interconnections 45D. The plurality of middle plugs 47 may include a plurality of first middle plugs 47A, a plurality of second middle plugs 47B, and a plurality of third middle plugs 47C; para [0018] - “an interlayer insulating layer 40”) formed on a first surface of the core substrate 21 or 21, 30; and
an electrically conductive layer 45, 39, 93, Via1, 45B, Via2, 45C, 47C, 45D having a predetermined shape and comprising a core conductive layer 45, 39, 93 (para [0018] - “through electrode 39…a plurality of middle interconnections 45…a protruding electrode 93”) and a rewiring conductive layer Via1, 45B, Via2, 45C, 47C, 45D embedded in the rewiring layer Via1, 45B, Via2, 45C, 47C, 45D, 40,
wherein the core conductive layer 45, 39, 93 comprises:
a first conductive layer 45A (para [0027] - “a first middle interconnection 45A”) disposed on the first surface of the core substrate 21 or 21, 30;
a through-hole conductive layer 39 disposed in the through hole extending through the core substrate 21 or 21, 30; and
a second conductive layer 93 (para [0018] - “protruding electrode 93”) disposed on a second surface of the core substrate 21 or 21, 30 opposite the first surface,
wherein the core conductive layer 45, 39, 93 is electrically connected to the rewiring conductive layer 45D, 47C, 45C, Via2, 45B, Via1, 40 comprising an insulating layer 40 (para [0021] - “interlayer insulating layer 40”) and a connection structure of vias 45D, 47C, 45C, Via2, 45B, Via1,
wherein the connection structure of vias 45D, 47C, 45C, Via2, 45B, Via1 comprises multiple vias Via1, 45B, Via2, 45C disposed in the insulating layer 40,
wherein the multiple vias Via1, 45B, Via2, 45C comprise a first via Via1, 45B (para [0027] - “a plurality of second middle interconnections 45B”) and two or more second vias Via2, 45C (para [0027] - “a plurality of third middle interconnections 45C”) disposed in a vertically stacked relationship,
wherein the first via Via1, 45B and the two or more second vias Via2, 45C are configured to meet at a common surface (interface of Via2 and the plurality of middle interconnections 45B),
wherein the first via Via1, 45B comprises a first via hole (volume occupied by Via1) and a first via pad 45B connected to each other,
wherein the two or more second vias Via2, 45C are each disposed on the first via pad 45B in contact with the first via hole, and
wherein the two or more second vias Via2, 45C are arranged per one first via Via1, 45B (for every two first vias, there are four second vias = 2 to 1 ratio.) and are in contact with the first via pad 45B.
Regarding claim 5, Lee teaches that the height of H2 (para [0042] - “The third height H3 may be greater than or equal to the second height H2. The third height H3 may range from about 0.5 μm to about 5 μm. For example, the third height H3 may be about 1.7 μm.”) that may range from about 0.5 to about 5 microns. Fig. 2 shows the spacing between the two or more second vias Via2 in contact with the first via pad 45B that is about the same as H2. Thus, Lee teaches the interval being greater than 0.2 micron (0.5 micron to about 5 micron).
Regarding claim 7, Lee teaches the two or more second vias Via2 that are disposed in a row on the first via Via1.
Regarding independent claim 10, Lee teaches a semiconductor comprising:
the substrate of claim 3 (see rejection of claim 3), and
a semiconductor element MC (para [0020] - “The memory cell MC”) mounted in the substrate.
Regarding independent claim 11, Lee teaches an electronic device substrate (see Fig. 1; see also Fig. 2), comprising:
through holes (occupied by each of the through electrodes 39; para [0072] - “a plurality of through electrodes 3) extending through the electronic device substrate in a thickness direction;
a core substrate 21 or 21, 30 (para [0018] - “substrate 21, a lower insulating layer 30”) in which the through holes are formed;
an upper rewiring layer Via1, 45B, Via2, 45C, 47C, 45D, 40 (para [0027] - “…a plurality of second middle interconnections 45B, a plurality of third middle interconnections 45C, and a plurality of fourth middle interconnections 45D. The plurality of middle plugs 47 may include a plurality of first middle plugs 47A, a plurality of second middle plugs 47B, and a plurality of third middle plugs 47C; para [0018] - “an interlayer insulating layer 40”) disposed on a first surface of the core substrate 21 or 21, 30,
wherein the electronic device substrate comprises an electrically conductive layer 45, 39, 93, Via1, 45B, Via2, 45C, 47C, 45D having a predetermined shape and comprising a core conductive layer 45, 39, 93 (para [0018] - “through electrode 39…a plurality of middle interconnections 45…a protruding electrode 93”) and configured to transmit electrical signals (interconnections and through electrode are reasonable capable of transmitting electrical signals),
wherein the electrically conductive layer is configured to electrically connect an upper portion of the core substrate 21 or 21, 30 and a lower portion of the core substrate 21 or 21, 30 through at least some of the through holes,
wherein the electrically conductive layer includes a rewiring conductive layer Via1, 45B, Via2, 45C, 47C, 45D comprising multiple vias configured to transmit electrical signals in an upward direction and a downward direction,
wherein the multiple vias Via1, 45B, Via2, 45C comprise a first via Via1, 45B (para [0027] - “a plurality of second middle interconnections 45B”) and two or more second vias Via2, 45C (para [0027] - “a plurality of third middle interconnections 45C”) disposed in a vertically stacked relationship,
wherein the first via Via1, 45B comprises a first via hole (volume occupied by Via1) and a first via pad 45B connected to each other,
wherein the two or more second vias Via2, 45C are each disposed on the first via pad 45B in contact with the first via hole, and
wherein the two or more second vias Via2, 45C are arranged per one first via Via1, 45B (for every two first vias, there are four second vias = 2 to 1 ratio.) and are in contact with the first via pad 45B.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
(1). Determining the scope and contents of the prior art.
(2). Ascertaining the differences between the prior art and the claims at issue.
(3). Resolving the level of ordinary skill in the pertinent art.
(4). Considering objective evidence present in the application indicating obviousness or nonobviousness.
In an alternate ground of rejection, claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Lee.
Regarding claim 5, Lee teaches a general condition of an interval between the two or more second vias in contact with the first pad that is in a micron range (para [0042]), but does not specify that the interval is equal to or greater than 0.2 micron.
The only difference between the claimed substrate and the substrate by Lee is a specific condition of the interval of being equal to or greater than 0.2 micron.
However, according to Section 2144.05 of the MPEP, "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F. 2d 454, 456, 105 USPQ 233, 235 (CCPA 1955).
Here, Lee teaches a general condition of the two or more second vias having an interval. Unless the Applicant can show that the claimed specific condition of a the interval of being equal to or greater than 0.2 micron produces unexpected results that are different in kind and not different in degree over said general condition as taught by Lee, claim 5 would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, because it would not be inventive to discover the optimum or workable ranges by routine experimentation.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Lee.
Regarding claim 6, Lee teaches a general condition of the two or more second vias having a size in the micron range (para [0042]), but does not specify that the size is between 10 micron and 100 micron.
The only difference between the claimed substrate and the substrate by Lee is a specific condition of the size that is between 10 micron and 100 micron.
However, according to Section 2144.05 of the MPEP, "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F. 2d 454, 456, 105 USPQ 233, 235 (CCPA 1955).
Here, Lee teaches a general condition of the two or more second vias having a size. Unless the Applicant can show that the claimed specific condition of the size being between 10 micron to 100 micron produces unexpected results that are different in kind and not different in degree over said general condition as taught by Lee, claim 6 would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, because it would not be inventive to discover the optimum or workable ranges by routine experimentation.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Lee and further in view of examiner’s assertion of official notice.
Regarding claim 9, Lee teaches the core substrate 21 that comprises a silicon substrate (para [0020] - “The substrate 21 may include a semiconductor substrate such as a single crystalline silicon wafer.”).
Lee does not disclose that the core substrate 21 comprises glass substrate.
Examiner asserts an official notice of the fact that glass and silicon are well-known materials that can form core substrate 21.
That is, the semiconductor art recognizes that both silicon and glass are functional equivalents when it comes to serving as a core substrate.
According to Section 2144.06.II, "In order to rely on equivalence as a rationale supporting an obviousness rejection, the equivalency must be recognized in the prior art" In re Ruff, 256 F.2d 590, 118 USPQ 340 (CCPA 1958).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to modify the substrate of Lee by substituting silicon substrate by another functionally-equivalent glass substrate as "An express suggestion to substitute one equivalent component or process for another is not necessary to render such substitution obvious. In re Fout, 675 F.2d 297, 213 USPQ 532 (CCPA 1982) (see Section 2144.06.II).
B. Prior-art rejections based on Liao
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1 and 2 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Pub. No. US 2024/0072442 to Liao ("Liao").
Fig. 25 of Liao has been annotated to support the rejection below:
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Regarding independent claim 1, Liao teaches a connection structure of vias (see Fig. 25 for example), comprising:
multiple vias disposed within an insulating layer 112, 122 (para [0022] - “In some embodiments, the dielectric layer 132 may be formed using processes and materials similar to those discussed above with respect to the dielectric layer 112 and/or dielectric layer 122.”; para [0016] - “n some embodiments, the dielectric layer 112 is formed of a polymer, such as polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), or the like. In other embodiments, the dielectric layer 112 is formed of a nitride such as silicon nitride; an oxide such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), or the like; or the like.”; para [0020] - “In some embodiments, the dielectric layer 122 is formed of a polymer, which may be a photo-sensitive material such as PBO, polyimide, BCB, or the like, that may be patterned using a lithography mask. In other embodiments, the dielectric layer 122 is formed of a nitride such as silicon nitride; an oxide such as silicon oxide, PSG, BSG, BPSG; or the like.”),
wherein the multiple vias 116, 114, 126, 124 (para [0016] - “first metallization pattern 116…The first metallization pattern 116 may penetrate through the dielectric layer 112 using through vias 114…”; para [0021] - “The through vias 124 and second metallization pattern 126 may be formed using processes and materials similar to those described above with respect to the through vias 114 and the first metallization pattern 116.”) comprises a first via 116, 114 and two or more second vias 126, 124 disposed in a vertically stacked relationship with the first via 116, 114,
wherein the first via 116, 114 and the two or more second vias 126, 124 are configured to meet at a common surface,
wherein the first via 116, 114 comprises a first via hole (of 114) and a first via pad 116 connected to each other,
wherein the two or more second vias 126, 124 are each disposed on the first via pad 116 in contact with the first via hole 114, and
wherein the two or more second vias 126, 124 are arranged per one first via 116, 114 and are in contact with the first via pad 116.
Regarding claim 2, wherein clause of "wherein the multiple vias are configured to transmit electrical signals in an upward direction and a downward direction" implies a structure in view the ends of the multiple vias are electrically connected to electrical elements above and below the multiple vias. Liao teaches the multiple vias that electrically connect the semiconductor chip 50A and/or 50B to the external second connectors 178. Thus, Liao teaches all of the structural limitations, including the implied structure, recited in the wherein clause above.
Allowable Subject Matter
The following is a statement of reasons for the indication of allowable subject matter:
Claim 8 is objected to for depending on a rejected base claim 3, but would be allowable if it is rewritten in independent form to include all of the limitations of the base claim 3 or the base claim 3 is amended to include all of the limitations of claim 8.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL JUNG whose telephone number is (408) 918-7554. The examiner can normally be reached 8:30 A.M. to 7 P.M.
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/MICHAEL JUNG/Primary Examiner, Art Unit 2817 16 January 2026