DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
Applicant’s cancellation of claims 21-26, and submission of new claims 27-28 in “Claims - 11/18/2025” is acknowledged.
However, as the new claim 28 depends on previously withdrawn claim 19, the claim 28 is considered as withdrawn as well.
This office action considers claims 1-20 and 27-28 are pending for prosecution, of which, claims 3, 10, 13,19-20 and 28 had been withdrawn, and claims 1-2, 4-9, 11-12, 14-18 and 27 are presented for further examination.
Response to Arguments
Applicant's arguments in “Remarks - 11/18/2025 - Applicant Arguments/Remarks Made in an Amendment”, have been fully considered, but they are not persuasive.
Firstly, it is noted that the features upon which applicant relies i.e. “invention are directed to reflow techniques for depositing superconducting interconnects at ambient temperatures that are below the melting tempe rature of the superconducting metal” (remarks on page 8); these limitations are not recited in any one of the rejected claims 1-2, 4-9, 11-12, 14-18, and cannot be considered as limitations unless those are recited in the claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993). It is noted with emphasis that instant claims are device claim, whereas applicant erroneously cited method steps to discredit the features of the instant office action.
Secondly, Applicant’s conceding that Luu describes [0030] the new deposition chamber "can be equipped with bakeout lamps that maintain the chamber and target at an elevated temperature when the chamber is in an idle state". At most this implies that the metal deposition occurs at "an elevated temperature" that can then be maintained, and it could be implied that this "elevated temperature" is at least above 160 degrees” is sufficient to teach that is less than the second superconducting metal ([0026] aluminum for layer 74 having melting points in [0026] is 1100 degree Celsius) than a melting temperature of the second superconducting metal (74) in claim 1 or comparative matrices in claims 8-9. It is to be noted that the prior art description i.e., ipsis verbis, such as elevated temperature is not required to understand the low temperature (See Vas-Cath, 935 F.2d at 1563, 19 USPQ2d at 1116; Martin v. Johnson, 454 F.2d 746, 751, 172 USPQ 391, 395 (CCPA 1972). Moreover, Examiners would like to note that MPEP § 2141.02. VI “A prior art reference must be considered in its entirety, i.e., as a whole, W.L. Gore & Associates, Inc. v. Garlock, Inc., 721 F.2d 1540, 220 USPQ 303 (Fed. Cir. 1983), cert. denied, 469 U.S. 851 (1984). Therefore, ess than the second superconducting metal ([0026] aluminum for layer 74 having melting points in [0026] is 1100 degree Celsius) than a melting temperature of the second superconducting metal (74) in claim 1 or comparative matrices in claims 8-9 less than melting point of (128 Fig 1A-1B) met the claimedl requirement. Please note that MPEP 2131.03 “[W]hen, as by a recitation of ranges or otherwise, a claim covers several compositions, the claim is ‘anticipated’ if one of them is in the prior art.” Titanium Metals Corp. v. Banner, 778 F.2d 775, 227 USPQ 773 (Fed. Cir. 1985) (citing In re Petering, 301 F.2d 676, 682, 133 USPQ 275, 280 (CCPA 1962)) (emphasis in original). .
As Applicant’s other arguments are also based on the patentability of claim 1, no further response is put forward, other than the Office Action’s diligent effort to present examiner's position why elected claims (1-2, 4-9, 11-12, 14-18 and 2) are not patentable as described in sections I-III, Infra.
Claim Rejections - 35 USC § 112 (2026-01-20)
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claim 27 is rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
Regarding claim 27, the instant claim recites limitation in view of claim 1, where in claim 17 recites “wherein depositing a second superconducting metal comprises depositing a layer of the second superconducting metal onto a top surface of the dielectric layer such that at least a portion of the layer of second superconducting metal has sufficient mobility to flow from the top surface of the dielectric layer into the opening to fill at least a portion of the opening." (claim 27, lines 1-5). There is insufficient antecedent basis for this limitation in the claim for “wherein depositing a second superconducting metal” (claim 27, line 1-2) in the claim. Appropriate clarification and/or correction are/is required. It is noted that the claim parent claim 1 recites “depositing a second superconducting metal” (claim 1; Line 12). It is unclear whether the second recited “depositing a second superconducting metal” (claim 27, line 1-2) was intended to relate back to “depositing a second superconducting metal” (claim 1, line 12) or to set forth an additional ”depositing a second superconducting metal “ (claim 27, line 1-2). Clarification and/or correction are/is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Notes: when present, semicolon separated fields within the parenthesis (; ;) represent, for example, as (56; Fig 2A; [0033]) = (element 56; Figure No. 2A; Paragraph No. [0033]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. These conventions are used throughout this document.
Claims 1, 2, 4-5, 7-9,11-12 and 27 are rejected under 35 U.S.C. 102(a) (1) as being anticipated by LUU; VIVIEN et al. (US 20180337138 A1; of record) hereinafter Luu’138.
1. Luu’138 teaches a method of forming a superconducting integrated circuit for a quantum processor, the method comprising (see the entire document figs 1 to 8; [0032+), specifically as cited below):
depositing a first superconducting metal (56; Fig 2A; [0033]) to form a first superconducting metal layer that overlies at least a portion of a substrate (52), the first superconducting metal layer (56) comprising an upper surface (top surface of 56 not covered by 64) having a first region;
depositing a dielectric layer (58) to cover the first region of the first superconducting metal layer ;
patterning (Fig 2B) the dielectric layer (58) to expose at least a portion of the first region of the first superconducting metal layer (56) and form an opening (60) having sides defined by the dielectric layer (58) and a bottom defined by the exposed at least a portion of the first region of the first superconducting metal layer (56); and
depositing a second superconducting metal (74 comprising {70,72}; Fig 7; [0040]) for at an ambient temperature that is less (construed from Luu’138 disclosing that first and second superconducting layers (18,24 Fig 1 ; [0031]) are embedded in the first and the second dielectric layers 14 and 18 that is being formed of a low temperature dielectric material that can be employed in low temperatures (e.g., less than or equal to 160 degrees Celsius; in view of that superconducting layers must be within less than or equal to 160 degrees Celsius; whereas melting points of superconducting layers as cited in [0026] aluminum is 1100 degree Celsius) than a melting temperature of the second superconducting metal (74) such that the second superconducting metal fills the opening ([0004]) to form a connect (70) that conductively contacts the at least a portion of the first region of the first superconducting metal layer (56) and forms a second superconducting metal layer (72) that overlies the dielectric layer (58) and the connect (70).
2. The method of claim 1, Luu’138 further teaches (the method) further comprising depositing (Fig 5; [0040]) an adhesion layer (70) to line at least the sides of the opening (60) prior to depositing the second superconducting metal (72).
4. The method of claim 1, Luu’138 further teaches (the method) further comprising planarizing (Fig 8; [0040]) the second superconducting metal layer.
5. The method of claim 4, Luu’138 further teaches, wherein planarizing the second superconducting metal layer ([0040]) comprises chemical-mechanical polishing (CMP).
7. The method of claim 1, Luu’138 further teaches, wherein depositing a second superconducting metal comprises depositing aluminum ([0026]).
8. The method of claim 7, Luu’138 further teaches, wherein depositing a second superconducting metal at an ambient temperature that is less than a melting temperature of the second superconducting metal comprises depositing at an ambient temperature that is less than 650°C (construed from claim 1 rejection 1).
9. The method of claim 8, Luu’138 further teaches, wherein depositing a second superconducting metal at an ambient temperature that is less than a melting temperature of the second superconducting metal comprises depositing at an ambient temperature that is between 100°C and 520°C (construed from claim 1 rejection 1).
11. The method of claim 7, Luu’138 further teaches, wherein depositing the second superconducting metal (74) comprises depositing aluminum by physical vapor deposition (PVD) ([0022]).
12. The method of claim 7, Luu’138 further teaches, wherein depositing the first superconducting metal (55) comprises depositing aluminum ([0026]).
27.The method of claim 1, Luu’138 further teaches, wherein depositing a second superconducting metal ([0026] aluminum for layer 74 comprising {70,72}; Fig 7; [0040]) comprises depositing a layer of the second superconducting metal (74) onto a top surface of the dielectric layer (58 overlying 56; fig 7) such that at least a portion of the layer of second superconducting metal (portion of 74 overlying 58) has sufficient mobility to flow from the top surface of the dielectric layer (74 overlying 58) into the opening (60,66; Fig 3) to fill (depicted in Fig 7 and described in [0040] as “final superconducting layers 74 are deposited to form the resultant structure of FIG. 7. Following deposition of the contact material fill, the superconducting material 74 is placed into a polish platen 120 and is polished via chemical mechanical polishing (CMP) down to the surface level of the dielectric layer 58 to form a first contact 76, a second conductive line 78, a second contact 80, and a third conductive contact 82 that form part of the metal interconnects and provide the resultant structure of FIG. 8 ) at least a portion of the opening (60,66; Fig 3).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over LUU; VIVIEN et al. (US 20180337138 A1; of record) hereinafter Luu’138; in view of Renzas; James Russell M et al., (US 11276727 A1; of record) hereinafter Renzas.
6. The method of claim 1, while Luu’138 further teaches, wherein patterning the dielectric layer to form an opening comprises patterning the dielectric layer to form an opening (60), but is silent on “a dimension of greater than 0.1 micron”.
However, in the analogous art, Renzas teaches a fabricating superconducting via (Col 1, Line 16-17), wherein (Col 25, Line 65-66) the metal or multi-layer metal stack in the via has a thickness between approximately 100 nanometers (nm) and one (1) micrometer (μm);
Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to configure Luu’138 opening as per Renzas, and thereby, the combination will have an opening (60) with “a dimension of greater than 0.1 micron ,since this configuration, at least, bring the near-zero resistance (Renzas Col 26 line 6-7) See MPEP 2144.05, I.
Claims 14-18 are rejected under 35 U.S.C. 103 as being unpatentable over LUU; VIVIEN et al. (US 20180337138 A1) hereinafter Luu’138; in view of Lanting; Trevor M et al., (US 20200152851 A1) hereinafter Lanting.
14. The method of any one of claim 1, Luu’138 does not expressly disclose (the method), further comprising:
after depositing the first superconducting metal layer (56; Fig 2A), patterning the first superconducting metal layer (56) to form an additional opening);
depositing an additional dielectric layer to fill the additional opening; and
depositing the dielectric layer to cover the first region of the first superconducting metal layer and a top surface of the additional dielectric layer.
Nevertheless, in the analogous art, Lanting teaches fabricating superconducting integrated circuits that include a set of wiring layers ([0001]), wherein (Fig 1A-1H; [0021, [0059+]) after depositing the first superconducting metal layer (104; 1A; [0060]), patterning the first superconducting metal layer (104; Fig 1B; [0061]) to form an additional opening 106;
depositing an additional dielectric layer (106; [0061]) to fill the additional opening; and
depositing the dielectric layer (108; Fig 1C; [0062]) to cover the first region of the first superconducting metal layer and a top surface of the additional dielectric layer.
Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to configure Luu’138 as per Lanting, and thereby, the combination will have process steps as claimed, since this configuration, at least, reduces noise in superconducting devices (Lanting [0001]) as ince noise is a serious concern to the operation of quantum computers, measures should be taken to reduce noise wherever possible ([0007]).
15. The method of claim 14, the combination of Luu’138 and Lanting) further teaches (the method), further comprising (Lanting [0061]):
prior to patterning the first superconducting metal layer, depositing a polish stop layer over the at least a portion of the first superconducting metal layer; and wherein patterning the first superconducting metal layer further comprises patterning the first superconducting metal layer and the polish stop layer.
16. The method of claim 15, the combination of Luu’138 and Lanting) further teaches (the method), further comprising (Lanting [0023]):
after depositing the additional dielectric layer to fill the additional opening,
planarizing the additional dielectric layer to have a top surface level with a top surface of the polish stop layer; and removing the polish stop layer.
17. The method of claim 16, the combination of Luu’138 and Lanting) further teaches (the method), further comprising (Lanting ; Fig 1D; [0063]):
depositing a second polish stop layer over at least a portion of the second superconducting metal layer;
patterning the second polish stop layer and the second superconducting metal layer to form a third opening; and
depositing a third dielectric layer to fill the third opening.
18. The method of any one of claim 1, the combination of Luu’138 and Lanting) further teaches (the method), further comprising (Lanting [0110]) depositing a superconducting barrier layer overlying the second superconducting metal layer and patterning the second superconducting metal layer and the superconducting barrier layer.
Conclusion
THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOAZZAM HOSSAIN whose telephone number is (571)270-7960. The examiner can normally be reached on M-F: 8:30AM - 6:00 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio J. Maldonado can be reached on 571-272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MOAZZAM HOSSAIN/Primary Examiner, Art Unit 2898
January 20, 2026