DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Status
The amendments to claim 1 received on 26 January 2026 are acknowledged. Claims 2 and 3 were previously cancelled.
Claim Objections
Claim 1 objected to because of the following informalities: The article --A-- is missing before the word --(t)ransistor-- in the claim preamble.
Similarly, claims 4-10 are objected to because the article --the-- is missing before the word --(t)ransistor-- in each claim preamble.
Claim 11 is objected to because the article --A-- is missing before the word –(m)ethod-- in the claim preamble.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
Claims 9 and 10 are rejected under 35 U.S.C. 112(a) as failing to comply with the written description requirement. The claims contain subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor had possession of the claimed invention. The inclusion of the limitations “...a second electrically-conductive layer made of a metal or a metal alloy coating at least one of the sides of said gate region, wherein the second layer coats the side of the gate region located in the direction of the first electrode and further extends, on top and in contact with the upper surface of the silicon nitride layer, all the way to the first electrode” in claim 1, introduces new matter to claims 9 and 10 that is not described in the specification. Claim 9 adds the second layer coating the side of the gate region located in the direction of the second electrode, and claim 10 adds a step in cross-section view, neither of which is taught in combination with the above claim 1 limitations.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1,and 4-11 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
Claim 1 recites the limitation --the first layer-- in its third paragraph, claims 4-5 recite --the first layer—in their first line, claim 6 recites --the first layer—in its second line, and claim 7 recites --the first layer—at the end. There is insufficient antecedent basis for this limitation in the claim. For the purpose of examination, the limitation will be read as --the first gallium nitride layer--.
Claim 1 recites the limitation --the second layer-- in its last paragraph, and claim 9 recites --the second layer-- in its first line. There is insufficient antecedent basis for this limitation in the claim. For the purpose of examination, the limitation will be read as --the second electrically-conductive layer--.
Claims 8, 10, and 11 are rejected due to their dependency on claim 1.
Allowable Subject Matter
Claims 1 and 4-8, and 11 are allowed, contingent upon resolution of the 112(b) rejections identified above.
The following is an examiner’s statement of reasons for allowance, which paraphrases and summarizes the claimed invention without intending the be limiting, wherein the legally defined scope of the claimed invention is defined by the allowed claims themselves in view of the written description under 35 USC 112:
Regarding Claim 1 – The prior art pertinent to the instant application and known to the examiner does not teach nor render obvious the subject matter: “(A t)ransistor comprising: a first gallium nitride layer coated by an aluminum-gallium nitride layer and by a silicon nitride layer; a gate region penetrating into the first gallium nitride layer,... a second electrically-conductive layer made of a metal or a metal alloy coating at least one of the sides of said gate region,... wherein the second (electrically-conductive) layer coats the side of the gate region located in the direction of the first electrode and further extends... all the way to the first electrode.”
Claims 4-8, and 11 are allowable due to their dependency on claim 1.
Relevant Prior Art
Lei et al (US 20210335778 A1, hereinafter “Lei”)
Mishra et al (US 20200119179 A1, hereinafter “Mishra”)
Kawai et al (US 20140239311 A1, hereinafter “Kawai”)
Tsuchiya et al (JP 2017073525 A, hereinafter “Tsuchiya”)
Lei teaches a transistor that “...may include an electrode component formed in ... at least one trench. The electrode component may include an electrode. The electrode may ... be connected to the source terminal of the transistor... The electrode component may be separated from the gate terminal in the trench. ... The electrode component may be in contact with a sidewall of the trench.” [0042, 0044]
Mishra teaches “…(T)he average sidewall angle α of the III-N body layer 17 in the gate region 81 relative to the top surface of III-N channel layer 16 (opposite the substrate) is <90°, for example between 20°-80°, e.g., 30°-80°…” (Mishra Fig. 5, [0094]) The angle (α) presented in Mishra can be compared with the angle (a) in the instant application by subtracting from 90°. This means Mishra suggested 10° to 60° when compared with the instant application. The angle is chosen along with the thicknesses of GaN and AlGaN layers to achieve the desired net polarization charge and resulting threshold voltage (Mishra [0094]). Furthermore, Mishra teaches the inclusion of a p-type layer sandwiched between other III-N layers (e.g. GaN) to help determine and control threshold voltage (Mishra [0062]).
Kawai discloses a transistor wherein ”...n-type high-concentration impurity regions NP1 and NP are formed on a side surface portion of the trench T on the source electrode SE side and on a side surface portion of the trench T on the drain electrode DE side, and the n-type high-concentration impurity region NP1 on the source electrode SE side of the trench T is extended to reach a portion below the source electrode SE. In this manner, not only the on resistance of the recess edge portion on the source electrode side can be reduced but also an ohmic-access resistance of the source electrode can be reduced by a simultaneous process.” [0257]
Tsuchiya teaches “…the contact resistance can be reduced because the 2DEG layer and … layers 9 and 10 overlap each other.” [0062]
No prior art reference or combination of references appears to teach “...a second electrically conductive layer made of a metal or a metal alloy coating at least one of the sides of said gate region,... wherein the second (electrically-conductive) layer coats the side of the gate region located in the direction of the first electrode and further extends... all the way to the first electrode.” (Claim 1)
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JASON MCDONALD whose telephone number is (571) 272-5944. The examiner can normally be reached M-F 7:30a-5p Eastern, alternating Fridays out of office.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at (571) 272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/JASON MCDONALD/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898