DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The abstract of the disclosure is objected to because it refers to purported merits or speculative applications of the invention (see line: “Through the application… are realized.”) . A corrected abstract of the disclosure is required and must be presented on a separate sheet, apart from any other text. See MPEP § 608.01(b).
The disclosure is objected to because of the following informalities:
[0047] appears to be out of place with the description of Figures
[0067] "8-bite"
[0076] "16bits"
[0077] "buffer and sued"
[0018], [0081], [0085], formula quality raises legibility issues for reproduction (see C.F.R. 1.52(a)(1)(iv)).
Appropriate correction is required.
The specification is objected to as failing to provide proper antecedent basis for the claimed subject matter. See 37 CFR 1.75(d)(1) and MPEP § 608.01(o). Correction of the following is required: Claim 1 recites “Master Control Reset”, “Collection Due Process”, and “rectified linear unit”, and thereby claims 2-8,10 inherit the deficiencies by reasons of dependence. The disclosure does not appear to describe the “Master Control Reset” and “Collection Due Process” as explicitly an MCR instruction and a CDP instruction, which renders the specification inconsistent with the claims.
The use of the term ARM Cortex-M, which is a trade name or a mark used in commerce, has been noted in this application. The term should be accompanied by the generic terminology; furthermore the term should be capitalized wherever it appears or, where appropriate, include a proper symbol indicating use in commerce such as ™, SM , or ® following the term.
Although the use of trade names and marks used in commerce (i.e., trademarks, service marks, certification marks, and collective marks) are permissible in patent applications, the proprietary nature of the marks should be respected and every effort made to prevent their use in any manner which might adversely affect their validity as commercial marks.
Claim Objections
Claim 4 is objected to because of the following informalities: the claim contains a formula with low quality which raises legibility issues for reproduction as similarly discussed in the specification section. Claim 4 further recites the limitation “wherein e is natural constant in mathematics”. However, the formula recited in claim 4 does not appear to contain “e”. Appropriate correction is required.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier.
Such claim limitations are: “instruction set setting module” and “instruction set execution module” in claim 9.
The term “module” has been interpreted as a generic placeholder. See MPEP 2181.I.A.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 9 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 9 recites the “instruction set setting module” and “instruction set execution module”.
These limitations invoke 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. However, the written description fails to provide adequate written description of the corresponding structure, material, or acts for performing the entire claimed functions of these limitations. See rejection under 35 U.S.C. 112(b) below for further details as to the requirement for the written description.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-10 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim limitations “instruction set setting module” and “instruction set execution module” invoke 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. However, the written description fails to disclose the corresponding structure, material, or acts for performing the entire claimed function and to clearly link the structure, material, or acts to the function.
As to the “instruction set setting module” in claim 9, this module is merely described in ([0035-0036], [0051], [0119-0120], [0122-0123]). However, these description describe functional operations of the module, and no algorithm could be found in the specification. In the drawings, this module is merely illustrated as a black box, “51” in Fig. 5. Thus, there is insufficient structure to perform the claimed functions.
As to the “instruction set execution module” in claim 9, this module is merely described in ([0035], [0037], [0051], [0119], [0121-0123]). However, these description describe functional operations of the module, and no algorithm could be found in the specification. In the drawings, this module is merely illustrated as a black box, “52” in Fig. 5. Thus, there is insufficient structure to perform the claimed functions.
Therefore, the claim is indefinite and is rejected under 35 U.S.C. 112(b) or pre-AIA 35 U.S.C. 112, second paragraph.
Applicant may:
(a) Amend the claim so that the claim limitation will no longer be interpreted as a limitation under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph;
(b) Amend the written description of the specification such that it expressly recites what structure, material, or acts perform the entire claimed function, without introducing any new matter (35 U.S.C. 132(a)); or
(c) Amend the written description of the specification such that it clearly links the structure, material, or acts disclosed therein to the function recited in the claim, without introducing any new matter (35 U.S.C. 132(a)).
If applicant is of the opinion that the written description of the specification already implicitly or inherently discloses the corresponding structure, material, or acts and clearly links them to the function so that one of ordinary skill in the art would recognize what structure, material, or acts perform the claimed function, applicant should clarify the record by either:
(a) Amending the written description of the specification such that it expressly recites the corresponding structure, material, or acts for performing the claimed function and clearly links or associates the structure, material, or acts to the claimed function, without introducing any new matter (35 U.S.C. 132(a)); or
(b) Stating on the record what the corresponding structure, material, or acts, which are implicitly or inherently set forth in the written description of the specification, perform the claimed function. For more information, see 37 CFR 1.75(d) and MPEP §§ 608.01(o) and 2181.
Claim 1 recites “a convolutional neural network acceleration method based on a Cortex-M processor”. However, the metes and bounds of this limitation are indefinite. It is indefinite as to whether the recited neural network is based on a Cortex-M processor, or whether the manner of acceleration is based on a Cortex-M processor. For example, it is indefinite as to whether "based on" means that the accelerating (or the convolutional neural network) is implemented on a Cortex-M processor, or whether "based on" means that there are aspects of the accelerating (or the convolutional neural network) that are similar to accelerating (or a convolutional neural network) of a Cortex-M processor; in the latter case, it is indefinite as to what level of similarity would be required for the "based on" language to be apt. For example, the metes and bounds of a Cortex-M processor are indefinite, given that the metes and bounds of this limitation may change if new Cortex-M processors are introduced. For example, it is indefinite as to whether a processor that is exactly the same as a Cortex-M processor, but which is not (or no longer) branded as a "Cortex-M" processor, would meet the "Cortex-M" processor limitation. For example, it is indefinite as to whether a processor that is essentially the same as a Cortex-M processor, but which is not branded as a "Cortex-M" processor, would meet the "Cortex-M" processor limitation; if so, it is indefinite as to what the essentials of a Cortex-M processor are, the presence of which would contribute to the “essentially the same” designation.
Claim 1 further recites the limitation "setting a Master Control Reset (MCR) instruction and a Collection Due Process (CDP) instruction according to common basic operators of a convolutional neural network, wherein the common basic operators comprise a convolution operator, a rectified linear unit (Relu) activation operator, a pooling operator, a table look-up operator and a quantization operator" in lines 4-8. However, the metes and bounds of this limitation are indefinite. For example, it is indefinite as to what it means "setting" MCR instructions and CDP instructions. For example, it is indefinite as to whether the limitation entails setting MCR instructions alongside setting operators of the convolutional neural network, or whether setting MCR instructions entails setting operators of the convolutional neural network, or whether some other relationship is the case. For example, it is indefinite as to whether the limitation entails setting a CDP instruction alongside setting operators of the convolutional neural network, or whether setting a CDP instruction entails setting operators of the convolutional neural network, or whether some other relationship is the case. For example, it is indefinite as to whether the operators of the convolutional neural network are "set" or not.
Claim 1 further recites the limitation “according to common basic operators”. However, it is indefinite as to the criteria by which an operator (or a basic operator) would be considered “common”. Similarly, it is indefinite as to the criteria by which an operator (or a common operator) would be considered to be “basic”.
Claim 1 further recites the limitation “enabling the common basic operators of the convolutional neural network through the CDP instruction”. However, it is indefinite as to what it means to enable the common basic operators.
Claims 2-8, 10 inherit the deficiency by reasons of dependence, and are similarly rejected.
Claim 3 recites the limitation “a first register, a second register, a scale register, a control register”. However, the metes and bounds of this limitation are indefinite as it is unclear how “configuring the internal register through the MCR instruction” can itself comprise configuring multiple registers (a first register, a second register, a scale register, a control register).
Claim 3 further recites the limitation “a first MCR instruction”. However, the metes and bounds of this limitation are indefinite as it is unclear how “configuring the internal register through the MCR instruction” can itself comprise configuring multiple instructions (a first MCR instruction).
Claim 3 further recites the limitation “enabling the convolution operator”. However, it is indefinite as to what it means to “enable” the convolution operator.
Claim 4 recites the limitation “a first register, a second register, a scale register”. However, the metes and bounds of this limitation are indefinite as it is unclear how “configuring the internal register through the MCR instruction” can itself comprise configuring multiple registers (a first register, a second register, a scale register).
Claim 4 further recites the limitation “a second MCR instruction”. However, the metes and bounds of this limitation are indefinite as it is unclear how “configuring the internal register through the MCR instruction” can itself comprise configuring multiple instructions (a second MCR instruction).
Claim 4 further recites the limitation “enabling the Relu activation operator”. However, it is indefinite as to what it means to “enable” the Relu activation operator.
Claim 5 recites the limitation “a first register, a second register, a third register, a scale register”. However, the metes and bounds of this limitation are indefinite as it is unclear how “configuring the internal register through the MCR instruction” can itself comprise configuring multiple registers (a first register, a second register, a third register, a scale register).
Claim 5 further recites the limitation “a third MCR instruction”. However, the metes and bounds of this limitation are indefinite as it is unclear how “configuring the internal register through the MCR instruction” can itself comprise configuring multiple instructions (a third MCR instruction).
Claim 5 further recites the limitation “enabling the pooling operator”. However, it is indefinite as to what it means to “enable” the pooling operator.
Claim 6 recites the limitation “a first register, a second register, a scale register”. However, the metes and bounds of this limitation are indefinite as it is unclear how “configuring the internal register through the MCR instruction” can itself comprise configuring multiple registers (a first register, a second register, a scale register).
Claim 6 further recites the limitation “a fourth MCR instruction”. However, the metes and bounds of this limitation are indefinite as it is unclear how “configuring the internal register through the MCR instruction” can itself comprise configuring multiple instructions (a fourth MCR instruction).
Claim 6 further recites the limitation “enabling the table look-up operator”. However, it is indefinite as to what it means to “enable” the table look-up operator.
Claim 7 recites the limitation “a first register, a second register, a scale register”. However, the metes and bounds of this limitation are indefinite as it is unclear how “configuring the internal register through the MCR instruction” can itself comprise configuring multiple registers (a first register, a second register, a scale register).
Claim 7 further recites the limitation “a second MCR instruction”. However, the metes and bounds of this limitation are indefinite as it is unclear how “configuring the internal register through the MCR instruction” can itself comprise configuring multiple instructions (a second MCR instruction).
Claim 7 further recites the limitation “enabling the quantization operator”. However, it is indefinite as to what it means to “enable” the quantization operator.
Claim 8 recites the limitation “configuring a main memory address to a first register”, “configuring a local buffer address to a second register”, and “configuring stride block information to a scale register”. However, it is indefinite as to what it means to “configure” the respective addresses to their corresponding registers.
Claim 8 further recites the limitation “enabling a data reading operation”. However, it is indefinite as to what it means to “enable” the data reading operation.
Claim 8 further recites the limitation “enabling a data writing operation”. However, it is indefinite as to what it means to “enable” the data writing operation.
Claim 10 recites “the convolutional neural network acceleration method based on a Cortex-M processor”. However, the metes and bounds of this limitation are indefinite for the reasons stated with respect to claim 1.
Claim 9 recites “a convolutional neural network acceleration system based on a Cortex-M processor”. However, the metes and bounds of this limitation are indefinite. It is indefinite as to whether the recited neural network is based on a Cortex-M processor, or whether the manner of acceleration is based on a Cortex-M processor. For example, it is indefinite as to whether "based on" means that the accelerating (or the convolutional neural network) is implemented on a Cortex-M processor, or whether "based on" means that there are aspects of the accelerating (or the convolutional neural network) that are similar to accelerating (or a convolutional neural network) of a Cortex-M processor; in the latter case, it is indefinite as to what level of similarity would be required for the "based on" language to be apt. For example, the metes and bounds of a Cortex-M processor are indefinite, given that the metes and bounds of this limitation may change if new Cortex-M processors are introduced. For example, it is indefinite as to whether a processor that is exactly the same as a Cortex-M processor, but which is not (or no longer) branded as a "Cortex-M" processor, would meet the "Cortex-M" processor limitation. For example, it is indefinite as to whether a processor that is essentially the same as a Cortex-M processor, but which is not branded as a "Cortex-M" processor, would meet the "Cortex-M" processor limitation; if so, it is indefinite as to what the essentials of a Cortex-M processor are, the presence of which would contribute to the “essentially the same” designation.
Claim 9 further recites the limitation "setting a MCR instruction and a CDP instruction according to common basic operators of a convolutional neural network, wherein the common basic operators comprise a convolution operator, a Relu activation operator, a pooling operator, a table look-up operator and a quantization operator" in lines 19-22. However, the metes and bounds of this limitation are indefinite. For example, it is indefinite as to what it means "setting" MCR instructions and CDP instructions. For example, it is indefinite as to whether the limitation entails setting MCR instructions alongside setting operators of the convolutional neural network, or whether setting MCR instructions entails setting operators of the convolutional neural network, or whether some other relationship is the case. For example, it is indefinite as to whether the limitation entails setting a CDP instruction alongside setting operators of the convolutional neural network, or whether setting a CDP instruction entails setting operators of the convolutional neural network, or whether some other relationship is the case. For example, it is indefinite as to whether the operators of the convolutional neural network are "set" or not.
Claim 9 further recites the limitation “MCR” in line 19. However, the metes and bounds of this limitation are indefinite. For example, if “MCR” is an acronym, it is indefinite as to what this acronym stands for.
Claim 9 further recites the limitation “CDP” in line 19. However, the metes and bounds of this limitation are indefinite. For example, if “CDP” is an acronym, it is indefinite as to what this acronym stands for.
Claim 9 further recites the limitation “according to common basic operators”. However, it is indefinite as to the criteria by which an operator (or a basic operator) would be considered “common”. Similarly, it is indefinite as to the criteria by which an operator (or a common operator) would be considered to be “basic”.
Claim 9 further recites the limitation “enables the common basic operators of the convolutional neural network through the CDP instruction”. However, it is indefinite as to what it means to enable the common basic operators.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claim 10 is rejected under 35 U.S.C. 101 because the claimed invention is directed to non-statutory subject matter. The claim does not fall within at least one of the four categories of patent eligible subject matter because the claims encompass signals and other transitory forms of signal transmission. Examiner suggests to amend claim 10 to recite “non-transitory” to ensure the claims do not encompass signals and other transitory forms of signal transmission. Similarly, Applicant is advised to ensure such amendment has literal antecedent basis from the specification.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-10 are rejected under 35 U.S.C. 103 as being unpatentable over US 20200110607 A1 Croxford et al. (hereinafter “Croxford”) in view of "Arm Cortex-M33 Devices Generic User Guide". Revision: r0p4. Generic User Guide. Copyright © 2017, 2018 Arm Limited or its affiliates. pp. 1-7, 12-14, 128-133, 193, 254. 10 April 2018. (hereinafter “Guide”) in view of US 20210182077 A1 Chen et al. (hereinafter “Chen”).
Regarding claim 1, Croxford discloses a convolutional neural network acceleration method ([0023]) based on a Cortex-M processor, wherein the method comprises:
setting a Master Control Reset (MCR) instruction and a Collection Due Process (CDP) instruction according to common basic operators ([0007]) of a convolutional neural network (Fig. 7 “700” [0048]), wherein the common basic operators comprise a convolution operator ([0030]), a rectified linear unit (Relu) activation operator ([0056]), a pooling operator ([0057]), a table look-up operator and a quantization operator; and
configuring an internal register (Fig. 1 “230” [0032]) of a convolutional neural network coprocessor (Fig. 1 “220” [0032]) through the MCR instruction, and then enabling the common basic operators ([0007]) of the convolutional neural network ([0048]) through the CDP instruction.
Croxford appears to be silent to disclosing: based on a Cortex-M processor, setting a Master Control Reset (MCR) instruction and a Collection Due Process (CDP) instruction, and a table look-up operator and a quantization operator.
Guide discloses based on a Cortex-M processor (p. 7 “About this book”), wherein the method comprises:
setting a Master Control Reset (MCR) instruction (p. 3-128 Table 3-7: MCR, MCR2 MCRR, MCRR2) and a Collection Due Process (CDP) instruction (p. 3-128 Table 3-7: CDP, CDP2).
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Croxford’s method to further comprise basing on a Cortex-M processor and the MCR and CDP instructions as disclosed by Guide’s features because they are in the claimed invention’s same field of endeavor of data processing architecture (p. 7 “About this book”). Modifying with Guide’s basing on a Cortex-M processor and MCR and CDP instructions would have been obvious to one of ordinary skill in the art as doing so would yield significant improvements for developers by providing efficient processor core, system, and memories that deliver exceptional power efficiency through an efficient instruction set and extensively optimized design (p. 1-12). Using Guide’s basing on a Cortex-M processor and MCR and CDP instructions features to provide a predictable result in Croxford’s method before the effective filing date would have been obvious since one of ordinary skill in the art would recognize that Croxford’s method was ready for improvement to incorporate these high-performance processor cores and optimized instruction sets for processing convolutional neural network data, as doing so would be beneficial by delivering exceptional power efficiency.
Guide and the combination of Croxford in view of Guide are silent with further disclosing a table look-up operator and a quantization operator.
Chen discloses a table look-up operator ([3255]) and a quantization operator ([3200], [3209]).
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Croxford in view of Guide’s method to further comprise table look-up and quantization operators as disclosed by Chen’s features because they are in the claimed invention’s same field of endeavor of data processing architecture ([Abstract]). Modifying with Chen’s table look-up and quantization operators would have been obvious to one of ordinary skill in the art as doing so would yield significant improvements for developers by providing improved processing speed with reduced weight storage and memory access overhead via the quantization operations ([3332]) of which is accessed by the lookup table operations ([3255], [3262-3263]). Using Chen’s table look-up and quantization operators features to provide a predictable result in Croxford in view of Guide’s method before the effective filing date would have been obvious since one of ordinary skill in the art would recognize that Croxford in view of Guide’s method was ready for improvement to incorporate these quantization and table look-up operations for processing convolutional neural network data as doing so would be beneficial by delivering reduced weight storage and memory access overhead and improved processing speeds.
Regarding claim 2, the teachings addressed in the claim 1 analysis and rejection are incorporated, and Croxford in view of Guide in view of Chen disclose the method wherein Croxford discloses:
the step of configuring the internal register of the convolutional neural network coprocessor through the MCR instruction (see claim 1 mapping) comprises:
configuring a data address ([0038] address), stride block information ([0080] horizontal and vertical) and format information ([0085] format) of the internal register (Fig. 1 “230” [0032]) of the convolutional neural network coprocessor (Fig. 1 “220” [0032]) through the MCR instruction, wherein the data address is used for reading and writing data in operation ([0032]), the stride block information is used for partitioning data in operation ([0072]), and the format information is used for confirming an operation format ([0004]) and a write-back format of data.
Croxford appears to be silent to disclosing through the MCR instruction and a write-back format of data.
Guide discloses a MCR instruction (p. 3-128 Table 3-7: MCR, MCR2 MCRR, MCRR2) and a write-back format of data (p. 3-254 write-back suffix).
The motivation to combine provided with respect to claim 1 similarly applies.
Regarding claim 3, the teachings addressed in the claim 1 analysis and rejection are incorporated, and Croxford in view of Guide in view of Chen disclose the method wherein Croxford discloses:
wherein the step of configuring the internal register through the MCR instruction, and then enabling the common basic operators through the CDP instruction (see claim 1 mapping), comprises:
configuring a local buffer address ([0038]) of a convolution kernel ([0052]) to a first register (Fig. 2 “210a” [0035]), configuring a local buffer address ([0038]) of feature data ([0052]) to a second register (Fig. 2 “210b” [0035]), configuring stride block information ([0052]) to a scale register ([0070] via the feature map manipulation, [0072] separate register), and configuring format information ([0085] format) to a control register ([0036] control data stored in internal storage) through a first MCR instruction;
enabling the convolution operator ([0030]) through the CDP instruction, and determining a preset channel number ([0029], [0050] three: red, green, blue) and a preset number of sets of the feature data in each operation ([0050] 224 pixels wide and 224 pixels high) according to the stride block information ([0052]);
sequentially performing Multiply Accumulate operations on the feature data and the convolution kernel ([0052] multiplication and addition (accumulation)) in a channel direction ([0052] sliding determined by stride information) according to a total channel number and the preset channel number of the feature data ([0050] colors and red/green/blue); and
sequentially performing the Multiply Accumulate operations on the feature data and the convolution kernel in each of channels of the feature data in a preset direction ([0052] multiplication and addition (accumulation)) according to a total number of the sets and the preset number of the sets of the feature data ([0050] colors and red/green/blue), and the format information ([0085] format) until convolution results of all the channels are obtained ([0073]).
Croxford appears to be silent to disclosing through a first MCR instruction.
Guide discloses through a first MCR instruction (p. 3-128 Table 3-7: MCR, MCR2 MCRR, MCRR2).
The motivation to combine provided with respect to claim 1 similarly applies.
Regarding claim 4, the teachings addressed in the claim 1 analysis and rejection are incorporated, and Croxford in view of Guide in view of Chen disclose the method wherein Croxford discloses:
the step of configuring the internal register through the MCR instruction, and then enabling the common basic operators through the CDP instruction (see claim 1 mapping), further comprises:
configuring a local buffer address ([0038]) of input data ([0033], [0052]) to a first register (Fig. 2 “210a” [0035]), configuring a local buffer address ([0038]) of write-back information to a second register (Fig. 2 “210b” [0035]), and configuring stride block information ([0052]) to a scale register ([0070] via the feature map manipulation, [0072] separate register) through a second MCR instruction;
enabling the Relu activation operator ([0056]) of the convolutional neural network ([0048]) through the CDP instruction, inputting the input data to a Relu activation function
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x
<
0
x
,
x
≥
0
([0056]) according to the stride block information ([0052]), and returning a result value ([0056] predefined output), wherein e is a natural constant in mathematics and x is the input data ([0056] input); and
writing the result value back ([0056] output of a convolutional layer) to a local buffer according to the write-back information.
Croxford appears to be silent to disclosing write-back information, through a second MCR instruction, through the CDP instruction, wherein e is a natural constant in mathematics, and a local buffer.
Guide discloses write-back information (p. 3-254 write-back suffix), through a second MCR instruction (p. 3-128 Table 3-7: MCR, MCR2 MCRR, MCRR2), through the CDP instruction (p. 3-128 Table 3-7: CDP, CDP2), and a local buffer (Fig. 1-2 “MTB”).
The motivation to combine provided with respect to claim 1 similarly applies.
Guide and the combination of Croxford in view of Guide appear to be silent to disclosing wherein e is a natural constant in mathematics.
Chen discloses wherein e is a natural constant in mathematics ([0118], [0205], [3921]).
The motivation to combine provided with respect to claim 1 similarly applies.
Regarding claim 5, the teachings addressed in the claim 1 analysis and rejection are incorporated, and Croxford in view of Guide in view of Chen disclose the method wherein Croxford discloses:
the step of configuring the internal register through the MCR instruction, and then enabling the common basic operators through the CDP instruction (see claim 1 mapping), further comprises:
configuring a local buffer address ([0038]) of a first vector set (Fig. 2 “x” [0035]) to a first register (Fig. 2 “210a” [0035]), configuring a local buffer address ([0038]) of a second vector set (Fig. 2 “y” [0035]) to a second register (Fig. 2 “210b” [0035]), configuring a local buffer address ([0038]) of write-back information to a third register (Fig. 2 “210c” [0035]), and configuring stride block information ([0080] horizontal and vertical) to a scale register ([0070] via the feature map manipulation, [0072] separate register) through a third MCR instruction;
enabling the pooling operator ([0057]) of the convolutional neural network ([0048]) through the CDP instruction, comparing values in the first vector set and the second vector set one by one according to the stride block information ([0061]), and returning a vector with a larger value from each comparison ([0061] output of max pool; [0067-0068] “
C
f
(
2
)
”); and
writing a maximum pooling result obtained by the comparison back to a local buffer ([0068]) according to the write-back information.
Croxford appears to be silent to disclosing write-back information, through the CDP instruction, and through a third MCR instruction.
Guide discloses write-back information (p. 3-254 write-back suffix), through the CDP instruction (p. 3-128 Table 3-7: CDP, CDP2), and through a third MCR instruction (p. 3-128 Table 3-7: MCR, MCR2 MCRR, MCRR2).
The motivation to combine provided with respect to claim 1 similarly applies.
Regarding claim 6, the teachings addressed in the claim 1 analysis and rejection are incorporated, and Croxford in view of Guide in view of Chen disclose the method wherein Croxford discloses:
the step of configuring the internal register through the MCR instruction, and then enabling the common basic operators through the CDP instruction (see claim 1 mapping), further comprises:
configuring a local buffer address ([0038]) of input data ([0033], [0052]) to a first register (Fig. 2 “210a” [0035]), configuring a local buffer address ([0038]) of write-back information to a second register (Fig. 2 “210b” [0035]), and configuring stride block information ([0052]) and table base address information to a scale register ([0070] via the feature map manipulation, [0072] separate register) through a fourth MCR instruction;
enabling the table look-up operator of the convolutional neural network ([0048]) through the CDP instruction, and performing a table look-up operation according to the input data ([0033], [0052]), the stride block information ([0052]), and the table base address information; and
writing a table look-up result back to a local buffer according to the write-back information.
Croxford appears to be silent with disclosing write-back information, table base address information, through a fourth MCR instruction, enabling the table look-up operator through the CDP instruction, and performing a table look-up operation, and the table base address information; and writing a table look-up result back to a local buffer according to the write-back information.
Guide discloses disclosing write-back information (p. 3-254 write-back suffix), through a fourth MCR instruction (p. 3-128 Table 3-7: MCR, MCR2 MCRR, MCRR2), through the CDP instruction (p. 3-128 Table 3-7: CDP, CDP2).
The motivation to combine provided with respect to claim 1 similarly applies.
Guide and the combination of Croxford in view of Guide appear to be silent with disclosing table base address information, enabling the table look-up operator, and performing a table look-up operation, and the table base address information; and writing a table look-up result back to a local buffer.
Chen discloses table base address information ([3276] lookup table control information), enabling the table look-up operator ([3255]), and performing a table look-up operation ([3276]); and writing a table look-up result back to a local buffer ([3400] output neurons to the storage unit 4).
The motivation to combine provided with respect to claim 1 similarly applies.
Regarding claim 7, the teachings addressed in the claim 1 analysis and rejection are incorporated, and Croxford in view of Guide in view of Chen disclose the method wherein Croxford discloses:
wherein the step of configuring the internal register through the MCR instruction, and then enabling the common basic operators through the CDP instruction (see claim 1 mapping), further comprises:
configuring a local buffer address ([0038]) of input data ([0033], [0052]) to a first register (Fig. 2 “210a” [0035]), configuring a local buffer address ([0038]) of write-back information to a second register (Fig. 2 “210b” [0035]), and configuring stride block information ([0052]) to a scale register ([0070] via the feature map manipulation, [0072] separate register) through a second MCR instruction; and
enabling the quantization operator of the convolutional neural network ([0048]) through the CDP instruction, and converting a 32-bit single-precision floating-point number conforming to an IEEE-754 standard in the input data ([0033], [0052]) into a 16-bit integer according to the stride block information ([0052]), or converting a 16-bit integer in the input data ([0033], [0052]) into a 32-bit single-precision floating-point number conforming to the IEEE-754 standard; and writing a conversion result back to a local buffer according to the write-back information.
Croxford appear to be silent to disclosing write-back information, through a second MCR instruction, enabling the quantization operator, through the CDP instruction, and converting a 32-bit single-precision floating-point number conforming to an IEEE-754 standard or converting a 16-bit integer into a 32-bit single-precision floating-point number conforming to the IEEE-754 standard; and writing a conversion result back to a local buffer according to the write-back information.
Guide discloses write-back information (p. 3-254 write-back suffix), through a second MCR instruction (p. 3-128 Table 3-7: MCR, MCR2 MCRR, MCRR2), through the CDP instruction (p. 3-128 Table 3-7: CDP, CDP2), and converting a 32-bit single-precision floating-point number conforming to an IEEE-754 standard or converting a 16-bit integer into a 32-bit single-precision floating-point number conforming to the IEEE-754 standard (p. 3-193); and writing a conversion result back to a local buffer according to the write-back information (p. 3-193 Sd).
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Croxford’s method to further comprise conversion instructions as disclosed by Guide’s features because they are in the claimed invention’s same field of endeavor of data processing architecture (p. 7 “About this book”). Modifying with Guide’s conversion instructions would have been obvious to one of ordinary skill in the art as doing so would yield significant improvements for developers by providing efficient processor core, system, and memories that deliver exceptional power efficiency through an efficient instruction set and extensively optimized design including IEEE754-compliant single-precision floating-point computations (p. 1-12). Using Guide’s conversion instructions features to provide a predictable result in Croxford’s method before the effective filing date would have been obvious since one of ordinary skill in the art would recognize that Croxford’s method was ready for improvement to incorporate these optimized and IEEE754-compliant instructions for processing convolutional neural network data as doing so would be beneficial by delivering exceptional power efficiency.
Guide and the combination of Croxford in view of Guide appear to be silent to disclosing enabling the quantization operator.
Chen discloses enabling the quantization operator ([3200], [3209]).
The motivation to combine provided with respect to claim 1 similarly applies.
Regarding claim 8, the teachings addressed in the claim 1 analysis and rejection are incorporated, and Croxford in view of Guide in view of Chen disclose the method wherein Croxford discloses:
configuring a main memory address ([0043]) to a first register (Fig. 2 “210a” [0035]), configuring a local buffer address ([0038]) to a second register (Fig. 2 “210b” [0035]), and configuring stride block information ([0080] horizontal and vertical) to a scale register ([0070] via the feature map manipulation, [0072] separate register) through a fifth MCR instruction;
enabling a data reading operation ([0033] reads) through the CDP instruction, and reading data in the main memory address to a local buffer ([0035], [0061] reading; Fig. 2 “210c” [0035]) according to the stride block information ([0080] horizontal and vertical); and
enabling a data writing operation ([0033] writes) through the CDP instruction, and writing the data in the local buffer to the main memory address ([0035], [0061] writing) according to the stride block information ([0080] horizontal and vertical).
Croxford appears to be silent to disclosing through a fifth MCR instruction, through the CDP instruction.
Guide discloses a fifth MCR instruction (p. 3-128 Table 3-7: MCR, MCR2 MCRR, MCRR2), through the CDP instruction (p. 3-128 Table 3-7: CDP, CDP2).
The motivation to combine provided with respect to claim 1 similarly applies.
Regarding claim 10, the teachings addressed in the claim 1 analysis and rejection are incorporated, and Croxford in view of Guide in view of Chen disclose, wherein Croxford discloses a computer-readable storage medium storing a computer program thereon ([0022-0023] computer-implemented methods), characterized in that, wherein the computer program is executed by a processor (Fig. 1 “100” [0026]), implements the convolutional neural network acceleration method ([0023]) based on the Cortex-M processor according to claim 1 (see claim 1 mapping).
Croxford appears to be silent to disclosing based on the Cortex-M processor.
Guide discloses based on a Cortex-M processor (p. 7 “About this book”).
The motivation to combine provided with respect to claim 1 similarly applies.
Claim 9 is directed to a system that would practice the method of claim 1. The analysis of claim 1 similarly applies to claim 9. In addition, claim 9 recites: an instruction set setting module and instruction set execution module.
Croxford discloses an instruction set setting module (Fig. 1 “130” [0024]) and instruction set execution module (Fig. 1 “120” [0023-0024]).
Conclusion
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/MARKUS ANTHONY VILLANUEVA/Examiner, Art Unit 2151
/James Trujillo/Supervisory Patent Examiner, Art Unit 2151
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