DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 02/27/2026 have been fully considered but they are not persuasive. Applicant argues that the Kamikawa et al. (US 2022/0123166 A1) does not teach the limitations “removing the second semiconductor portion” and “removing the mask”. Examiner respectfully disagrees as shown in the rejection of those limitations below.
Applicant further argues that Kamikawa et al. (US 2022/0123166 A1) does not teach the limitation “separating the first semiconductor portion and the template substrate after removing the semiconductor portion and the removing the mask, wherein a part of the of the first semiconductor portion remained on the template substrate after the separating”. Examiner respectfully disagrees and draws the Applicants attention to Para [0121 and 0122] and Figs 6(c), 7(b) and 7(c) of Kamikawa et al. (US 2022/0123166 A1). As shown below, (Para [0122] and Fig 6(c) disclose cleaving point 112 as a layer left on substrate 101 after the cleave process and Para [0121] and Fig 7(b) and 7(c) further teaches that a cleaved portion (112) is formed within the epitaxially grown layer (105), or rather, being provided at a level higher that the bottom of said layer (105) cleave. Para [0121] specifically states, “With the trench 109, the shape of the III-nitride ELO layers 105 is shown in FIGS. 7(b) and 7(c), wherein the cleaving point 112 is above the bottom of the III-nitride ELO layers 105”, therefore a portion of 105 remains on the substrate 101).
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-5, 7-11 and 18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kamikawa et al. (US 2022/0123166 A1, hereinafter Kamikawa ‘166).
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With respect to Claim 1 Kamikawa ‘166 discloses a method for producing a semiconductor device (Fig 4(a) – 5(b)), the method comprising:
preparing a semiconductor substrate (101/102, Fig 4(a), Para [0087]) comprising an underlying substrate (101, Fig 4(a), Para [0087]), a mask (102/103, Fig 4(a), Para [0087]) comprising an opening portion (103, Fig 4(a), Para [0087]) and a mask portion (102, Fig 4(a), Para [0087]) that includes a first region (side of 102 as shown in annotated Fig 4(a) of Kamikawa ‘166) and a second region (horizontal area of 102 as shown in annotated Fig 4(a) of Kamikawa ‘166), and a first semiconductor portion (105, Fig 4(b), Para 0095]) formed from above the opening portion (103) over the first region (side of 102)(growth process disclosed in Para [0092]); and
a second semiconductor portion (401, Fig 4(c), Para [0097]) containing a gallium congener (Para [0097] discloses 401 debris formed “during growth of thick In-containing AlGaN and InGaN layers within the III-nitride semiconductor device layers 106” and Para [0186] discloses a Ga congener (In, Al and/or boron) in 106 from which 401 is formed) and located above the second region (horizontal area of 102) where the first semiconductor portion (105) is not formed (Fig 4(c) discloses 401 formed in area of second region and 105 is not in that region).
forming a third semiconductor portion (106, Fig 4(e), Para [0097]) located above the first semiconductor portion (105) and containing the gallium congener and gallium (Para [0097] discloses 106 formed by growth of thick In-containing AlGaN and InGaN layers and Para [0186] discloses 106 containing gallium congener (In, Al and/or boron))
removing the second semiconductor portion (401)(Para [0097] discloses 401 is removed);
removing the mask (102)(Para [0056] discloses mask 102 is removed); and
separating (disclosed in Fig 6(c) and Para [0120]) the first semiconductor portion (105) and the underlying substrate (101) after the removing the second semiconductor portion (401) and the removing the mask (102)(Fig 6(a) discloses element 114 (which comprises first semiconductor portion 105) still attached to substrate 101 and the mask 102 and second semiconductor portion 401 have been removed),
wherein the separation is performed by breaking the first semiconductor portion (105) (Para [0120] and Fig 6(c) disclosed element 114 (which comprises first semiconductor portion 105) is separated from 101 by cleaving the device from the substrate) and a part of the first semiconductor portion (105) remained on the underlying substrate (101) after the separating (Para [0122] and Fig 6(c) disclose cleaving point 112 as a layer left on substrate 101 after the cleave process and Para [0121] and Fig 7(b) and 7(c) further teaches that a cleaved portion (112) is formed within the epitaxially grown layer (105), or rather, being provided at a level higher that the bottom of said layer (105) cleave. Para [0121] specifically states, “With the trench 109, the shape of the III-nitride ELO layers 105 is shown in FIGS. 7(b) and 7(c), wherein the cleaving point 112 is above the bottom of the III-nitride ELO layers 105”, therefore a portion of 105 remains on the substrate 101).
With respect to Claim 2 Kamikawa ‘166 discloses all limitations of the method for producing a semiconductor device according to claim 1, and Kamikawa ‘166 discloses further wherein the gallium congener is aluminum (Para [0097] discloses 401 debris formed from AlGaN growth and Para [0186] discloses a Ga congener of Al in 106 from which 401 is formed).
With respect to Claim 4 Kamikawa ‘166 discloses all limitations of the method for producing a semiconductor device according to claim 1, and Kamikawa ‘166 further discloses wherein the second semiconductor portion (401) located above the second region (horizontal area of 102 as shown in annotated Fig 4(a) of Kamikawa ‘166) and the third semiconductor portion (106) each contain a nitride semiconductor (Para [0097] discloses 106 and 401 as a III-nitride semiconductor device layer formed by growth of thick In-containing AlGaN and InGaN layers).
With respect to Claim 5 Kamikawa ‘166 discloses all limitations of the method for producing a semiconductor device according to claim 4, and Kamikawa ‘166 discloses further wherein the nitride semiconductor (106 and 401) is aluminum gallium nitride (Para [0097] discloses 106 and 401 a III-nitride semiconductor device layer formed by growth of growth of thick In-containing AlGaN layers).
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With respect to Claim 7 Kamikawa ‘166 discloses all limitations of the method for producing a semiconductor device according to claim 1, and Kamikawa ‘166 further discloses wherein in the forming of the third semiconductor portion (106), a fourth semiconductor portion (sidewalls of 106 as shown in annotated Fig 4(e) of Kamikawa ‘166, ) along side surfaces (Fig 4(e) discloses 106 extending over the side surfaces of first semiconductor portion 105) of the first semiconductor portion (105) is formed.
With respect to Claim 8 Kamikawa ‘166 discloses all limitations of the method for producing a semiconductor device according to claim 1, and Kamikawa ‘166 further discloses wherein the third semiconductor portion (106) is in contact with an upper surface (top of 105 as shown in annotated Fig 4(e) of Kamikawa ‘166) of the first semiconductor portion (105).
With respect to Claim 9 Kamikawa ‘166 discloses all limitations of the method for producing a semiconductor device according to claim 1, and Kamikawa ‘166 further discloses wherein the mask portion (102) comprises at least one of a silicon oxide and a silicon nitride (Para [0177] discloses mask 102 as a multiple-stacking layer structure comprising SiO2 and SiN).
With respect to Claim 10 Kamikawa ‘166 discloses all limitations of the method for producing a semiconductor device according to claim 9, and Kamikawa ‘166 further discloses wherein the second semiconductor portion (401) located above the second region (horizontal area of 102 as shown in annotated Fig 4(a) of Kamikawa ‘166) is in contact with the mask portion (102)(Fig 4(e) discloses 401 in contact with mask 102).
With respect to Claim 11 Kamikawa ‘166 discloses all limitations of the method for producing a semiconductor device according to claim 9, and Kamikawa ‘166 further discloses wherein the first semiconductor portion (105) contains silicon and a GaN-based semiconductor (Para [0186] discloses 105 contains silicon along with III-nitride layers and Para [0093] discloses III nitride layers 105 contains GaN).
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With respect to Claim 18 Kamikawa ‘166 discloses all limitations of the method for producing a semiconductor device according to claim 1, and Kamikawa ‘166 further discloses wherein after the second semiconductor portion (401) located above the second region (horizontal area of 102 as shown in annotated Fig 4(a) of Kamikawa ‘166) is formed, a fifth semiconductor portion (p-electrodes 504 disclosed in Para [0106] and Fig 5(b)) located above the third semiconductor portion (106)(Fig 5(b) discloses p-electrodes over 106) is formed (disclosed in Para [0114]), and
the removing the second semiconductor is performed after the fifth semiconductor portion (504) is formed, (annotated Fig 4(d) discloses p-electrode (not labeled as 504 in Fig 4(d)) is present on structure 114 and the semiconductor portion 401 and mask 102 are still present, therefore the p-electrode is formed before removal of 401).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3, 6 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Kamikawa ‘166 in view of the following arguments.
With respect to Claim 3 Kamikawa ‘166 discloses all limitations of the method for producing a semiconductor device according to claim 1, but Kamikawa ‘166 does not explicitly disclose wherein:
the removing the mask is performed after the removing the second semiconductor portion.
However Kamikawa ‘166 discloses further discloses wherein: the removing the mask (102) and the removing of the second semiconductor portion (401) is conducted by a wet etch process (Para [0056] and [0097] respectively, and Para [0097] discloses both 401 and 102 are present and discloses a wet etch process to remove 401).
Therefore, it would have been obvious to a person having ordinary skill in the art, before the effective filing date, absent unexpected results, that the removal of the mask (102) is performed after the removing the second semiconductor portion (401) as in the wet etch process the second semiconductor portion (401) would be exposed to and removed by the etchant before the mask layer (102) would be fully exposed and fully removed by the etchant as 401 is on top of 102.
With respect to Claim 6 Kamikawa ‘166 discloses all limitations of the method for producing a semiconductor device according to claim 5, and Kamikawa ‘166 discloses further wherein the aluminum gallium nitride (Para [0097] discloses 106 and 401 a III-nitride semiconductor device layer formed by growth of growth of thick In-containing AlGaN layers) contained in the second semiconductor portion (401) located above the second region (horizontal area of 102 as shown in annotated Fig 4(a) of Kamikawa ‘166) has a different composition from that of the aluminum gallium nitride (Para [0097] discloses 106 and 401 a III-nitride semiconductor device layer formed by growth of growth of thick In-containing AlGaN layers) contained in the third semiconductor portion (106).
But Kamikawa ‘166 fails to explicitly disclose the aluminum gallium nitride contained in the semiconductor portion located above the second region has a different composition from that of the aluminum gallium nitride contained in the second semiconductor portion.
However, Kamikawa ‘166 discloses in Para [0177] a mask 102 as a multiple-stacking layer structure comprising SiO2 which is the same structure as the mask 102 disclosed in the specification Para [0022] of the instant application. Further, the deposition method of the aluminum gallium nitride for the second semiconductor portion (106) and the semiconductor portion (401) located above the second region is a CVD process like the vapor phase growth process in the instant application Para [0007]. Therefore, the aluminum gallium nitride in the semiconductor portion located above the second region and the aluminum gallium nitride contained in the second semiconductor portion of Kamikawa ‘166 must behave the same as the aluminum gallium nitride in the semiconductor portion located above the second region and the aluminum gallium nitride contained in the second semiconductor portion of the instant application, and so the aluminum gallium nitride contained in the semiconductor portion located above the second region also has a different composition from that of the aluminum gallium nitride contained in the second semiconductor portion.
With respect to Claim 16 Kamikawa ‘166 discloses all limitations of the method for producing a semiconductor device according to claim 1, wherein a thickness of the second semiconductor portion (401) located above the second region (horizontal area of 102 as shown in annotated Fig 4(a) of Kamikawa ‘166) is smaller than a thickness of the third semiconductor portion (106).
But Kamikawa ‘166 fails to explicitly disclose a thickness of the semiconductor portion located above the second region is smaller than a thickness of the second semiconductor portion. However, Kamikawa ‘166 discloses in Para [0097] a semiconductor portion (401) located above the second region of AlGaN and InGaN layers and gallium which are the same materials of the semiconductor portion located above the second region as the instant application disclosed in Para [0024] and [0043] and in Para [0097] discloses Kamikawa ‘166 discloses a second semiconductor portion (106) formed by growth of thick In-containing AlGaN and InGaN layers which are the materials of the second semiconductor portion of the instant application as disclosed in Para [0024] and [0043]. Further the deposition method of the semiconductor materials (106) and (401) of Kamikawa ‘166 is a CVD process like the vapor phase growth process for the deposition of the semiconductor materials in the instant application Para [0007]. Therefore, as the semiconductor portion located above the second region of Kamikawa ‘166 and the second semiconductor portion are equivalent in material and deposition to the instant application, a thickness of the semiconductor portion located above the second region is smaller than a thickness of the second semiconductor portion.
Claim 23 is rejected under 35 U.S.C. 103 as being unpatentable by Kamikawa ‘166 with support of Liu, An-Chen & Tu, Po-Tsung & Langpoklakpam, Catherine & Huang, Yu-Wen & Chang, Ya-Ting & Tzou, An-Jye & Hsu, Lung-Hsing & Lin, Chun-Hsiung & Kuo, Hao-Chung & Chang, Edward. (2021). The Evolution of Manufacturing Technology for GaN Electronic Devices. Micromachines, hereinafter Liu et al.), in view of the following arguments.
With respect to Claim 23 Kamikawa ‘166 discloses all limitations of the method for producing a semiconductor device according to claim 11, and in a further embodiment (Fig 1(b)) Kamikawa ‘166 further discloses wherein the underlying substrate (101) comprises a main substrate (hetero-substrate 101, Fig 1(b), Para [0044]), and the main substrate (101) is a heterogeneous substrate (Para [0044] discloses 101 as a hetero-substrate of sapphire) having a different lattice constant from that of the GaN- based semiconductor (105) (Para [0186] discloses 105 contains silicon along with III-nitride layers and Para [0093] discloses III nitride layers 105 contains GaN) (one of ordinary skill in the art will recognize that sapphire has a different lattice constant from that of GaN. This is also supported by Liu et al. (Liu et al. discloses in Table 1, Page 6 that GaN has a different lattice constant than sapphire)).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Kamikawa ‘166’s further teaching wherein the underlying substrate comprises a main substrate, and the main substrate is a heterogeneous substrate having a different lattice constant from that of the GaN- based semiconductor into Kamikawa ‘166’s method. The ordinary artisan would have been motivated to modify Kamikawa ‘166 in the manner set forth above, at least, because, as Kamikawa ‘166 teaches in Para [0184], the use of a heterogeneous substrate of GaN and sapphire allows a separation using a c-plane cleaving plane to separate structures which provides a preferred separation method over separation of devices on a single layer substrate.
As incorporated, the teaching of Kamikawa ‘166 wherein the underlying substrate comprises a main substrate, and the main substrate is a heterogeneous substrate having a different lattice constant from that of the GaN- based semiconductor would be used in the substrate (101) of Kamikawa ‘166.
Claims 24-25 are rejected under 35 U.S.C. 103 as being unpatentable over Kamikawa ‘166 with support of Liu et al., in view of Okagawa et al. (JP 2007-314360, hereinafter Okagawa ‘360), in view of the following arguments.
With respect to Claim 24 Kamikawa ‘166, as supported by Liu et al. discloses all limitations of the method for producing a semiconductor device according to claim 23,
But Kamikawa ‘166, as supported by Liu et al. fails to explicitly disclose wherein the underlying substrate comprises a seed portion located above the main substrate, and the seed portion is exposed from the opening portion.
Nevertheless, in a related endeavor (Fig 6(a)–6(d) of Okagawa ‘360), Okagawa ‘360 teaches disclose wherein the underlying substrate (10/20/30, Fig 6(d) of Okagawa ‘360, Para [0005]) comprises a seed portion (dashed portion of 30, as disclosed in Fig 6(c) and Para [0005] of Okagawa ‘360) located above the main substrate (10), and the seed portion (dashed portion of 30) is exposed from the opening portion (Para [0005] of Okagawa ‘360 discloses, “Although illustration is omitted, the growth of the Si-added GaN crystal also occurs in the groove of the sapphire processed substrate”).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Okagawa ‘360’s teaching of wherein the underlying substrate comprises a seed portion located above the main substrate, and the seed portion is exposed from the opening portion into Kamikawa ‘166, as supported by Liu et al.’s device. Kamikawa ‘166, as supported by Liu et al. teaches a substrate with a main portion and a heterogeneous sapphire substrate. Okagawa ‘360 also teaches a sapphire substrate with a main GaN portion and further teaches how to use that substrate structure to begin crystal growth. The ordinary artisan would have been motivated to modify Kamikawa ‘166, as supported by Liu et al. in the manner set forth above, at least, because, as Okagawa ‘360 teaches in Para [0007] this configuration enables the substrate to be easily separated from the crystal and Para [0009] teaches the crystal provides improved quality of the device.
As incorporated, the teaching of wherein the underlying substrate comprises a seed portion located above the main substrate, and the seed portion is exposed from the opening portion taught by Okagawa ‘360 would be used in the underlying substrate (101) in the method of Kamikawa ‘166, as supported by Liu et al.
With respect to Claim 25 Kamikawa ‘166, as supported by Liu et al. and modified by Okagawa ‘360 discloses all limitations of the method for producing a semiconductor device according to claim 24, and Okagawa ‘360 further teaches wherein the opening portion (concave portion of 10 as shown in Fig 6(c) of Okagawa ‘360) has a slit shape (Fig 6(c) of Okagawa ‘360 discloses a slit shape), and the seed portion (dashed portion of 30, as disclosed in Fig 6(c)) has a longitudinal shape (Fig 6(c) of Okagawa ‘360 discloses seed area 30 having a longitudinal shape (grows horizontally) as it overlaps the concave portion of 10) overlapping with the opening portion (concave portion of 10 as shown in Fig 6(c) of Okagawa ‘360).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PAUL A. BERRY whose telephone number is (703)756-5637. The examiner can normally be reached M-F 8-5 EST.
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/PAUL A BERRY/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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