The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
The substitute specification, filed 6 January 2026 has been reviewed, found acceptable and has replaced the previous substitute specification.
The disclosure is objected to because of the following informalities found in the substitute specification: Page 9, line 30, it is noted that the term “run” should be rewritten as --are-- for an appropriate characterization. Appropriate correction is required.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1, 5-7, 9, 11, 12; 14, 18-20; 21, 26-28, 30, 32, 33 are rejected under 35 U.S.C. 103 as being unpatentable over Flatters et al in view of Shono (both references of record).
Flatters et al (i.e. Figures 1(a), 1(b), 2(a), 3) discloses a waveguide interface arrangement, comprising: a printed circuit board having a dielectric layer (i.e. insulating layer 3) having a first (i.e. lower) main side with a first metallization (i.e. conductive layer 11) disposed thereon and an opposite second (i.e. upper) main side with a second metallization (i.e. conductive layer 8) disposed thereon including a probe launch (i.e. 14); a first aperture (i.e. unlabeled) is formed in the first metallization (11), as evident from Figure 1(a) and a second aperture (i.e. aperture 9) is formed as a part of the second metallization, as evident from Figure 1(b); a backshort, as shown in Figure 2(a), includes a backshort dielectric layer (i.e. insulating layer 17) having a first main side with a first backshort metallization (i.e. conductive layer 24) and an opposite second main side with a second backshort metallization (i.e. conductive layer 26) and including a backshort aperture (i.e. backshort recess 20) that forms an air cavity with metalized walls {i.e. recess walls (21, 25)} extending between the first and second metallizations (as per claims 5, 6, 18, 19, 26, 27), as evident from Figure 2(a), that faces the second aperture (9) formed as a part of the second metallization (8). As described in paragraph [0057], in an alternative arrangement, the backshort may have a dielectric layer that includes via holes therein connecting the first and second backshort metallizations, as per claims 7, 20, 28. As evident from Figure 3, the aperture (20) in the backshort, the aperture (9) on the second main side and the aperture (unlabeled) on the first main side are all align with an opening of a waveguide (not labeled) that is attachable to the waveguide interface arrangement. Moreover, as evident from Fig. 3, note that an electronic component (i.e. electrical signal source 33) typically connects with the probe launch (14). Regarding claims 9, 30, note that the probe launch (14) of the second metallization enters into the backshort (22) through an opening (i.e. an open side) therein. Regarding claims 11, 32, as evident from Figure 1(b), via holes electrically connect the first and second metallization associated with the printed circuit board (3). Regarding claims 12, 33, as evident from Figure 1(a), a metallization is provided on waveguide sidewall (i.e. 7) to electrically connect the first and second metallizations associated with the printed circuit board (3). Regarding claim 14, note that this claim is met by the backshort, as described above. Regarding claim 21, note the method recited in this claim is met by the waveguide interface arrangement as described above, especially since the described configuration satisfies the various process steps recited (i.e. providing, mounting, attaching, etc.). However, Flatters et al does not explicitly disclose that the dielectric layer of the backshort and the dielectric layer of the PCB are made of the same dielectric material.
Shono (i.e. Fig. 3) discloses a waveguide/planar converter having a PCB layer (i.e. dielectric substrate 11a) and a backshort layer (i.e. short-circuiting lid (22) with a main body (22a) that is insulating or dielectric). As described at column 8, lines 1-4, the dielectric/insulating main body lid (22a) can comprise of various specified dielectric materials, which are the same dielectric materials that form the dielectric substrate layer (11a), which are also described at column 6, lines 45-48.
Accordingly, it would have been obvious in view of the references, taken as a whole, to have configured the dielectric layer of the PCB and the dielectric layer of the backshort in Flatters et al to have been the same dielectric material, such as taught by Shono. Such a modification would have been considered an obvious substitution of art recognized equivalents, especially since the generic nature of the dielectric layers for the PCB and backshort in Flatters et al would have suggested any equivalent selection dielectric materials would have been usable, such as the same dielectric material as taught by Shono, thereby suggesting the obviousness of such a modification.
Claims 8; 29 are rejected under 35 U.S.C. 103 as being unpatentable over the preceding rejection as applied to claims 1, 21, respectively above, and further in view of Lo Hine Tong et al (of record).
Note that the above resultant combination discloses the claimed invention except for the microwave conductor being disposed on the first metallization of the printed circuit board.
Lo Hine Tong et al (i.e. FIG. 1) discloses a transition between a waveguide and a microstrip line having a configuration corresponding to the waveguide interface arrangement as described in Flatters et al, but includes the microwave conductor (i.e. microstrip line 31) disposed on a printed circuit board main side corresponding to the first main side of the printed circuit board in Flatters et al.
Accordingly, it would have been obvious in view of the references to have modified the microwave conductor in the resultant combination to have been on a first main side of the printed circuit board, such as taught by Lo Hine Tong et al. Such a modification would have been considered an obvious substitution of equivalent configurations, especially since whether the microwave conductor is on a first main side or on a second main side would not have affected the operation of the interface or transition (i.e. appropriate coupling would have occur irrespective of whether the microwave conductor is on the first main side or the second main side of the printed circuit board), thereby suggesting the obviousness of such a modification.
Applicant's arguments filed 6 January 2026 have been fully considered but they are not persuasive.
Regarding the rejections based on prior art to Flatters et al, applicants’ have argued that Flatters et al fails to disclose that a backshort dielectric layer and the PCB dielectric layer have the same dielectric material. Moreover, applicants’ contend that, although Shono does teach that the lid and substrate can be of the “same dielectric material”, such a recognition does not emphasize or rely on such sameness to solve any particular technical problem. Applicants’ further contend that the examiners selection of the “same material” is merely a design consideration in contrast to specific reasons for using the “same dielectric material” in applicants’ invention. Additionally, applicants’ contend that a “broadest reasonable interpretation” (i.e. BRI) must include an intentional selection of the “same dielectric material” within the context of applicants’ invention. Accordingly, applicants’ contention that even with the teaching of the “same dielectric material” by Shono, the resultant combination of Shono with Flatters et al would still be deficient as it would not resolve the desired problems.
In response, the examiner has considered those arguments and have reached the following conclusion: As evident from the above new grounds of rejection, Flatters et al, when taken in combination with the Shono reference clearly discloses that the obviousness of having the PCB dielectric layer being the same dielectric material as the dielectric material of the backshort dielectric layer, consistent with the teaching in Shono, and thus the resultant combination continues to meet the above cited claims. It should be noted that up until this point, applicants’ has not raised any issues about the lid and substrate being of the “same dielectric material” and thus the examiners desired selection of the “same dielectric material” in the resultant combination would have been consistent and appropriate based on “on its face” from the teachings in the combination of references. Now, it appears that the “same dielectric material” limitation has taken a degree of “criticality” in the determination of patentability. Even with applicants’ emphasis on a particular critical purpose, benefit or rationale for using the “same dielectric material”, such does not preclude the examiner from selecting the “same dielectric material” as a mere design consideration based on what Shono teaches as the broadest reasonable interpretation. It should be noted that the claims have not placed any explicit limits on what characterizes the “same dielectric material” as to its explicit function or purpose and as such, the examiner will not read any such limits (i.e. function, purpose) from the specification into the claims (i.e. the BRI is merely the consideration to use the same dielectric material). However, the examiner does recognize the critical nature of the “same dielectric material” limitation, and in an effort to expedite prosecution, the examiner does suggest that perhaps if the purpose or rationale of using the “same dielectric material” were to be added to the respective independent claims, then such could be considered sufficient to distinguish over the prior art rejections. For example, perhaps by adding --to minimize thermal (mismatches/effects) in the waveguide interface arrangement-- prior to the end of each independent claim, such limitation would be consistent with the originally filed specification and deemed satisfactory to distinguish over the prior art rejections (note that the “mismatches/effects” are each acceptable alternatives and selecting one or the other alternative would distinguish over the prior art). Otherwise, the examiner believes that the obviousness combination continues to meet applicants’ claimed invention.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication should be directed to BENNY T LEE at telephone number (571) 272-1764.
/BENNY T LEE/PRIMARY EXAMINER
ART UNIT 2843
B. Lee