DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 03/09/26 has been entered.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 9-11, and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Saita et al.; US 2009/0242256 A1; 03/2009 in view of Okubora; US 2005/0146403 A1; 01/2003 and Nakamura et al. US 2015/0145011 A1; 06/2015.
Claim 1: Saita discloses a thin film capacitor (Fig 1. par [0024] a thin film capacitor) comprising: a metal foil (par [0026] Ni foil #2 may be a base metal foil).
Saita discloses a dielectric film (Fig 1. par [0026] the dielectric film #3) covering the one main surface of the metal foil (Fig 1. #2 and #3) and having an opening through which the metal foil is partly exposed ( Fig 1. Left side gap in #3); a first electrode layer contacting the metal foil through the opening (Fig. 1 par [0025] Cu electrode #4 on left side of Fig. 1); and a second electrode layer contacting the dielectric film without contacting the metal foil (Fig. 1 right side #4 layer on top of #3 not contacting #2).
Saita does not appear to disclose having one roughened main surface; and wherein other main surface of the metal foil is roughened wherein the first and second electrode layers are separated from each other by an annular slit wherein the first electrode layer is provided in a first area surrounded by the slit, and wherein the second electrode layer is provided in a second area positioned outside the slit such that the second electrode layer surrounds the first electrode layer.
Okubora discloses having one roughened main surface; and wherein other main surface of the metal foil is roughened ( [0069] The above organic substrate material #33 is formed by bonding copper foils #35 and #36 whose surfaces are appropriately roughed to top and bottom main sides, respectively of the core substrate #34 ).
Okubura does not appear to disclose the first and second electrode layers are separated from each other by an annular slit wherein the first electrode layer is provided in a first area surrounded by the slit, and wherein the second electrode layer is provided in a second area positioned outside the slit such that the second electrode layer surrounds the first electrode layer.
However, Nakamura teaches the first (Fig 12., #66a) and second (Fig 12., #66b) electrode layers are separated from each other by an annular slit (par [0048] The semiconductor device #20 includes a guard ring G in the boundary region. The guard ring G mainly includes the lower electrode #66c.), wherein the first electrode layer ( Fig 12., #66a) is provided in a first area surrounded by the slit ( [0048] guard ring G), and wherein the second electrode layer (Fig 12, #66b) is provided in a second area positioned outside the slit ( as shown in Fig. 12 ) such that the second electrode layer ( Fig. 2 peripheral circuit region 12; also Fig. 12 peripheral circuit region Z electrode #66b ) surrounds the first electrode layer ( Fig. 2 memory cell regions 11; Fig. 12 #66a ).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention, to utilize the teachings of Nakamura with Saita and Okubura to have one roughened main surface and other main surface of the metal foil is roughened wherein the first and second electrode layers are separated from each other by an annular slit wherein the first electrode layer is provided in a first area surrounded by the slit, and wherein the second electrode layer is provided in a second area positioned outside the slit such that the second electrode layer surrounds the first electrode layer because a rough surface increases the available area for charge storage.
Claim 9: Saita, Okubora, and Nakamura disclose the thin film capacitor as claimed in claim 1 (as discussed above).
Saita discloses a side surface of the metal foil is tapered (Fig 1, Ѳ) and thus other main surface (Fig 1 #2F’) of the metal layer (#2) is larger in area than the one main surface (#2B) of the metal foil.
Claim 10: Saita, Okubora, Nakamura disclose the thin film capacitor as claimed in claim 9 (as discussed above).
Saita discloses an angle formed by the other main surface of the metal foil and the side surface thereof is larger than 20° and less than 80° ( par [0057] “taking the symmetry of the taper angle into consideration, if the angle is such that 60̊ ≤ Ѳ ≤ 85̊ an element can be manufactured with no separation at all.”)
Claim 11: Saita, Okubora, Nakamura disclose the thin film capacitor as claimed in claim 10 (as discussed above).
Saita discloses an angle formed by the other main surface of the metal foil and the side surface thereof is larger than 30° and less than 60° ( par [0040] “the angle made by the either the top face 2F or the bottom face 2B and the side faces 2E is either 0̊ < Ѳ < 89̊ ”).
Claim 21: Saita discloses an electronic circuit substrate ( [0002] an electronic component which is buried so as to be sandwiched between two resin substrates) comprising: a substrate having a wiring pattern ( [0012] the supporting substrate may be a metal foil); a semiconductor IC provided in the substrate ( [0016] an electronic component module of an embodiment of this invention comprises the electronic component, buried so as to be sandwiched between a first resin substrate and a second resin substrate”) ;
Saita, Okubora, Nakamura disclose the thin film capacitor as claimed in claim 1 (as described above).
Saita discloses provided in the substrate ( [0024] thin film capacitor, buried so as to be sandwiched between a glass epoxy resin substrate (first resin substrate) and insulating material (second resin substrate)), wherein the first ( Fig. 1 #4) and second ( Fig. 1 # 6) electrode layers of the thin film capacitor ( as described above) are connected to the semiconductor IC through the wiring pattern (Fig 1. #2).
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Saita et al.; US 2009/0242256 A1; 03/2009 in view of Okubora; US 2005/0146403 A1; 01/2003 and Nakamura et al. US 2015/0145011 A1; 06/2015 as applied to claim 1 above, and further in view of Seiichi et al.; EP 1100295 A2; 09/2000.
Claim 12: Saita, Okubora, and Nakamura disclose the thin film capacitor as claimed in claim 1 (as discussed above).
Neither Saita nor Okubora nor Nakamura appear to disclose wherein a crystal particle diameter of a not-roughened center portion of the metal foil is less than 15 um in a direction parallel to the one main surface and less than 5 um in a direction orthogonal to the one main surface.
However, Seiichi teaches a crystal particle diameter of a not-roughened center portion of the metal foil is less than 15 µm ( [0015] the thickness of the metal layer to be 10 µm or more”) in a direction parallel to the one main surface and less than 5 µm in a direction orthogonal to the one main surface ( [0017] It is preferable that the thickness of the metal foil is in a range of about 3 µm to 18 µm for forming a fine wiring pattern.)
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention, to utilize the teachings of Seiichi with Saita, Okubora, and Nakamura to vary the thickness of the metal foil because thinner material is better for forming a fine wiring pattern, and roughening is better with a slightly thicker material.
Claims 4-7 and 13-15 are rejected under 35 U.S.C. 103 as being unpatentable over Saita et al.; US 2009/0242256 A1; 03/2009 in view of Okubora; US 2005/0146403 A1; 01/2003 and Nakamura et al. US 2015/0145011 A1; 06/2015 as applied to claim 1 above, and further in view of Nakamura et al. US 2015/0145011 A1; 06/2015.
Claim 4: Saita, Okubora, and Nakamura disclose the thin film capacitor as claimed in claim 1 (as discussed above).
Neither Saita nor Okubora appear to disclose further comprising a first insulating member provided inside the slit and positioned between the first and second electrode layers.
However, Nakamura teaches further comprising a first insulating member (Fig. 16, #81) provided inside the slit and positioned between the first (Fig 16, #69a) and second electrode layers (Fig 16, #69b).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention, to utilize the teachings of Nakamura et al. with Saita and Okubora to provide a first insulating member inside the slit and positioned between the first and second electrode layers because it isolates the layers during the wet etching process.
Claim 5: Saita, Okubora, and Nakamura disclose the thin film capacitor as claimed in claim 4 (as discussed above).
Saita discloses the first insulating member and the metal foil contact each other (par [0039] the dielectric element 1a is sandwiched between the glass epoxy resin substrate #10 and the insulating material #30 such that the insulating material #30 faces the bottom face (#2B Ni foil)).
Claim 6: Saita, Okubora, and Nakamura disclose the thin film capacitor as claimed in claim 4 (as discussed above).
Neither Saita nor Okubora appear to disclose the first insulating member is provided on the dielectric film so as not to contact the metal foil.
However, Nakamura teaches the first insulating member (Fig 14., #48) is provided on the dielectric film (Fig 14., #67) so as not to contact the metal foil. (Fig. 14 #68)
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention, to utilize the teachings of Nakamura et al. with Saita and Okubora to have the first insulating member on the dielectric film so as not to contact the metal foil because if the insulating member does not properly insulate the capacitor may short or fail.
Claim 7: Saita, Okubora, and Nakamura disclose the thin film capacitor as claimed in claims 4 (as discussed above).
Saita discloses a second insulating member (Fig 1, #3) provided on the one main surface of the metal foil (#2) and surrounding the second electrode layer (Fig 1, #4 on right side of figure).
Claim 13: Saita, and Okubora disclose the thin film capacitor as claimed in claim 1 (as discussed above).
Neither Saita nor Okubora appear to disclose the second electrode layer includes a first conductive member contacting the dielectric film and made of a conductive polymer material and a second conductive member contacting the first conductive member and made of a metal material.
However, Nakamura teaches the second electrode layer (par [0057] gate electrode #28a) includes a first conductive member (par [0062] gate conductive films #26a) contacting the dielectric film and made of a conductive polymer material ( [0062] a poly-crystalline silicon film containing phosphorous, a tungsten (W) film, a tungsten silicide (WSi) film and a multi-layered film including these films may be used) and a second conductive member (#26b) contacting the first conductive member (#26a) and made of a metal material (par [0062] gate conductive films #26a) contacting the dielectric film and made of a conductive polymer material ( [0062] a poly-crystalline silicon film containing phosphorous, a tungsten (W) film, a tungsten silicide (WSi) film and a multi-layered film including these films may be used).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention, to utilize the teachings of Nakamura et al. with Saita and Okubora to have the second electrode layer include a first conductive member contacting the dielectric film and made of a conductive polymer material and a second conductive member contacting the first conductive member and made of a metal material because a conductive polymer material lowers equivalent series resistance, improves temperature stability and increases safety.
Claim 14: Saita, Okubora, and Nakamura disclose the thin film capacitor as claimed in claim 13 (as discussed above).
Neither Saita nor Okubora appear to disclose the first electrode layer includes a third conductive member contacting the metal foil and made of a conductive polymer material and a fourth conductive member contacting the third conductive member and made of a metal material.
However, Nakamura teaches the first electrode layer (par [0109] an inter-layer insulating film #81 is formed to as to cover the upper electrodes #69a and #69b) includes a third conductive member (#67) contacting the metal foil ( par [0052] the upper electrode #69b is connected to a drawing wire #83b) and made of a conductive polymer material and a fourth conductive member (#82a and #82b contact plugs) contacting the third conductive member (#67) and made of a metal material ( par [0110] The metal wires #83a and #83b are made of aluminum, copper, or the like.)
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention, to utilize the teachings of Nakamura et al. with Saita and Okubora to have the first electrode layer include a third conductive member contacting the metal foil and made of a conductive polymer material and a fourth conductive member contacting the third conductive member and made of a metal material because the polymer material would further improve the performance and stability of the device.
Claim 15: Saita, Okubora, and Nakamura disclose the thin film capacitor as claimed in claim 13 (as discussed above),
Neither Saita nor Okubora appear to disclose wherein the first electrode layer includes a fourth conductive member contacting the metal foil and made of a metal material.
However, Nakamura teaches wherein the first electrode layer ( par [0109] an inter-layer insulating film #81 is formed to as to cover the upper electrodes #69a and #69b) includes a fourth conductive member (#82a and #82b contact plugs) contacting the metal foil and made of a metal material ( par [0110] The metal wires #83a and #83b are made of aluminum, copper, or the like.)
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention, to utilize the teachings of Nakamura et al. with Saita and Okubora to have the first electrode layer include a fourth conductive member contacting the metal foil and made of a metal material because it is a strong conductor and would be the interface between the contact plug and the internal metal foil.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Saita et al.; US 2009/0242256 A1; 03/2009, Okubora; US 2005/0146403 A1; 01/2003, and Nakamura et al.; US 2015/0145011 A1 as applied to claim 4 above, and further in view of Inaba; US 6479342 B1; 01/2000.
Claim 8: Saita, Okubora, and Nakamura disclose the thin film capacitor as claimed in claim 4 (as discussed above),
Neither Saita, Okubora, nor Nakamura appear to disclose the first insulating member has a first side surface contacting the first electrode layer and a second side surface contacting the second electrode layer, and wherein an angle formed by the one main surface of the electrode layer and first side surface of the first insulating member is larger than an angle formed by the one main surface of the electrode layer and the second side surface of the first insulating member.
However, Inaba teaches the first insulating member has a first side surface contacting the first electrode layer (Col 10 line 53-54 “An opening located on the first electrode layer #25 is formed in the second interlayer insulating layer #26) and a second side surface contacting the second electrode layer (#26), and wherein an angle formed by the one main surface of the electrode layer and first side surface of the first insulating member is larger than an angle formed by the one main surface of the electrode layer and the second side surface of the first insulating member (Col 10 lines 57-60 “The inner wall of the opening is preferably not vertical to the upper surface of the first electrode layer 25 but it is tapered so that the diameter thereof is gradually increased upward.”)
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention, to utilize the teachings of Inaba et al. with Saita, Okubora, and Nakamura to have the angle formed by the one main surface of the electrode layer and first side surface of the first insulating member larger than the angle formed by the one main surface of the electrode layer because of the roughness of the metallic foil.
Claims 16 – 18, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Seiichi et al.; EP 1100295 A2; 09/2000 in view of Okubora; US 2005/0146403 A1; 01/2003.
Claim 16: Seiichi discloses a manufacturing method ( [0042] “the method for producing a capacitor-mounted metal foil” ) for a thin film capacitor ( [0054] “forming capacitors on a metal foil” ), the method comprising: roughening one main surface of a metal foil ( [0044] “roughening a surface of a part of the metal film”); forming a dielectric film on the roughened one main surface of the metal foil ( par [0044] lines 57-58 “oxidizing the roughened surface of the metal film to form the metal layer and the dielectric layer”); and forming a first electrode layer ([0080] The metal layer #111 functions as an electrode (anode) of the capacitor #110) that contacts the part of the metal foil (#101) and a second electrode layer ([0084] The conductive layer #113 functions as an electrode (negative electrode) of the capacitor) that contacts the dielectric film (#112) without contacting the part of the metal foil (#101).
Seiichi does not appear to disclose removing a part of the dielectric film to expose a part of the metal foil
However, Okaburo teaches removing a part of the dielectric film to expose a part of the metal foil ( [0081] The first dielectric insulative layer has formed therethrough via holes #30 through which there is exposed a part of the first wiring layer #14 in the base substrate block #2 )
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention, to utilize the teachings of Okaburo with Seiichi to implement removing a part of the dielectric film to expose a part of the metal foil because this step is essential to create electrical connections in a device.
Claim 17: Seiichi and Okaburo disclose the manufacturing method as claimed in claim 16 (as discussed above).
Seiichi teaches forming a first insulating member ( [0105] after the insulating polymer layer #401 is formed on a part of the metal foil #101) that surrounds the part of the metal foil (#101), wherein, after the forming the first insulating member (#401), the first electrode (#111) is formed in an area surrounded by the first insulating member (#401), and the second electrode layer ([0109 lines 19-20 “The electrode #113b can be formed”) is formed outside the first insulating member(#401).
Claim 18: Seiichi and Okaburo disclose the manufacturing method as claimed in claim 17 (as discussed above).
Seiichi teaches forming a second insulating member (#112) that surrounds the first insulating member (Fig 4A and 4B #401), wherein, after the forming the first and second insulating members, the second electrode layer (#113) is formed in an area surrounded by the second insulating member (#112).
Claim 20: Seiichi and Okaburo disclose the manufacturing method as claimed in claim 16 (as discussed above).
Seiichi teaches roughening other main surface of the metal foil ( [0127] a metal film made of copper was formed on the aluminum by electroplating. [0128] the surface of the aluminum was subjected to alternating-current electrochemical etching in a hydrochloric acid solvent. Both sides of the film were immersed in the hydrochloric acid solvent.)
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Seiichi et al.; EP 1100295 A2; 09/2000 in view Okubora; US 2005/0146403 A1; 01/2003 as applied to claim 16 above and further in view of Shioga et al.; US 7940516 B2; 08/2010.
Claim 19: Seiichi and Okuburo disclose the manufacturing method as claimed in claim 16 (as discussed above).
Neither Seiichi nor Okuburo appear to disclose the second electrode layer is formed by forming a first conductive member in a paste or liquid form on the dielectric film and forming a second conductive member made of a metal material on a surface of the first conductive member.
However, Shioga teaches the second electrode layer (col 4, line 42 #12) is formed by forming a first conductive member in a paste (col 4, line 44 “a conductive paste may be used to form the lower electrode #12) or liquid form on the dielectric film (Fig 5 #13 dielectric layer) and forming a second conductive member (#14 upper electrode) made of a metal material (col 6 lines 2-3 “The upper electrode #14 is constituted by the metal part of the valve metal sheet #15”) on a surface of the first conductive member (#12).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention, to utilize the teachings of Shioga with Seiichi and Okuburo to form a first conductive member in a paste on the dielectric film and forming a second conductive member made of metal material on a surface of the first conductive member because the electrostatic capacitance of the capacitor can be increased.
Response to Amendment / Arguments
Applicant's arguments filed 03/09/26 have been fully considered but they are not persuasive.
Applicant’s argument with respect to Claim 1, Nakamura does show the peripheral circuit region 12 in Fig. 2 does surround the memory cell region 11 so that the second electrode layer surrounds the first electrode layer.
Applicant’s argument with respect to Claim 16 that Okubora should not be combined with Seiichi is not persuasive. However, "It is well-established that a determination of obviousness based on teachings from multiple references does not require an actual, physical substitution of elements." In re Mouttet, 686 F.3d 1322, 1332, 103 USPQ2d 1219, 1226 (Fed. Cir. 2012) (citing In re Etter, 756 F.2d 852, 859, 225 USPQ 1, 6 (Fed. Cir. 1985) (en banc)) ("Etter's assertions that Azure cannot be incorporated in Ambrosio are basically irrelevant, the criterion being not whether the references could be physically combined but whether the claimed inventions are rendered obvious by the teachings of the prior art as a whole."). See also In re Keller, 642 F.2d 413, 425, 208 USPQ 871, 881 (CCPA 1981) ("The test for obviousness is not whether the features of a secondary reference may be bodily incorporated into the structure of the primary reference.... Rather, the test is what the combined teachings of those references would have suggested to those of ordinary skill in the art."); In re Sneed, 710 F.2d 1544, 1550, 218 USPQ 385, 389 (Fed. Cir. 1983) ("[I]t is not necessary that the inventions of the references be physically combinable to render obvious the invention under review."); and In re Nievelt, 482 F.2d 965, 179 USPQ 224, 226 (CCPA 1973) ("Combining the teachings of references does not involve an ability to combine their specific structures" ).
Conclusion
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/K.N.F./Examiner, Art Unit 2817
/MARLON T FLETCHER/Supervisory Primary Examiner, Art Unit 2817