DETAILED ACTION
1. Claims 1-20 are pending in the application.
Notice of Pre-AIA or AIA Status
2. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
3. Claims 9 and 10 objected to under 37 CFR 1.75(c) as being in improper form because a multiple dependent claim should refer to other claims in the alternative only. See MPEP § 608.01(n).
Claim Rejections - 35 USC § 103
4. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
5. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
6. Claim(s) 1, 9, and 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nagel et al (hereafter Nagel)(US Pub. 20200293864) in view of Xie et al (hereafter Xie)(US Pub. 20200027556).
7. As to claim 1, Nagel discloses a Graphics Processing Unit (GPU) communication method ([0021]-[0022] GPU), comprising:
decomposing a matrix to be transmitted on each GPU into sub-matrices and a compressed matrix, wherein the compressed matrix obtained by decomposing each matrix to be transmitted is the same ([0048]-[0049] compressing [0050]-[0052] decomposing into sub-matrices);
causing each GPU to perform a reduce operation for respective sub-matrices, such that each GPU obtains an intermediate matrix ([0051]-[0052] rank reduced weight sub-matrix); and
respectively multiplying, by the compressed matrix, one or more intermediate matrices received by each GPU and the intermediate matrix of the GPU itself, so as to obtain a final matrix ([0049], [0051], [0064] multiplying).
8. Nagel does not disclose performing an allgather operation on each GPU, such that each GPU respectively sends the intermediate matrix of the GPU itself to all other GPUs.
However, Xie discloses performing an allgather operation on each GPU, such that each GPU respectively sends the intermediate matrix of the GPU itself to all other GPUs ([0121] all-gather execution).
9. Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to modify the teachings of Nagel, by incorporating an all-gather operation, as in Xie, for the benefit of reducing the latency of inter-machine gpu-gpu communication (Xie, [0123]).
10. As to claims 9 and 10, the combination of Nagel and Xie disclose a computer device, comprising: at least one processor; and a memory, which stores a computer program executable on the processor, wherein when executing the computer program, the processor executes the operations of the method according to any one of claims 1-8 and a non-transitory computer-readable storage medium, which stores a computer program, wherein when executed by a processor, the computer program executes the operations of the method according to any one of claims 1-8 ([0007]-[0009]).
Allowable Subject Matter
11. Claims 2-8 and 11-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
12. The following is a statement of reasons for the indication of allowable subject matter:
The claims recite at least wherein causing each GPU to perform the reduce operation for the respective sub-matrices, such that each GPU obtains the intermediate matrix further comprises: performing a compress operation on the intermediate matrix on each GPU; and respectively multiplying, by the compressed matrix, one or more intermediate matrices received by each GPU and the intermediate matrix of the GPU itself, so as to obtain the final matrix further comprises: performing a decompress operation on the one or more intermediate matrices received by each GPU and the intermediate matrix of the GPU itself, and respectively multiplying, by the compressed matrix, the one or more intermediate matrices and the intermediate matrix of the GPU itself, so as to obtain the final matrix; and
wherein causing each GPU to perform the reduce operation for respective sub-matrices, such that each GPU obtains the intermediate matrix comprises: after decomposing, in each GPU, each matrix to be transmitted into sub-matrices and the compressed matrix, respectively sending, by each GPU, a corresponding sub- matrix to all other GPUs, so that each GPU adds one or more received sub-matrices with one sub-matrix of the GPU itself to obtain the intermediate matrix.
The closest prior art of record US Pub. 20200293864 and 20200027556 teach the limitations as in independent claim 1; however, they do not teach or suggest at least wherein causing each GPU to perform the reduce operation for the respective sub-matrices, such that each GPU obtains the intermediate matrix further comprises: performing a compress operation on the intermediate matrix on each GPU; and respectively multiplying, by the compressed matrix, one or more intermediate matrices received by each GPU and the intermediate matrix of the GPU itself, so as to obtain the final matrix further comprises: performing a decompress operation on the one or more intermediate matrices received by each GPU and the intermediate matrix of the GPU itself, and respectively multiplying, by the compressed matrix, the one or more intermediate matrices and the intermediate matrix of the GPU itself, so as to obtain the final matrix; and
wherein causing each GPU to perform the reduce operation for respective sub-matrices, such that each GPU obtains the intermediate matrix comprises: after decomposing, in each GPU, each matrix to be transmitted into sub-matrices and the compressed matrix, respectively sending, by each GPU, a corresponding sub- matrix to all other GPUs, so that each GPU adds one or more received sub-matrices with one sub-matrix of the GPU itself to obtain the intermediate matrix.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL D YAARY whose telephone number is (571)270-1249. The examiner can normally be reached Mon-Fri 9-5:30.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, James Trujillo can be reached at (571)272-3677. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/MICHAEL D. YAARY/ Primary Examiner, Art Unit 2151