DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on December 18, 2025 has been entered.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 2 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 2, the claim states “wherein the wafer source cut out from an ingot is prepared”. Having a statement of something that happened in the past (cut out of an ingot) and then stating the wafer source is prepared (also past tense), is unclear as to the context of this for a method claim. When does that step happen, does it actually have to happen to read on the claimed method, since in the method being claimed it is stated as already happened? The scope of this claim is unclear. It is recommended to recite active method steps “cutting out the wafer source from an ingot (possibly with a specific time in relation to the other steps); and preparing the wafer source after it is cut from the ingot.”
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-7, 9-13 and 23 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by WO 2018/235843 A1 to Aketa et al. (hereinafter “Aketa” – previously cited reference).
Regarding claim 1, Aketa discloses a semiconductor device manufacturing method comprising:
a first supporting step in which a wafer source is supported from one side by a first supporting member (first support member 21 supports wafer source 1 from a first side; Figs. 1A-1B; paragraphs [0015], [0029]);
a step of forming a modified layer along a horizontal direction in a thickness direction intermediate portion of the wafer source (modified layer 34 formed along horizontal direction in thickness direction intermediate portion of wafer source 1; Fig. 3E; paragraph [0076]);
a second supporting step in which the wafer source is supported from the other side by a second supporting member (second support member 31 supporting wafer source 1 from a second side; Fig. 3D; paragraph [0069]);
a separating step in which the wafer source is cut in the horizontal direction from the thickness direction intermediate portion, and in which a wafer structure that includes the second supporting member and a wafer cut away from the wafer source is separated from the wafer source (wafer source 1 is cut in a thickness direction in a middle portion thereof in order to create an element formation wafer 41 coupled to second support member 31 and a non-formation wafer 42; Fig. 3F; paragraphs [0076]-[0080]); and
a step of forming a functional device to a section plane of the wafer (semiconductor element 11 formed to section plane of wafer 41; Fig. 3G; paragraph [0080]).
Regarding claim 2, Aketa discloses the semiconductor device manufacturing method according to Claim 1, wherein the wafer source cut out from an ingot is prepared (SiC monocrystal wafer source 1 may have a thickness of 1000 microns which is inherently sourced from a monocrystalline ingot; paragraphs [0016]-[0018]).
Regarding claim 3, Aketa discloses the semiconductor device manufacturing method according to Claim 1, further comprising: a step of transferring the wafer structure (element formation wafers 41 are moved for further processing, such as for chemical mechanical polishing; paragraph [0081]).
Regarding claim 4, Aketa discloses the semiconductor device manufacturing method according to Claim 1, further comprising: a wafer source reusing step in which a series of steps including the second supporting step and the separating step are repeated until the wafer source becomes unable to be separated (non-formation wafers are used to cut new wafer source 1 via steps S4-S7 until non-formation wafers can no longer be reused as a new semiconductor wafer source; Fig. 2A; paragraph [0120]).
Regarding claim 5, Aketa discloses the semiconductor device manufacturing method according to Claim 1, wherein the modified layer is formed by a laser light irradiation method (modified layer 34 created by laser irradiation along a horizontal direction in a thickness direction of the wafer source 1; paragraphs [0076]-[0079]).
Regarding claim 6, Aketa discloses the semiconductor device manufacturing method according to Claim 1, further comprising: a step of forming an epitaxial layer on the section plane of the wafer; and wherein the functional device is formed in the epitaxial layer (forming an epitaxial layer 29 on section plane of wafer 41 with semiconductor element 11 formed in layer 29; Fig. 3G; paragraph [0080]).
Regarding claim 7, Aketa discloses the semiconductor device manufacturing method according to Claim 6, further comprising: a step of polishing the section plane; and wherein the epitaxial layer is formed on the polished surface of the wafer (epitaxial layer 29 may be formed upon the polished main surface 2 of the wafer source 1; paragraph [0063]).
Regarding claim 9, Aketa discloses the semiconductor device manufacturing method according to Claim 1, further comprising: a step of polishing the section plane; wherein the functional device is formed in the polished surface of the wafer (epitaxial layer 29 may be formed within the polished main surface 2 of the wafer source 1; paragraph [0063]).
Regarding claim 10, Aketa discloses the semiconductor device manufacturing method according to Claim 1, further comprising: a step of removing the second supporting member from the wafer after the step of forming the functional device (second support member 31 is removed from wafer 41 after semiconductor element 11 formed; paragraphs [0063], [0100]).
Regarding claim 11, Aketa discloses the semiconductor device manufacturing method according to Claim 1, wherein the first supporting member is constituted of a same material as a material of the wafer source (wafer source 1 and support member 21 may be made from SiC; paragraphs [0015], [0040], [0055]).]).
Regarding claim 12, Aketa discloses the semiconductor device manufacturing method according to Claim 11, wherein the wafer source is constituted of an SiC monocrystal, and the first supporting member is constituted of an SiC monocrystal or an SiC polycrystal (wafer source 1 and support member 21 may be made from SiC monocrystal; paragraphs [0015], [0040], [0055]).
Regarding claim 13, Aketa discloses the semiconductor device manufacturing method according to Claim 1, wherein the first supporting member is bonded to the wafer source by a direct bonding method (wafer source 1 may be bonded to the first support member 21 by a direct wafer bonding method; paragraph [0055]).
Regarding claim 23, Aketa discloses the semiconductor device manufacturing method according to Claim 5, wherein the separating step includes a step of cleaving the wafer source in the horizontal direction with the modified layer as a starting point (wafer source 1 is cleaved along modified layer 34 in horizontal direction; Fig. 3F; paragraph [0079]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 21 and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Aketa.
Regarding claim 21, Aketa discloses the semiconductor device manufacturing method according to Claim 1, wherein a laser light is directly irradiated toward an inner portion of the wafer source (modified layer 34 created by laser irradiation along a horizontal direction in a thickness direction of the wafer source 1; paragraphs [0076]-[0079]).
Aketa fails to explicitly disclose the laser light being irradiated toward the other side of the wafer source, prior to the second supporting step.
However, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Aketa in this manner in order to potentially provide minimized ablation debris, undesired micro-cracks, or thermal effects in active areas while also accommodating wafers with delicate surface features (membranes, films, dielectrics etc.) on one side or the other.
Regarding claim 22, Aketa discloses semiconductor device manufacturing method according to Claim 1.
Aketa fails to explicitly disclose wherein the other side of the wafer source is a carbon plane.
However, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Aketa in this manner in order to potentially provide utilization of the wafer cleavage plane with the lowest fracture energy and weakest interatomic bonding relative the other planes.
Response to Arguments
Applicant's arguments filed December 18, 2025 have been fully considered. Applicant substantively amended claim 1 and provided associated arguments. Applicant argues on page 8 of the Response that Aketa discloses a method whereby the element forming wafer 41 is reused as the new semiconductor wafer source 51, but this does not appear to be the case. Examiner asserts that the Fig. 2A flowchart and Figs. 3F-3H illustrate that it is the element-unformed wafer 42 that is reused. Additionally, while Examiner agrees that Aketa does not appear to explicitly disclose functional device creation after wafer separation, this is not presently claimed in amended claim 1. Therefore, amended claim 1 is disclosed by Aketa. Further, while a single-reference obviousness statement was provided for claims 21 and 22 given the content of those claims, such limitations are readily disclosed in related references such as US 2018/0154542 A1 to Hirata.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to IAN DEGRASSE whose telephone number is (571) 272-0261. The examiner can normally be reached Monday through Friday 8:30a until 5:00p.
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/IAN DEGRASSE/Examiner, Art Unit 2818
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818