DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-7, 9-13 and 21-23 are rejected under 35 U.S.C. 103 as being unpatentable over WO 2018/235843 A1 to Aketa et al. (hereinafter “Aketa” – previously cited reference).
Regarding claim 1, Aketa discloses a semiconductor device manufacturing method comprising:
a first supporting step in which a wafer source is supported from one side by a first supporting member (first support member 21 supports wafer source 1 from a first side; Figs. 1A-1B; paragraphs [0015], [0029]);
a step of forming a modified layer along a horizontal direction in a thickness direction intermediate portion of the wafer source (modified layer 34 formed along horizontal direction in thickness direction intermediate portion of wafer source 1; Fig. 3E; paragraph [0076]);
a second supporting step in which the wafer source is supported from another side thereof by a second supporting member (second support member 31 supporting wafer source 1 from a second side; Fig. 3D; paragraph [0069]);
a separating step in which the wafer source is cut in the horizontal direction from the thickness direction intermediate portion, and in which a wafer structure that includes the second supporting member and a wafer cut away from the wafer source is separated from the wafer source (wafer source 1 is cut in a thickness direction in a middle portion thereof in order to create an element formation wafer 41 coupled to second support member 31 and a non-formation wafer 42; Fig. 3F; paragraphs [0076]-[0080]); and
a step of forming a functional device to a section plane of the wafer (semiconductor element 11 formed to section plane of wafer 41; Fig. 3G; paragraph [0080]).
Aketa fails to explicitly disclose the second supporting step being performed after the step of forming the modified layer.
However, Aketa paragraphs [0072] and [0095] disclose that the source 1 may have the same or greater thickness than the first support member 21 and may be made from the same material which strongly suggests that source 1 has rigidity enough to be self-supporting. Further, Aketa paragraphs [0010]-[0012] and thereafter disclose that the source 1 has a thickness enough to be cut along a horizontal direction parallel to the first main surface from a thickness direction intermediate portion which also suggests the source 1 as being self-supporting. Additionally, Aketa paragraph [0127] discloses that the support member 31 is only used for protection against external forces and not as part of the means of actually forming altered layer 34 which further suggests that layer 34 can be formed without being supported by member 31.
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Aketa with this predictable variation in order to potentially provide reduced risk of affecting laser transmission/focusing and introduction of unwanted particles during irradiation in line with known techniques in the art such as ‘stealth dicing’ and ‘dicing before grinding’ which are disclosed in patents such as US 9,093,518 B1 to Lei et al. (hereinafter “Lei” – newly cited reference). Lei Figs. 4-5 disclose laser irradiation of a wafer from front or back sides while being adhered to a carrier tape on only one side.
Regarding claim 2, Aketa discloses the semiconductor device manufacturing method according to Claim 1, further comprising: a step of preparing the wafer source by cutting out the wafer source from an ingot, prior to the first supporting step (SiC monocrystal wafer source 1 may have a thickness of 1000 microns which is inherently sourced from a monocrystalline ingot prior to being attached to any support members; paragraphs [0016]-[0018]).
Regarding claim 3, Aketa discloses the semiconductor device manufacturing method according to Claim 1, further comprising: a step of transferring the wafer structure (element formation wafers 41 are moved for further processing, such as for chemical mechanical polishing; paragraph [0081]).
Regarding claim 4, Aketa discloses the semiconductor device manufacturing method according to Claim 1, further comprising: a wafer source reusing step in which a series of steps including the second supporting step and the separating step are repeated until the wafer source becomes unable to be separated (non-formation wafers are used to cut new wafer source 1 via steps S4-S7 until non-formation wafers can no longer be reused as a new semiconductor wafer source; Fig. 2A; paragraph [0120]).
Regarding claim 5, Aketa discloses the semiconductor device manufacturing method according to Claim 1, wherein the modified layer is formed by a laser light irradiation method (modified layer 34 created by laser irradiation along a horizontal direction in a thickness direction of the wafer source 1; paragraphs [0076]-[0079]).
Regarding claim 6, Aketa discloses the semiconductor device manufacturing method according to Claim 1, further comprising: a step of forming an epitaxial layer on the section plane of the wafer; and wherein the functional device is formed in the epitaxial layer (forming an epitaxial layer 29 on section plane of wafer 41 with semiconductor element 11 formed in layer 29; Fig. 3G; paragraph [0080]).
Regarding claim 7, Aketa discloses the semiconductor device manufacturing method according to Claim 6, further comprising: a step of polishing the section plane; and wherein the epitaxial layer is formed on the polished surface of the wafer (epitaxial layer 29 may be formed upon the polished main surface 2 of the wafer source 1; paragraph [0063]).
Regarding claim 9, Aketa discloses the semiconductor device manufacturing method according to Claim 1, further comprising: a step of polishing the section plane; wherein the functional device is formed in the polished surface of the wafer (epitaxial layer 29 may be formed within the polished main surface 2 of the wafer source 1; paragraph [0063]).
Regarding claim 10, Aketa discloses the semiconductor device manufacturing method according to Claim 1, further comprising: a step of removing the second supporting member from the wafer after the step of forming the functional device (second support member 31 is removed from wafer 41 after semiconductor element 11 formed; paragraphs [0063], [0100]).
Regarding claim 11, Aketa discloses the semiconductor device manufacturing method according to Claim 1, wherein the first supporting member is constituted of a same material as a material of the wafer source (wafer source 1 and support member 21 may be made from SiC; paragraphs [0015], [0040], [0055]).]).
Regarding claim 12, Aketa discloses the semiconductor device manufacturing method according to Claim 11, wherein the wafer source is constituted of an SiC monocrystal, and the first supporting member is constituted of an SiC monocrystal or an SiC polycrystal (wafer source 1 and support member 21 may be made from SiC monocrystal; paragraphs [0015], [0040], [0055]).
Regarding claim 13, Aketa discloses the semiconductor device manufacturing method according to Claim 1, wherein the first supporting member is bonded to the wafer source by a direct bonding method (wafer source 1 may be bonded to the first support member 21 by a direct wafer bonding method; paragraph [0055]).
Regarding claim 21, Aketa discloses the semiconductor device manufacturing method according to Claim 1, wherein a laser light is directly irradiated toward an inner portion of the wafer source (modified layer 34 created by laser irradiation along a horizontal direction in a thickness direction of the wafer source 1; paragraphs [0076]-[0079]).
Aketa fails to explicitly disclose the laser light being irradiated toward the other side of the wafer source, prior to the second supporting step.
However, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Aketa in this manner in order to potentially provide minimized ablation debris, undesired micro-cracks, or thermal effects in active areas while also accommodating wafers with delicate surface features (membranes, films, dielectrics etc.) on one side or the other.
Regarding claim 22, Aketa discloses semiconductor device manufacturing method according to Claim 1.
Aketa fails to explicitly disclose wherein the other side of the wafer source is a carbon plane.
However, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Aketa in this manner in order to potentially provide utilization of the wafer cleavage plane with the lowest fracture energy and weakest interatomic bonding relative the other planes.
Regarding claim 23, Aketa discloses the semiconductor device manufacturing method according to Claim 5, wherein the separating step includes a step of cleaving the wafer source in the horizontal direction with the modified layer as a starting point (wafer source 1 is cleaved along modified layer 34 in horizontal direction; Fig. 3F; paragraph [0079]).
Response to Arguments
Applicant's arguments filed May 1, 2026 have been fully considered. Applicant presents amendments to claims 1-2 and corresponding arguments that amended claim 1 overcomes the 35 USC 102 rejection using Aketa. Examiner agrees as Aketa fails to explicitly disclose the second supporting step being performed after the step of forming the modified layer. However, for the reasons outlined above, such a modification of Aketa would be obvious and so amended claim 1 Is obvious over Aketa. Applicant further asserts that claims 21-22 are not obvious over Aketa but does not provide any substantive reasoning to support this statement. Therefore, claims 1-7, 9-13 and 21-23 are obvious over Aketa.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to IAN DEGRASSE whose telephone number is (571) 272-0261. The examiner can normally be reached Monday through Friday 8:30a until 5:00p.
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/IAN DEGRASSE/Examiner, Art Unit 2818
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818
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