DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
RESPONSE TO ARGUMENTS
Applicant’s arguments with respect to claims 1, 5-19, 22 and 40-42 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
In response to applicant’s arguments with regard to the independent claim 22 rejected under 35 U.S.C. 103(a) that the contenting following “A method of using computing apparatus to perform computing, wherein” does not constitute the preamble portion, but should be classified as the characteristic portion; applicant's arguments have fully been considered, but are not found to be persuasive.
The examiner respectfully disagrees, Please note that when reading the preamble in the context of the entire claim, the recitation of “… A method of using a computing apparatus to perform computing, wherein the computing apparatus comprises a processing circuit array, which is formed by connecting a plurality of processing circuits in a one-dimensional or multi-dimensional array structure, and the processing circuit array is configured to a plurality of parallelly operable processing circuit sub-arrays, the computing apparatus further comprises a control circuit configured to configure the processing circuit array according to configuration information to obtain the plurality of processing circuit sub-arrays …” is not limiting because the body of the claim describes a complete invention and the language recited solely in the preamble does not provide any distinct definition of any of the claimed invention’s limitations. Thus, the preamble of the claim(s) is not considered a limitation and is of no significance to claim construction. See Pitney Bowes, Inc. v. Hewlett-Packard Co., 182 F.3d 1298, 1305, 51 USPQ2d 1161, 1165 (Fed. Cir. 1999). See MPEP § 2111.02.
If applicant disagrees with the examiner’s understanding of independent claim 22, wherein the above preamble recites the purpose/intended use of the claimed method, the examiner requests applicant to specify which portion of independent claim 22 is considered as the preamble of the claim.
I. REJECTIONS BASED ON PRIOR ART
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 5-10, 14-19, 22 and 40-42 are rejected under 35 U.S.C. 103 as being unpatentable over Tanner (US Pub.: 2021/0048991) in view of Kesiraju et al. (US Pub.: 2020/0272597), Pellizzer et al. (US Pub.: 2005/0062497), and Seo et al. (US Patent 10,120,833).
As per claim 1, Tanner teaches/suggests a computing apparatus comprising: a processing circuit array, which is formed by connecting a plurality of processing circuits (e.g. associated with array of processing elements: [0047]; [0479]-[0480]), wherein the processing circuit array is configured to perform a multi-thread operation in response to receiving instruction (e.g. associated with multi-thread operations: [0482]), wherein a plurality of operation instructions are obtained by parsing a computing instruction received by the computing apparatus (e.g. associated with decoder parsing instruction to perform operations: [0409]) ([0409]; and [0479]-[0496]).
Tanner does not expressly teach the computing apparatus comprising:
being in a one-dimensional or multi-dimensional array structure, being configured to a plurality of parallel operable processing circuit sub-arrays and receiving a plurality of operation instructions, and each processing circuit sub-array is configured to perform at least one operation instruction in the plurality of operation instructions; and
the computing apparatus further comprises a control circuit configured to configure the processing circuit array according to configuration information to obtain the plurality of processing circuit sub arrays.
Kesiraju teaches/suggests a computing apparatus comprising: being in a one-dimensional or multi-dimensional array structure (Fig. 3-4), having a plurality of processing circuit sub-arrays (Fig. 5-7) and receiving a plurality of operation instructions (e.g. associated with decode unit (34) providing operations (ops) to be received by the processing elements for execution), and each processing circuit sub-array is configured to perform operation accordingly ([0049]-[0050]; [0056]-[0057]; and [0061]); and the computing apparatus further comprises the plurality of processing circuit sub arrays (Fig. 5-7) (Claim 17; Fig. 1-7; [0034]-[0035]; and [0049]-[0077]).
Pellizzer teaches/suggests a computing apparatus comprising: being configured to a processing architecture (e.g. associated with implementing/configuring a new computational architecture via programming: Fig. 1A; [0004]-[0005]; and comprising a control circuit (e.g. associated with control unit (125)) configured to configure the processing circuit array according to configuration information to obtain processing architecture (e.g. associated with control unit implementing computation architecture: Fig. 1A; [0004]-[0005]; [0007]-[0008]) (Fig. 1A-1B; [0004]-[0016]; [0046]; and [0068]-[0069]).
Seo teaches/suggests a computing apparatus comprising: being configured to parallelly operable processing architecture, and to perform at least one operation instruction in the plurality of operation instructions (e.g. associated with dynamically selecting processing elements to process instructions in parallel: col. 7, l. 34 to col. 8, l. 31; and col. 9, l. 47 to col. 10, l. 51) (Claim 1; and col. 5, l. 3 to col. 10, l. 65).
It would have been obvious for one of ordinary skill in this art, before the effective filing date of the claimed invention, to include Kesiraju’s array architectures, Pellizzer’s control unit and Seo’s parallel operations into Tanner’s apparatus for the benefit of implementing an optimized architecture (Kesiraju, [0003]-[0004]) and implementing new computational architecture by simply re-programming logic functions, interconnection via fast transferring operation (Pellizzer, [0005]; and [0050]), and better manage resources by decreasing inefficiency and enhancing processing speed (Seo, col. 7, ll. 56-58) to obtain the invention as specified in claim 1.
As per claim 5, Tanner, Kesiraju, Pellizzer and Seo teach/suggest all the claimed features of claim 1 above, where Tanner, Kesiraju, Pellizzer and Seo further teach/suggest the computing apparatus comprising wherein the plurality of operation instructions comprise at least one multi-stage pipeline operation, and the multi-stage pipeline operation comprises at least two operation instructions (Tanner, [0409]; [0479]-[0496]; Kesiraju, Fig. 1-7; [0034]-[0035]; [0049]-[0077]; Pellizzer, Fig. 1A-1B; [0004]-[0016]; [0046]; [0068]-[0069]; and Seo, Claim 1; col. 5, l. 3 to col. 10, l. 65).
As per claim 6, Tanner, Kesiraju, Pellizzer and Seo teach/suggest all the claimed features of claim 1 above, where Tanner, Kesiraju, Pellizzer and Seo further teach/suggest the computing apparatus comprising wherein the operation instruction comprises a predicate, and each processing circuit judges whether to perform an associated operation instruction according to the predicate (Tanner, [0409]; [0479]-[0496]; Kesiraju, Fig. 1-7; Fig. 12-14; [0034]-[0035]; [0049]-[0077]; [0093]-[0100]; Pellizzer, Fig. 1A-1B; [0004]-[0016]; [0046]; [0068]-[0069]; and Seo, Claim 1; col. 5, l. 3 to col. 10, l. 65).
As per claim 7, Tanner, Kesiraju, Pellizzer and Seo teach/suggest all the claimed features of claim 1 above, where Tanner, Kesiraju, Pellizzer and Seo further teach/suggest the computing apparatus comprising wherein the processing circuit array is a one-dimensional array, and one or a plurality of processing circuits in the processing circuit array are configured to serve as one processing circuit sub-array (Tanner, [0409]; [0479]-[0496]; Kesiraju, Fig. 1-7; [0034]-[0035]; [0049]-[0077]; Pellizzer, Fig. 1A-1B; [0004]-[0016]; [0046]; [0068]-[0069]; and Seo, Claim 1; col. 5, l. 3 to col. 10, l. 65).
As per claim 8, Tanner, Kesiraju, Pellizzer and Seo teach/suggest all the claimed features of claim 1 above, where Tanner, Kesiraju, Pellizzer and Seo further teach/suggest the computing apparatus comprising wherein the processing circuit array is a two-dimensional array, wherein one or more rows of processing circuits in the processing circuit array are configured to serve as one processing circuit sub-array; or one or more columns of processing circuits in the processing circuit array are configured to serve as one processing circuit sub-array; or one or more rows of processing circuits along a diagonal direction of the processing circuit array are configured to serve as one processing circuit sub-array (Tanner, [0409]; [0479]-[0496]; Kesiraju, Fig. 1-7; [0034]-[0035]; [0049]-[0077]; Pellizzer, Fig. 1A-1B; [0004]-[0016]; [0046]; [0068]-[0069]; and Seo, Claim 1; col. 5, l. 3 to col. 10, l. 65).
As per claim 9, Tanner, Kesiraju, Pellizzer and Seo teach/suggest all the claimed features of claim 8 above, where Tanner, Kesiraju, Pellizzer and Seo further teach/suggest the computing apparatus comprising wherein the plurality of processing circuits located in the two-dimensional array are configured to be connected in a predetermined two-dimensional interval mode with one or more of the remaining processing circuits in the same row, column, or diagonal in at least one of row, column, or diagonal directions of the plurality of processing circuits (Tanner, [0409]; [0479]-[0496]; Kesiraju, Fig. 1-7; [0034]-[0035]; [0049]-[0077]; Pellizzer, Fig. 1A-1B; [0004]-[0016]; [0046]; [0068]-[0069]; and Seo, Claim 1; col. 5, l. 3 to col. 10, l. 65).
As per claim 10, Tanner, Kesiraju, Pellizzer and Seo teach/suggest all the claimed features of claim 9 above, where Tanner, Kesiraju, Pellizzer and Seo further teach/suggest the computing apparatus comprising wherein the predetermined two-dimensional interval mode is associated with the number of processing circuits spaced in the connection (Tanner, [0409]; [0479]-[0496]; Kesiraju, Fig. 1-7; [0034]-[0035]; [0049]-[0077]; Pellizzer, Fig. 1A-1B; [0004]-[0016]; [0046]; [0068]-[0069]; and Seo, Claim 1; col. 5, l. 3 to col. 10, l. 65).
As per claim 14, Tanner, Kesiraju, Pellizzer and Seo teach/suggest all the claimed features of claim 7 above, where Tanner, Kesiraju, Pellizzer and Seo further teach/suggest the computing apparatus comprising wherein the plurality of processing circuits in the processing circuit sub-array are formed into one or a plurality of closed loops (Tanner, [0092]; [0409]; [0479]-[0496]; Kesiraju, Fig. 1-7; [0034]-[0035]; [0049]-[0077]; [0101]-[0104]; Pellizzer, Fig. 1A-1B; [0004]-[0016]; [0046]; [0068]-[0069]; and Seo, Claim 1; col. 5, l. 3 to col. 10, l. 65).
As per claim 15, Tanner, Kesiraju, Pellizzer and Seo teach/suggest all the claimed features of claim 1 above, where Tanner, Kesiraju, Pellizzer and Seo further teach/suggest the computing apparatus comprising wherein each processing circuit sub-array is suitable for performing at least one of following operations: an arithmetic operation, a logical operation, a comparison operation, and a lookup table operation (Tanner, [0409]; [0479]-[0496]; Kesiraju, Fig. 1-7; [0034]-[0035]; [0049]-[0077]; Pellizzer, Fig. 1A-1B; [0004]-[0016]; [0046]; [0068]-[0069]; and Seo, Claim 1; col. 5, l. 3 to col. 10, l. 65).
As per claim 16, Tanner, Kesiraju, Pellizzer and Seo teach/suggest all the claimed features of claim 1 above, where Tanner, Kesiraju, Pellizzer and Seo further teach/suggest the computing apparatus further comprising a data operating circuit, which comprises a pre-operating circuit and/or a post-operating circuit, wherein the pre-operating circuit is configured to perform pre-processing on input data of at least one operation instruction, and the post-operating circuit is configured to perform post-processing on output data of at least one operation instruction (Tanner, [0409]; [0479]-[0496]; Kesiraju, Fig. 1-7; [0034]-[0035]; [0049]-[0077]; Pellizzer, Fig. 1A-1B; [0004]-[0016]; [0046]; [0068]-[0069]; and Seo, Claim 1; col. 5, l. 3 to col. 10, l. 65).
As per claim 17, Tanner, Kesiraju, Pellizzer and Seo teach/suggest all the claimed features of claim 16 above, where Tanner, Kesiraju, Pellizzer and Seo further teach/suggest the computing apparatus comprising wherein the pre-processing comprises data placement and/or lookup table operations, and the post-processing comprises data type conversion and/or compression operations (Tanner, [0379]-[0380]; [0409]; [0479]-[0496]; Kesiraju, Fig. 1-7; [0034]-[0035]; [0049]-[0077]; Pellizzer, Fig. 1A-1B; [0004]-[0016]; [0046]; [0068]-[0069]; and Seo, Claim 1; col. 5, l. 3 to col. 10, l. 65).
As per claim 18, Tanner, Kesiraju, Pellizzer and Seo teach/suggest all the claimed features of claim 17 above, where Tanner, Kesiraju, Pellizzer and Seo further teach/suggest the computing apparatus comprising wherein the data placement comprises sending input data and/or output data of the operation instruction to corresponding processing circuits for operations after splitting or merging the input data and/or the output data of the operation instruction accordingly according to a data type of the input data and/or the output data of the operation instruction (Tanner, [0379]-[0380]; [0409]; [0479]-[0496]; Kesiraju, Fig. 1-7; [0034]-[0035]; [0049]-[0077]; Pellizzer, Fig. 1A-1B; [0004]-[0016]; [0046]; [0068]-[0069]; and Seo, Claim 1; col. 5, l. 3 to col. 10, l. 65).
As per claim 19, Tanner, Kesiraju, Pellizzer and Seo teach/suggest all the claimed features of claim 1 above, where Tanner, Kesiraju, Pellizzer and Seo further teach/suggest an integrated circuit chip, comprising the computing apparatus of claim 1 (Tanner, [0409]; [0479]-[0496]; Kesiraju, Fig. 1-7; Fig. 18; [0034]-[0035]; [0049]-[0077]; [0113]; Pellizzer, Fig. 1A-1B; [0004]-[0016]; [0046]; [0068]-[0069]; and Seo, Claim 1; col. 5, l. 3 to col. 10, l. 65).
As per claim 22, claim 22 is rejected in accordance to the same rational and reasoning as the above rejection of claim 1, as claim 22 is the method carried out by the computing apparatus of claim 1.
As per claim 40, Tanner, Kesiraju, Pellizzer and Seo teach/suggest all the claimed features of claim 1 above, where Tanner, Kesiraju, Pellizzer and Seo further teach/suggest the computing apparatus comprising wherein an operation code of the computing instruction represents a plurality of operations performed by the processing circuit array, and the control circuit is further configured to acquire and parse the computing instruction to obtain a plurality of operation instructions corresponding to the plurality of operations represented by the operation code (Tanner, [0409]; [0479]-[0496]; Kesiraju, Fig. 1-7; [0034]-[0035]; [0049]-[0077]; Pellizzer, Fig. 1A-1B; [0004]-[0016]; [0046]; [0068]-[0069]; and Seo, Claim 1; col. 5, l. 3 to col. 10, l. 65).
As per claim 41, Tanner, Kesiraju, Pellizzer and Seo teach/suggest all the claimed features of claim 40 above, where Tanner, Kesiraju, Pellizzer and Seo further teach/suggest the computing apparatus comprising wherein the control circuit extracts corresponding configuration information to configure the processing circuit array according to the plurality of operation instructions to obtain the plurality of processing circuit sub-arrays (Tanner, [0409]; [0479]-[0496]; Kesiraju, Fig. 1-7; [0034]-[0035]; [0049]-[0077]; Pellizzer, Fig. 1A-1B; [0004]-[0016]; [0046]; [0068]-[0069]; and Seo, Claim 1; col. 5, l. 3 to col. 10, l. 65).
As per claim 42, Tanner, Kesiraju, Pellizzer and Seo teach/suggest all the claimed features of claim 41 above, where Tanner, Kesiraju, Pellizzer and Seo further teach/suggest the computing apparatus comprising wherein the control circuit comprises a register used for storing configuration information, and the control circuit extracts corresponding configuration information from the register according to the plurality of operation instructions and configures the processing circuit array according to the configuration information to obtain the plurality of processing circuit sub-arrays (Tanner, [0075]; [0409]; [0479]-[0496]; Kesiraju, Fig. 1-7; [0026]; [0034]-[0035]; [0049]-[0077]; Pellizzer, Fig. 1A-1B; [0004]-[0016]; [0046]; [0068]-[0069]; and Seo, Claim 1; col. 5, l. 3 to col. 10, l. 65).
Claims 11-13 are rejected under 35 U.S.C. 103 as being unpatentable over Tanner (US Pub.: 2021/0048991) in view of Kesiraju et al. (US Pub.: 2020/0272597), Pellizzer et al. (US Pub.: 2005/0062497), and Seo et al. (US Patent 10,120,833) as applied to claim 1 above, and further in view of Vorbach et al. (US Pub.: 2012/0216012).
As per claim 11, Tanner, Kesiraju, Pellizzer and Seo teach/suggest all the claimed features of claim 1 above, where Tanner, Kesiraju, Pellizzer and Seo further teach/suggest the computing apparatus comprising sub-arrays in the processing circuit array are configured to serve as one processing circuit sub-array (Tanner, [0409]; [0452]-[0453]; [0479]-[0496]; Kesiraju, Fig. 1-7; [0034]-[0035]; [0049]-[0077]; Pellizzer, Fig. 1A-1B; [0004]-[0016]; [0046]; [0068]-[0069]; and Seo, Claim 1; col. 5, l. 3 to col. 10, l. 65).
Tanner, Kesiraju, Pellizzer and Seo do not expressly teach/suggest the computing apparatus comprising wherein the processing circuit array is a three-dimensional array, and one or a plurality of three-dimensional architecture are operating accordingly.
Vorbach teach/suggest an apparatus comprising wherein the processing circuit array is a three-dimensional array, and one or a plurality of three-dimensional architecture are operating accordingly ([0012]).
It would have been obvious for one of ordinary skill in this art, before the effective filing date of the claimed invention, to include Vorbach’s three dimensional architecture into Tanner, Kesiraju, Pellizzer and Seo’s apparatus for the benefit of improving data processing efficiency, power consumption and software scalability (Vorbach, [0005]; and [0016]) to obtain the invention as specified in claim 11.
As per claim 12, Tanner, Kesiraju, Pellizzer, Seo, and Vorbach teach/suggest all the claimed features of claim 11 above, where Tanner, Kesiraju, Pellizzer, Seo, and Vorbach further teach/suggest the computing apparatus comprising wherein the three-dimensional array is a three-dimensional array composed of a plurality of layers, wherein each layer comprises a two-dimensional array of a plurality of processing circuits arranged along row, column, and diagonal directions, wherein a processing circuit located in the three-dimensional array is configured to be connected in a predetermined three-dimensional interval mode with one or more of the remaining processing circuits in the same row, column, diagonal, or a different layer in at least one of row, column, diagonal, and layer directions of the processing circuit (Tanner, [0409]; [0479]-[0496]; Kesiraju, Fig. 1-7; [0034]-[0035]; [0049]-[0077]; Pellizzer, Fig. 1A-1B; [0004]-[0016]; [0046]; [0068]-[0069]; Seo, Claim 1; col. 5, l. 3 to col. 10, l. 65; and Vorbach, [0012]).
As per claim 13, Tanner, Kesiraju, Pellizzer, Seo, and Vorbach teach/suggest all the claimed features of claim 12 above, where Tanner, Kesiraju, Pellizzer, Seo, and Vorbach further teach/suggest the computing apparatus comprising wherein the predetermined three-dimensional interval mode is associated with the number of intervals and the number of layers of intervals between to-be-connected processing circuits (Tanner, [0409]; [0479]-[0496]; Kesiraju, Fig. 1-7; [0034]-[0035]; [0049]-[0077]; Pellizzer, Fig. 1A-1B; [0004]-[0016]; [0046]; [0068]-[0069]; Seo, Claim 1; col. 5, l. 3 to col. 10, l. 65; and Vorbach, [0012]).
II. CLOSING COMMENTS
CONCLUSION
STATUS OF CLAIMS IN THE APPLICATION
The following is a summary of the treatment and status of all claims in the application as recommended by M.P.E.P. 707.07(i):
CLAIMS REJECTED IN THE APPLICATION
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
DIRECTION OF FUTURE CORRESPONDENCES
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHUN KUAN LEE whose telephone number is (571)272-0671. The examiner can normally be reached Monday-Friday.
IMPORTANT NOTE
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Idriss Alrobaye can be reached on (571) 270-1023. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CHUN KUAN LEE/Primary Examiner
Art Unit 2181 February 18, 2026