DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
CONTINUED EXAMINATION UNDER 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 4/22/2026 has been entered.
RESPONSE TO ARGUMENTS
Applicant’s arguments with respect to claims 1, 5-19, 22, 40 and 42 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
I. REJECTIONS BASED ON PRIOR ART
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 5-10, 14-19, 22, 40 and 42 are rejected under 35 U.S.C. 103 as being unpatentable over Tanner (US Pub.: 2021/0048991) in view of Kesiraju et al. (US Pub.: 2020/0272597), KIM et al. (US Pub.: 2021/0117781) and Brothers et al. (US Pub.: 2017/0011288).
As per claim 1, Tanner teaches/suggests a computing apparatus, comprising: a processing circuit array, which is formed by connecting a plurality of processing circuits, wherein the processing circuit array is configured to operating accordingly (e.g. associated with array of processing elements operating accordingly: [0047]; [0479]-[0480]), wherein the plurality of operation instructions are obtained by parsing a computing instruction received by the computing apparatus ([0409]) ([0047]; [0409]; and [0479]-[0496]).
Tanner does not teach the computing apparatus comprising:
in a one-dimensional or multi-dimensional array structure, a plurality of processing circuit sub-arrays in response to receiving a plurality of operation instructions, wherein the plurality of operation instructions comprise a multi-stage pipeline operation, and each processing circuit sub-array is configured to serve as a different stage of the multi-stage pipeline operation; and
the computing apparatus further comprises a control circuit configured to configure the processing circuit array according to configuration information extracted from the plurality of operation instructions or from a configuration instruction to obtain the plurality of processing circuit sub-arrays.
Kesiraju teaches/suggests a computing apparatus, comprising: in a one-dimensional or multi-dimensional array structure (Fig. 3-4) (Claim 17; Fig. 1-7; [0034]-[0035]; [0049]-[0077]; and [0114])
KIM teaches/suggests a computing apparatus, comprising: a plurality of processing circuit sub-arrays, wherein the plurality of operation instructions comprise a multi-stage pipeline operation, and each processing circuit sub-array is configured to serve as a different stage of the multi-stage pipeline operation; and to obtain the plurality of processing circuit sub-arrays (e.g. associated with neurons/PEs for each of the multiple layers of neural network) (Fig. 1; and [0053]-[0056]).
Brothers teaches/suggests a computing apparatus, comprising: operating in response to receiving a plurality of operation instructions; and the computing apparatus further comprises a control circuit configured to configure the processing circuit array according to configuration information extracted from the plurality of operation instructions or from a configuration instruction (e.g. associated with parsing instructions for controlling processing units within NN processor) ([0022]-[0024]; and [0049]-[0055]).
It would have been obvious for one of ordinary skill in this art, before the effective filing date of the claimed invention, to include Kesiraju’s array architectures, KIM’s neural network layers and Brothers’ neural network instructions into Tanner’s apparatus for the benefit of implementing an optimized architecture (Kesiraju, [0003]-[0004]), increasing processing speed (KIM, [0066]) and optimizing power and performance (Brothers, [0025]) to obtain the invention as specified in claim 1.
As per claim 5, Tanner, Kesiraju, KIM, and Brothers teach/suggest all the claimed features of claim 1 above, where Tanner, Kesiraju, KIM, and Brothers further teach/suggest the computing apparatus comprising: wherein the plurality of operation instructions comprise at least one multi-stage pipeline operation, and the multi-stage pipeline operation comprises at least two operation instructions (Tanner, [0047]; [0409]; [0479]-[0496]; Kesiraju, Claim 17; Fig. 1-7; [0034]-[0035]; [0049]-[0077]; [0114]; KIM, Fig. 1; [0053]-[0056]; and Brothers, [0022]-[0024]; [0049]-[0055]).
As per claim 6, Tanner, Kesiraju, KIM, and Brothers teach/suggest all the claimed features of claim 1 above, where Tanner, Kesiraju, KIM, and Brothers further teach/suggest the computing apparatus comprising: wherein the operation instruction comprises a predicate, and each processing circuit judges whether to perform an associated operation instruction according to the predicate (Tanner, [0047]; [0069]; [0409]; [0411]; [0413]; [0479]-[0496]; Kesiraju, Claim 17; Fig. 1-7; [0034]-[0035]; [0049]-[0077]; [0114]; KIM, Fig. 1; [0053]-[0056]; and Brothers, [0022]-[0024]; [0049]-[0055]).
As per claim 7, Tanner, Kesiraju, KIM, and Brothers teach/suggest all the claimed features of claim 1 above, where Tanner, Kesiraju, KIM, and Brothers further teach/suggest the computing apparatus comprising: wherein the processing circuit array is a one-dimensional array, and one or a plurality of processing circuits in the processing circuit array are configured to serve as one processing circuit sub-array (Tanner, [0047]; [0409]; [0452]-[0453]; [0479]-[0497]; [0530]; Kesiraju, Claim 17; Fig. 1-7; [0034]-[0035]; [0049]-[0077]; [0114]; KIM, Fig. 1; [0053]-[0056]; and Brothers, [0022]-[0024]; [0049]-[0055]), wherein it would have been an obvious design choice to one of ordinary skilled in the art to further implement the above claimed features.
As per claim 8, Tanner, Kesiraju, KIM, and Brothers teach/suggest all the claimed features of claim 1 above, where Tanner, Kesiraju, KIM, and Brothers further teach/suggest the computing apparatus comprising: wherein the processing circuit array is a two-dimensional array, wherein one or more rows of processing circuits in the processing circuit array are configured to serve as one processing circuit sub-array; or one or more columns of processing circuits in the processing circuit array are configured to serve as one processing circuit sub-array; or one or more rows of processing circuits along a diagonal direction of the processing circuit array are configured to serve as one processing circuit sub-array (Tanner, [0047]; [0409]; [0452]-[0453]; [0479]-[0497]; [0530]; Kesiraju, Claim 17; Fig. 1-7; [0034]-[0035]; [0049]-[0077]; [0114]; KIM, Fig. 1; [0053]-[0056]; and Brothers, [0022]-[0024]; [0049]-[0055]), wherein it would have been an obvious design choice to one of ordinary skilled in the art to further implement the above claimed features.
As per claim 9, Tanner, Kesiraju, KIM, and Brothers teach/suggest all the claimed features of claim 8 above, where Tanner, Kesiraju, KIM, and Brothers further teach/suggest the computing apparatus comprising: wherein the plurality of processing circuits located in the two-dimensional array are configured to be connected in a predetermined two-dimensional interval mode with one or more of the remaining processing circuits in the same row, column, or diagonal in at least one of row, column, or diagonal directions of the plurality of processing circuits (Tanner, [0047]; [0409]; [0452]-[0453]; [0479]-[0497]; [0530]; Kesiraju, Claim 17; Fig. 1-7; [0034]-[0035]; [0049]-[0077]; [0114]; KIM, Fig. 1; [0053]-[0056]; and Brothers, [0022]-[0024]; [0049]-[0055]), wherein it would have been an obvious design choice to one of ordinary skilled in the art to further implement the above claimed features.
As per claim 10, Tanner, Kesiraju, KIM, and Brothers teach/suggest all the claimed features of claim 9 above, where Tanner, Kesiraju, KIM, and Brothers further teach/suggest the computing apparatus comprising: wherein the predetermined two-dimensional interval mode is associated with the number of processing circuits spaced in the connection (Tanner, [0047]; [0409]; [0452]-[0453]; [0479]-[0497]; [0530]; Kesiraju, Claim 17; Fig. 1-7; [0034]-[0035]; [0049]-[0077]; [0114]; KIM, Fig. 1; [0053]-[0056]; and Brothers, [0022]-[0024]; [0049]-[0055]), wherein it would have been an obvious design choice to one of ordinary skilled in the art to further implement the above claimed features.
As per claim 14, Tanner, Kesiraju, KIM, and Brothers teach/suggest all the claimed features of claim 7 above, where Tanner, Kesiraju, KIM, and Brothers further teach/suggest the computing apparatus comprising: wherein the plurality of processing circuits in the processing circuit sub-array are formed into one or a plurality of closed loops (Tanner, [0047]; [0409]; [0452]-[0453]; [0479]-[0497]; [0530]; Kesiraju, Claim 17; Fig. 1-7; [0034]-[0035]; [0049]-[0077]; [0114]; KIM, Fig. 1; [0053]-[0056]; and Brothers, [0022]-[0024]; [0049]-[0055]), wherein it would have been an obvious design choice to one of ordinary skilled in the art to further implement the above claimed features.
As per claim 15, Tanner, Kesiraju, KIM, and Brothers teach/suggest all the claimed features of claim 1 above, where Tanner, Kesiraju, KIM, and Brothers further teach/suggest the computing apparatus comprising: wherein each processing circuit sub-array is suitable for performing at least one of following operations: an arithmetic operation, a logical operation, a comparison operation, and a lookup table operation (Tanner, [0047]; [0409]; [0452]-[0453]; [0479]-[0497]; [0530]; Kesiraju, Claim 17; Fig. 1-7; [0034]-[0035]; [0049]-[0077]; [0114]; KIM, Fig. 1; [0053]-[0056]; and Brothers, [0022]-[0024]; [0049]-[0055]), wherein it would have been an obvious design choice to one of ordinary skilled in the art to further implement the above claimed features.
As per claim 16, Tanner, Kesiraju, KIM, and Brothers teach/suggest all the claimed features of claim 1 above, where Tanner, Kesiraju, KIM, and Brothers further teach/suggest the computing apparatus further comprising: a data operating circuit, which comprises a pre-operating circuit and/or a post-operating circuit, wherein the pre-operating circuit is configured to perform pre-processing on input data of at least one operation instruction, and the post-operating circuit is configured to perform post-processing on output data of at least one operation instruction (Tanner, [0047]; [0409]; [0452]-[0453]; [0479]-[0497]; [0530]; Kesiraju, Claim 17; Fig. 1-7; [0034]-[0035]; [0049]-[0077]; [0114]; KIM, Fig. 1; [0053]-[0056]; and Brothers, [0022]-[0024]; [0049]-[0055]), wherein it would have been an obvious design choice to one of ordinary skilled in the art to further implement the above claimed features.
As per claim 17, Tanner, Kesiraju, KIM, and Brothers teach/suggest all the claimed features of claim 16 above, where Tanner, Kesiraju, KIM, and Brothers further teach/suggest the computing apparatus comprising: wherein the pre-processing comprises data placement and/or lookup table operations, and the post-processing comprises data type conversion and/or compression operations (Tanner, [0047]; [0409]; [0452]-[0453]; [0479]-[0497]; [0530]; Kesiraju, Claim 17; Fig. 1-7; [0034]-[0035]; [0049]-[0077]; [0114]; KIM, Fig. 1; [0053]-[0056]; and Brothers, [0022]-[0024]; [0049]-[0055]), wherein it would have been an obvious design choice to one of ordinary skilled in the art to further implement the above claimed features.
As per claim 18, Tanner, Kesiraju, KIM, and Brothers teach/suggest all the claimed features of claim 17 above, where Tanner, Kesiraju, KIM, and Brothers further teach/suggest the computing apparatus comprising: wherein the data placement comprises sending input data and/or output data of the operation instruction to corresponding processing circuits for operations after splitting or merging the input data and/or the output data of the operation instruction accordingly according to a data type of the input data and/or the output data of the operation instruction (Tanner, [0047]; [0409]; [0452]-[0453]; [0479]-[0497]; [0530]; Kesiraju, Claim 17; Fig. 1-7; [0034]-[0035]; [0049]-[0077]; [0114]; KIM, Fig. 1; [0053]-[0056]; and Brothers, [0022]-[0024]; [0049]-[0055]), wherein it would have been an obvious design choice to one of ordinary skilled in the art to further implement the above claimed features.
As per claim 19, claim 19 is rejected in accordance to the same rational and reasoning as the above rejection of claim 1, where Tanner, Kesiraju, KIM, and Brothers further teach/suggest an integrated circuit chip, comprising the computing apparatus of claim 1 (Tanner, [0047]; [0408]-[0409]; [0452]-[0453]; [0479]-[0497]; [0530]; Kesiraju, Claim 17; Fig. 1-7; [0034]-[0035]; [0049]-[0077]; [0114]; KIM, Fig. 1; [0053]-[0056]; and Brothers, [0022]-[0024]; [0049]-[0055]).
As per claim 22, claim 22 is rejected in accordance to the same rational and reasoning as the above rejection of claim 1, as claim 22 is the method carried out by the computing apparatus of claim 1, where Tanner, Kesiraju, KIM, and Brothers further teach/suggest the method comprising using the plurality of processing circuit sub-arrays to perform the multi-stage pipeline operation in response to receiving the plurality of operation instructions (Tanner, [0047]; [0408]-[0409]; [0452]-[0453]; [0479]-[0497]; [0530]; Kesiraju, Claim 17; Fig. 1-7; [0034]-[0035]; [0049]-[0077]; [0114]; KIM, Fig. 1; [0053]-[0056]; and Brothers, [0022]-[0024]; [0049]-[0055]).
As per claim 40, Tanner, Kesiraju, KIM, and Brothers teach/suggest all the claimed features of claim 1 above, where Tanner, Kesiraju, KIM, and Brothers further teach/suggest the computing apparatus comprising: wherein an operation code of the computing instruction represents a plurality of operations performed by the processing circuit array, and the control circuit is further configured to acquire and parse the computing instruction to obtain a plurality of operation instructions corresponding to the plurality of operations represented by the operation code (Tanner, [0047]; [0409]; [0452]-[0453]; [0479]-[0497]; [0530]; Kesiraju, Claim 17; Fig. 1-7; [0034]-[0035]; [0049]-[0077]; [0114]; KIM, Fig. 1; [0053]-[0056]; and Brothers, [0022]-[0024]; [0049]-[0055]), wherein it would have been an obvious design choice to one of ordinary skilled in the art to further implement the above claimed features.
As per claim 42, Tanner, Kesiraju, KIM, and Brothers teach/suggest all the claimed features of claim 1 above, where Tanner, Kesiraju, KIM, and Brothers further teach/suggest the computing apparatus comprising: wherein the control circuit comprises a register used for storing configuration information, and the control circuit extracts corresponding configuration information from the register according to the plurality of operation instructions and configures the processing circuit array according to the configuration information to obtain the plurality of processing circuit sub-arrays (Tanner, [0047]; [0409]; [0452]-[0453]; [0479]-[0497]; [0530]; Kesiraju, Claim 17; Fig. 1-7; [0034]-[0035]; [0049]-[0077]; [0114]; KIM, Fig. 1; [0053]-[0056]; and Brothers, [0022]-[0024]; [0049]-[0055]), wherein it would have been an obvious design choice to one of ordinary skilled in the art to further implement the above claimed features.
Claims 11-13 are rejected under 35 U.S.C. 103 as being unpatentable over Tanner (US Pub.: 2021/0048991) in view of Kesiraju et al. (US Pub.: 2020/0272597), KIM et al. (US Pub.: 2021/0117781) and Brothers et al. (US Pub.: 2017/0011288) as applied to claim 1 above, and further in view of Vorbach et al. (US Pub.: 2012/0216012).
As per claim 11, Tanner, Kesiraju, KIM, and Brothers teach/suggest all the claimed features of claim 1 above, where Tanner, Kesiraju, KIM, and Brothers further teach/suggest the computing apparatus comprising sub-arrays in the processing circuit array are configured to serve as one processing circuit sub-array (Tanner, [0047]; [0409]; [0452]-[0453]; [0479]-[0497]; [0530]; Kesiraju, Claim 17; Fig. 1-7; [0034]-[0035]; [0049]-[0077]; [0114]; KIM, Fig. 1; [0053]-[0056]; and Brothers, [0022]-[0024]; [0049]-[0055]), but do not expressly teach/suggest the computing apparatus comprising wherein the processing circuit array is a three-dimensional array, and one or a plurality of three-dimensional architecture are operating accordingly.
Vorbach teach/suggest an apparatus comprising wherein the processing circuit array is a three-dimensional array, and one or a plurality of three-dimensional architecture are operating accordingly ([0012]).
It would have been obvious for one of ordinary skill in this art, before the effective filing date of the claimed invention, to include Vorbach’s three dimensional architecture into Tanner, Kesiraju, KIM, and Brothers’ apparatus for the benefit of improving data processing efficiency, power consumption and software scalability (Vorbach, [0005]; and [0016]) to obtain the invention as specified in claim 11.
As per claim 12, Tanner, Kesiraju, KIM, Brothers, and Vorbach teach/suggest all the claimed features of claim 11 above, where Tanner, Kesiraju, KIM, Brothers, and Vorbach further teach/suggest the computing apparatus comprising wherein the three-dimensional array is a three-dimensional array composed of a plurality of layers, wherein each layer comprises a two-dimensional array of a plurality of processing circuits arranged along row, column, and diagonal directions, wherein a processing circuit located in the three-dimensional array is configured to be connected in a predetermined three-dimensional interval mode with one or more of the remaining processing circuits in the same row, column, diagonal, or a different layer in at least one of row, column, diagonal, and layer directions of the processing circuit (Tanner, [0047]; [0409]; [0452]-[0453]; [0479]-[0497]; [0530]; Kesiraju, Claim 17; Fig. 1-7; [0034]-[0035]; [0049]-[0077]; [0114]; KIM, Fig. 1; [0053]-[0056]; Brothers, [0022]-[0024]; [0049]-[0055]; and Vorbach, [0012]), wherein it would have been an obvious design choice to one of ordinary skilled in the art to further implement the above claimed features.
As per claim 13, Tanner, Kesiraju, KIM, Brothers, and Vorbach teach/suggest all the claimed features of claim 12 above, where Tanner, Kesiraju, KIM, Brothers, and Vorbach further teach/suggest the computing apparatus comprising wherein the predetermined three-dimensional interval mode is associated with the number of intervals and the number of layers of intervals between to-be-connected processing circuits (Tanner, [0047]; [0409]; [0452]-[0453]; [0479]-[0497]; [0530]; Kesiraju, Claim 17; Fig. 1-7; [0034]-[0035]; [0049]-[0077]; [0114]; KIM, Fig. 1; [0053]-[0056]; Brothers, [0022]-[0024]; [0049]-[0055]; and Vorbach, [0012]), wherein it would have been an obvious design choice to one of ordinary skilled in the art to further implement the above claimed features.
II. CLOSING COMMENTS
CONCLUSION
STATUS OF CLAIMS IN THE APPLICATION
The following is a summary of the treatment and status of all claims in the application as recommended by M.P.E.P. 707.07(i):
CLAIMS REJECTED IN THE APPLICATION
Per the instant office action, claims 1, 5-19, 22, 40, and 42 have received a first action on the merits and are subject of a first action non-final.
DIRECTION OF FUTURE CORRESPONDENCES
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHUN KUAN LEE whose telephone number is (571)272-0671. The examiner can normally be reached Monday-Friday.
IMPORTANT NOTE
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Idriss Alrobaye can be reached on (571) 270-1023. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CHUN KUAN LEE/Primary Examiner
Art Unit 2181 May 02, 2026
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