Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-6, 10, 13, 22, 23, 27, 36 and 43 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by PCT/CN2021/115779, as seen in PGPUB (20240194747).
PNG
media_image1.png
496
863
media_image1.png
Greyscale
Regarding claim 1, Lin teaches a metal oxide thin film transistor, comprising:
a metal oxide semiconductor layer (103) on a base substrate (fig. 1: 20), and
a source electrode (fig. 1: 104) and a drain electrode (fig. 1: 105) being in contact with the metal oxide semiconductor layer;
wherein the metal oxide semiconductor layer comprises a stacked structure, the stacked structure at least comprises a first semiconductor layer (fig. 6: 131) and a second semiconductor layer (fig. 6: 132),
a carrier mobility of the first semiconductor layer is higher than a carrier mobility of the second semiconductor layer (par. 110 and 120; please note that crystallinity affects carrier mobility by controlling the electronic band structure, scattering rates, and interface quality. Higher crystallinity and favorable crystal orientation generally mean fewer scattering events and higher mobility);
the metal oxide semiconductor layer comprises a lower surface, an upper surface and a lateral surface (please see fig. 6 above which shows this configuration between recited elements), and the source electrode is in contact with the lateral surface and the upper surface (please see fig. 6 above which shows this configuration between recited elements);
a region of the lateral surface being in contact with the source electrode or the drain electrode at least comprises a first contact region located on the first semiconductor layer and a second contact region located on the second semiconductor layer (please see fig. 6 above which shows this configuration between recited elements);
the first contact region and the second contact region on the oxide semiconductor layer comprise a shape provided in the following:
the shape comprises a first angle (fig. 6: α1) between the lower surface of the metal oxide semiconductor layer and the lateral surface of the first contact region, and a second angle (fig. 6: α2) between the lower surface of the metal oxide semiconductor layer and the lateral surface of the second contact region, and the first angle is larger than the second angle (par. 101).
Regarding claim 2, Lin teaches a metal oxide thin film transistor according to claim 1, wherein the first angle is an included angle between the first contact region and a flat surface parallel to the lower surface and intersecting with the first contact region; and the second angle is an included angle between the second contact region and a flat surface parallel to the lower surface and intersecting with the second contact region (please see fig. 6 above which shows this configuration between recited elements).
Regarding claim 3, Lin teaches a metal oxide thin film transistor according to claim 1, wherein the second semiconductor layer is close to the source electrode and the drain electrode in the stacked structure of the metal oxide semiconductor layer; the first contact region is all or part of a contact region between the source electrode or the drain electrode and the first semiconductor layer, and the second contact region is all or part of a contact region between the source electrode or the drain electrode and the second semiconductor layer (please see fig. 6 above which shows this configuration between recited elements).
Regarding claim 4, Lin teaches a metal oxide thin film transistor according to claim 1, wherein the first semiconductor layer and the second semiconductor layer satisfy at least one of the following conditions: the first semiconductor layer and the second semiconductor layer comprise metal oxide semiconductors with different crystallinity; the first semiconductor layer and the second semiconductor layer comprise metal oxide semiconductors with different compositions; the first semiconductor layer and the second semiconductor layer comprise metal oxide semiconductors with different band gaps (par. 110, 119, 120, 175, 176, 178-180).
Regarding claim 5, Lin teaches a metal oxide thin film transistor according to claim 3, wherein a crystallinity of the metal oxide of the first semiconductor layer is smaller than a crystallinity of the metal oxide of the second semiconductor layer (par. 110).
Regarding claim 6, Lin teaches a metal oxide thin film transistor according to claim 1 , wherein in a direction perpendicular to a main surface of the base substrate, an extension distance of the first contact region from a position closest to the upper surface to a position closest to the lower surface is smaller than an extension distance of the second contact region from a position closest to the upper surface to a position closest to the lower surface.
Regarding claim 10, Lin teaches a metal oxide thin film transistor according to claim 1, wherein the metal oxide semiconductor layer further comprises a third semiconductor layer; the third semiconductor layer is located between the first semiconductor layer and the second semiconductor layer and is in direct contact with the first semiconductor layer and the second semiconductor layer (par. 112).
Regarding claim 13, Lin teaches a metal oxide thin film transistor according to claim 1, wherein the metal oxide semiconductor layer comprises an overlapping region that at least partially overlaps with a projection of the source electrode or the drain electrode on the base substrate, and a non-overlapping region that does not overlap with the projection of the source electrode or the drain electrode on the base substrate; a content percentage of oxygen (O) element of the overlapping region is smaller than a content percentage of oxygen element of the non-overlapping region (par. 122, 123, 127, 128, 133 and 136).
Regarding claim 22, Lin teaches a metal oxide thin film transistor according to claim 1, wherein the first contact region is a first concave surface, and at least a part of the first concave surface is located in the first semiconductor layer (please see fig. 6 above which shows this configuration between recited elements).
Regarding claim 23, Lin teaches a metal oxide thin film transistor according to claim 22, wherein in a direction of the first concave surface away from the lower surface, the first angle first increases and then decreases, and a distance between the first concave surface and a center of the metal oxide semiconductor layer first decreases and then increases (please see fig. 6 above which shows this configuration between recited elements).
Regarding claim 27, Lin teaches a metal oxide thin film transistor according to claim 1, wherein a contour of the metal oxide semiconductor layer comprises four edges, and the four edges correspond to a first lateral surface, a second lateral surface, a third lateral surface and a fourth lateral surface respectively, and the first lateral surface and the second lateral surface are oppositely arranged, the third lateral surface and the fourth lateral surface are oppositely arranged; the first lateral surface, the third lateral surface, the second lateral surface and the fourth lateral surface are sequentially arranged; the first contact region is a region where the source electrode is in contact with at least one of the second lateral surface and the third lateral surface (please see fig. 6 above which shows this configuration between recited elements).
Regarding claim 36, Lin teaches a metal oxide thin film transistor according to claim 3, wherein the first semiconductor layer comprises an amorphous or nano-crystalline metal oxide semiconductor; and the second semiconductor layer comprises a c- axis crystallized metal oxide semiconductor (par. 119, 120, 179 and 180).
Regarding claim 43, Lin teaches a display panel, comprising the metal oxide thin film transistor according to claim 1 (par. 206).
Allowable Subject Matter
Claim 7 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 11 (please noted dependency) is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 25 (please noted dependency) is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 26 is objected to due to its dependency on claim 25.
Claim 28 (please noted dependency) is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 34 is objected to due to its dependency on claim 28.
Claim 35 is objected to due to its dependency on claim 28.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CALEB E HENRY whose telephone number is (571)270-5370. The examiner can normally be reached Mon-Fri.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eva Montalvo can be reached at (571) 270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/CALEB E HENRY/Primary Examiner, Art Unit 2818
Prosecution Insights