DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-4 and 6-11 is/are rejected under 35 U.S.C. 103 as being unpatentable over TSUZUKI (US 20090283798) in view of KOWALIK-SEIDL (US 20190148484).
Regarding claim 1, TSUZUKI discloses a semiconductor device, comprising:
a semiconductor substrate (the semiconductor layer comprising 1-4 and 6, see fig 1, para 89-90 and 99);
p-type body regions (fig 1, 2a, para 81) disposed in the semiconductor substrate, wherein each of the p-type body regions is in direct contact with a source metal layer (the p regions 2a are in direct contact with metal layer 12a and 10, see fig 1, para 84), and the source metal layer is made only of metal (12a and 10 can be metal, see fig 1, para 7 and 84); and
wherein the semiconductor substrate comprises at least one first region (the left region of the device in fig 1), and a region of the semiconductor substrate outside the at least one first region is a second region (the right region of the device in fig 1);
each p-type body region of p-type body regions in the at least one first region is provided with a first p-type body region contact region (the p+ body contact regions 4a, see fig 1, para 92), and the source metal layer is in direct contact with the first p-type body region contact region to form an ohmic contact (4a is in direct contact with 12a to make ohmic contact, see fig 1, para 92);
each of p-type body regions in the second region forms no ohmic contact with the source metal layer (2a forms a Schottky contact with 10, not an ohmic contact, see fig 1, para 96), wherein each of p-type body regions in the second region is integrally formed (each bod region 2a between each trench T1 is a continuous, integral shape, see fig 1); and
each p-type body region of the p-type body regions comprises n-type source regions (source regions 3a, see fig 1, para 81), wherein the n-type source regions are in direct contact with the source metal layer (3a is in direct contact with 12a, see fig 1), and the n-type source regions in each p-type body region of p-type body regions in the at least one first region are in direct contact with the first p-type body region contact region (3a and 4a are in direct contact, see fig 1).
TSUZUKI fails to explicitly disclose a device comprising p-type columns disposed in the semiconductor substrate, wherein each of the p-type columns is below a respective one of the p-type body regions.
KOWALIK-SEIDL teaches a device comprising p-type columns (fig 1, 133, para 34) disposed in the semiconductor substrate, wherein each of the p-type columns is below a respective one of the p-type body regions (each column 133 is below a body 132, see fig 1, para 30).
TSUZUKI and KOWALIK-SEIDL are analogous art because they both are directed towards vertical semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of TSUZUKI with the p-type columns of KOWALIK-SEIDL because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of TSUZUKI with the p-type columns of KOWALIK-SEIDL in order to lower the on resistance of the device (see KOWALIK-SEIDL para 34).
Regarding claim 2, TSUZUKI and KOWALIK-SEIDL disclose the semiconductor device according to claim 1.
The first embodiment of TSUZUKI fails to explicitly disclose a device. wherein a shape of the at least one first region comprises at least one of a polygon, a circle, or an ellipse.
A second embodiment of TSUZUKI teaches a device. wherein a shape of the at least one first region comprises at least one of a polygon (the portions comprising 2a can be hexagonally shaped, see fig 7A, para 120), a circle, or an ellipse.
The two embodiments of TSUZUKI are analogous art because they both are directed towards vertical semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the first embodiment of TSUZUKI with the shape of the second embodiment of TSUZUKI because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the first embodiment of TSUZUKI with the shape of the second embodiment of TSUZUKI in order to improve the recovery property of the diode cell (see TSUZUKI para 19).
Regarding claim 3, TSUZUKI and KOWALIK-SEIDL disclose the semiconductor device according to claim 1.
TSUZUKI further discloses a device, wherein a p-type body region of the p-type body regions in the second region is provided with a second p-type body region contact region (body regions 2a of the second region contain region 2al which is a part of the body in contact with the source metal 12a, see fig 1, para 94), and
a doping concentration of the second p-type body region contact region is lower than a doping concentration of the first p-type body region contact region (the doping concentration of 2al directly below T2 can be 1E17 per cc, which is lower than the doping concentration of 4a which can be 1E19 per cc, see para 92 and 138).
Regarding claim 4, TSUZUKI and KOWALIK-SEIDL disclose the semiconductor device according to claim 3.
TSUZUKI further discloses a device, wherein the source metal layer is in contact with the second p-type body region contact region but no ohmic contact is formed between the source metal layer and the second p-type body region contact region (12a is in direct contact with 2al, but they form a Schottky contact and not an ohmic contact, see fig 1, para 130).
Regarding claim 6, TSUZUKI and KOWALIK-SEIDL disclose the semiconductor device according to claim 1.
TSUZUKI fails to explicitly disclose a device, wherein each of the p-type columns is in contact with the respective one of the p-type body regions.
KOWALIK-SEIDL teaches a device, wherein each of the p-type columns is in contact with the respective one of the p-type body regions (each column 133 is below and in direct contact with a body 132, see fig 1, para 30).
TSUZUKI and KOWALIK-SEIDL are analogous art because they both are directed towards vertical semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of TSUZUKI with the p-type columns of KOWALIK-SEIDL because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of TSUZUKI with the p-type columns of KOWALIK-SEIDL in order to lower the on resistance of the device (see KOWALIK-SEIDL para 34).
Regarding claim 7, TSUZUKI and KOWALIK-SEIDL disclose the semiconductor device according to claim 1.
TSUZUKI further discloses a device, wherein the semiconductor substrate comprises an n-type drain region (n+ region 6, see fig 1, para 5) and an n-type drift region (fig 1, 1, para 5) disposed above the n-type drain region, and each of the p-type body regions forms a PN junction structure with the n-type drift region (the p-type regions 2a form a pn junction with n-type region 1, see fig 1).
Regarding claim 8, TSUZUKI and KOWALIK-SEIDL disclose the semiconductor device according to claim 1.
TSUZUKI further discloses a device. further comprising gate structures (gates 7a and 8a, see fig 1, para 83). each of the gate structures comprises a gate dielectric layer (fig 1, 7a, para 83) and a gate (fig 1, 8a, para 81).
Regarding claim 9, TSUZUKI and KOWALIK-SEIDL disclose the semiconductor device according to claim 8.
TSUZUKI further discloses a device, wherein the gate structures are planar gate structures or trench gate structures (7a and 8a form a trench gate structure in T1, see fig 1, para 81-82).
Regarding claim 10, TSUZUKI and KOWALIK-SEIDL disclose the semiconductor device according to claim 8.
TSUZUKI further discloses a device, wherein each of the gate structures is isolated from the source metal layer via an interlayer insulating layer (8 is isolated from 10 by insulator 9, see fig 1, para 84).
Regarding claim 11, TSUZUKI and KOWALIK-SEIDL disclose the semiconductor device according to claim 1.
TSUZUKI further discloses a device, wherein the semiconductor substrate comprises an n-type drain region (fig 1, 6, para 5) and an n-type drift region (fig 1, 1, para 5) disposed above the n-type drain region.
TSUZUKI fails to explicitly disclose a device wherein each of the p-type columns forms a PN junction structure with the n-type drift region. and a charge balance between a p-type column of the p-type columns and a adjacent n-type drift region is formed.
KOWALIK-SEIDL teaches a device wherein each of the p-type columns forms a PN junction structure with the n-type drift region (the column 133 forms a pn junction with the drift region 134, see fig 1, para 31). and a charge balance between a p-type column of the p-type columns and a adjacent n-type drift region is formed (133 is a charge compensation p-type region that can balance the charge of 134, see fig 1, para 32).
TSUZUKI and KOWALIK-SEIDL are analogous art because they both are directed towards vertical semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of TSUZUKI with the p-type columns of KOWALIK-SEIDL because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of TSUZUKI with the p-type columns of KOWALIK-SEIDL in order to lower the on resistance of the device (see KOWALIK-SEIDL para 34).
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over TSUZUKI (US 20090283798) in view of KOWALIK-SEIDL (US 20190148484) and further in view of YILMAZ (US 20130200451).
Regarding claim 12, TSUZUKI and KOWALIK-SEIDL disclose the semiconductor device according to claim 1.
TSUZUKI and KOWALIK-SEIDL fails to explicitly disclose a device, wherein the p-type columns are configured to float.
YILMAZ teaches a device wherein the p-type columns are configured to float (212 can be floating, see fig 4N, para 54).
TSUZUKI, KOWALIK-SEIDL and YILMAZ are analogous art because they both are directed towards semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of TSUZUKI and KOWALIK-SEIDL with the floating columns of YILMAZ because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of TSUZUKI and KOWALIK-SEIDL with the floating columns of YILMAZ in order to improve the blocking capacity of the device (see YILMAZ para 34).
Response to Arguments
Applicant’s arguments with respect to claim(s) 1 have been considered but are moot because the new ground of rejection does not rely on the combination of references applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JONAS TYLER BEARDSLEY whose telephone number is (571)272-3227. The examiner can normally be reached 930-600 M-F.
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/JONAS T BEARDSLEY/Examiner, Art Unit 2811
/SAMUEL A GEBREMARIAM/Primary Examiner, Art Unit 2811