DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Claims
This is a final office action in response to the applicant’s arguments and remarks filed on 05/13/2026. Claims 1-13 are pending in the current office action. Claim 1 has been amended by the applicant.
Status of the Rejection
All 35 U.S.C. § 102 and 103 rejections from the previous office action are substantially maintained and modified only in response to the amendments to the claims.
Claim Rejections - 35 USC § 102
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1, 6, 11, and 12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chou et al. (US-20150069619-A1).
Regarding Claim 1, Chou teaches a method for fabricating a semiconductor device (Paragraph [0009] method for forming a semiconductor device), comprising the steps of:
providing a pre-processed device comprising a dielectric layer, a metal layer embedded in the dielectric layer and a first substrate covering the dielectric layer, wherein the dielectric layer comprises a first dielectric layer, an etch stop layer and a second dielectric layer that are sequentially deposited, wherein the metal layer is embedded in the first dielectric layer, and wherein the etch stop layer is located over the metal layer (Paragraphs [0010-0017] Figure 1 device comprises first substrate (element 102) which is covering a dielectric layer that comprises first inter-metal dielectric layer (element 110), that can be considered the claimed "first dielectric layer" and has metal layers (elements 112a-112d), embedded in it, where elements 112a shown in Figure 1 can be considered the metal layer as claimed, a first inter-layer dielectric layer (element 106) that can be considered the claimed "second dielectric layer" and an etch stop layer that can be positioned between the first inter-metal dielectric layer and the first inter-layer dielectric layer);
forming, on the first substrate, a mask layer from which a portion of the first substrate is exposed (Paragraphs [0024-0027] Figures 2 and 3 a mask layer is formed that can be considered to comprise patterned mask (element 302), anti-reflection coating layer (element 304) and hard mask layer (element 306). These layers are patterned to expose a portion of the first substrate in order to etch that substrate to form an opening (element 310));
exposing the second dielectric layer by etching the first substrate through a first etching process with the mask layer serving as a mask (Paragraph [0027-0029] Figure 3 the first substrate can be etched with one etch process, and the inter-layer dielectric (element 106) can be etched with a different process such that the first etch process would expose the claimed "second dielectric layer". The etch processes use the hard mask layer (element 306));
forming an opening by etching the exposed second dielectric layer through a second etching process with the mask layer serving as a mask, wherein the second etching process stops at the etch stop layer (Paragraphs [0027-0030] Figure 3 the inter-layer dielectric (element 106) can be etched with one etch process, in an embodiment where there is an etch stop layer such that multiple etching processes, one for each type of material used by each successive layer, are utilized to provide sufficient etch selectivity);
forming an isolation layer covering at least a sidewall of the opening, wherein a portion of the first dielectric layer is located between the metal layer and a portion of the isolation layer that covers a bottom of the opening (Paragraph [0034] Figure 4 a dielectric isolation layer (element 412) is formed such that it covers the first opening (element 310). As seen in Figure 4, this results in some portion of first inter-metal dielectric layer (element 110), equivalent to the claimed "first dielectric layer", being between the metal layer (element 112a) and the isolation layer (element 412)); and
exposing the metal layer by etching away the first dielectric layer under the opening (Paragraph [0036] Figure 5 an additional etching process removes some of the first inter-metal dielectric layer (element 110) to expose the metal layer (element 112a)),
wherein a portion of the metal layer that is under the bottom of the opening and is located between the sidewalls of the opening is continuous (Figure 5 element 112a, which can be considered the metal layer as claimed is continuous. Further, in a different embodiment than the embodiment shown in the Figures, which have been used as reference for clarity above, Paragraph [0047] outlines an embodiment where the process forms a structure where the conductive plug formed is connected to only one metal line in the first semiconductor chip and only one metal line in the second semiconductor chip. In this embodiment, there would only be one metal interconnect line underneath the opening formed such that it could be connected to the conductive plug that would be formed within the opening, and therefore the instant limitation would be met).
Regarding Claim 6, Chou teaches wherein the isolation layer comprises a silicon oxide layer and/or a silicon nitride layer (Paragraph [0035] dielectric isolation layer (412) can be silicon nitride or silicon dioxide).
Regarding Claim 11, Chou teaches wherein each of the first dielectric layer and the second dielectric layer is an oxide layer (Paragraph [0014] first inter-layer dielectric can comprise glass, which comprise a silicon oxide. Paragraph [0016] first inter-metal dielectric can comprise glass, which comprise a silicon oxide).
Regarding Claim 12, Chou teaches wherein the pre-processed device further comprises a second substrate on which the dielectric layer is formed, wherein a wafer comprising the second substrate is a carrier wafer or a device wafer, with a wafer comprising the first substrate being a device wafer (Paragraph [0010] Figure 1 the device comprises a second wafer (element 200) that is a device wafer).
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Chou, as applied to claim 1 above, and further in view of Bookbinder et al. (WO-2020112710-A1).
In regards to Claim 2, modified Chou fails to teach that wherein the first substrate has a thickness greater than 50 µm.
Bookbinder teaches methods related to interconnects and vias (Paragraphs [0003-0005]). Bookbinder teaches that a substrate can have a thickness in the range of 10-2000µm (Paragraph [0117]) and that individual substrate layers within can have a thickness in the range of 0.1-1500µm (Paragraph [0118]).
It would have been obvious to one of ordinary skill in the art to have modified the method of Chou by selecting as the thickness of the first substrate a thickness of a substrate layer as taught by Bookbinder.
This modification would have been obvious as it would have been the combination of a known prior art elements according to known methods to yield predictable results. This combination would have had the predictable result of providing a suitable thickness for a substrate layer. See MPEP 2143(I)(A).
It would have been obvious to one of ordinary skill in the art to have selected and incorporated a substrate thickness at a level within the disclosed range of 0.1-1500µm, including at amounts that overlap with the claimed range of greater than 50 µm. It has been held that obviousness exists where the claimed ranges overlap or lie inside ranges disclosed by the prior art. See MPEP 2144.05 (I).
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Chou as applied to claim 1 above, and further in view of Favre et al. (US-20120259449-A1).
In regards to Claim 3, Chou fails to teach wherein a time interval between the first etching process and the second etching process is from 2 h to 12 h.
Favre teaches methods related to semiconductor manufacturing (Paragraph [0001]). Favre teaches that between manufacturing steps there can be wait times as long as several hours as the product being manufactured is moved between equipment (Paragraph [0003]).
It would have been obvious to one of ordinary skill in the art to have modified the method of Chou by including a time interval between the first and second etching process as taught by Favre.
This modification would have been obvious because as taught by Favre, the limitations of a manufacturing schedule and the use of different equipment in the processing of a single object can result in a time interval between different processing steps.
It would have been obvious to one of ordinary skill in the art to have selected and incorporated a time interval between the first and second etching steps at a level within the disclosed range of up to several hours, including at amounts that overlap with the claimed range of 2-12 hours. It has been held that obviousness exists where the claimed ranges overlap or lie inside ranges disclosed by the prior art. See MPEP 2144.05 (I).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Chou as applied to claim 1 above, and further in view of Afzal et al. (WO-2019209433-A1).
Regarding Claim 4, Chou fails to teach wherein the mask layer has a thickness of 10 µm to 20 µm.
Afzal teaches a method of depositing a mask ([Abstract]). Afzal teaches that a deposited mask can have a thickness of 2-20µm (Paragraph [0015]).
It would have been obvious to one of ordinary skill in the art to have modified the method of Chou by depositing a mask with a thickness within the range taught by Afzal.
This modification would have been obvious as it would have been the combination of a known prior art elements according to known methods to yield predictable results. This combination would have had the predictable result of providing a suitable thickness for a mask layer. See MPEP 2143(I)(A).
It would have been obvious to one of ordinary skill in the art to have selected and incorporated a mask thickness at a level within the disclosed range of 2-20µm, including at amounts that overlap with the claimed range of 10-20 µm. It has been held that obviousness exists where the claimed ranges overlap or lie inside ranges disclosed by the prior art. See MPEP 2144.05 (I).
Claims 5 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Chou as applied to claim 1 above, and further in view of over Chen et al. (CN-106057786-A, machine translation).
Regarding Claim 5, Chou teaches all the limitations of claim 1 as outlined above.
Chou fails to teach wherein the isolation layer has a thickness of 2000 A to 3500 A.
Chen teaches a method for fabricating a semiconductor device (Paragraph [0004] method of forming a semiconductor package). Chen teaches methods that include etching dielectric layers to expose a metal layer (Paragraphs [0051-0055] dielectric layers are etched to expose a metal layer). Chen teaches that between etching steps, prior to exposing the metal layer, an isolation layer is formed in the opened created by the etching steps (Paragraph [0055] an isolation layer is formed). Chen teaches that the isolation layer has a thickness between 500 and 5000 Å (Paragraph [0056]).
It would have been obvious to one of ordinary skill in the art to have modified the method of Chou by selecting as the thickness of the isolation layer, the range for the thickness of the isolation layer taught by Chen.
This modification would have been obvious as it can be considered the combination of prior art elements according to known methods to yield predictable results. This combination would have had the predictable result of supplying a suitable range of thickness for the isolation layer in the method. See MPEP 2143(I)(A).
It would have been obvious to one of ordinary skill in the art to have selected and incorporated an isolation layer thickness at a level within the disclosed range of 500-5000Å, including at amounts that overlap with the claimed range of 2000-3500Å. It has been held that obviousness exists where the claimed ranges overlap or lie inside ranges disclosed by the prior art. See MPEP 2144.05 (I).
Regarding Claim 13, Chou teaches all the limitations of claim 1 as outlined above.
Chou fails to teach wherein the pre-processed device further comprises a second substrate on which the dielectric layer is formed, and wherein the second substrate is a stack of several wafers.
Chen teaches a method for fabricating a semiconductor device (Paragraph [0004] method of forming a semiconductor package). Chen teaches methods that include etching dielectric layers to expose a metal layer (Paragraphs [0051-0055] dielectric layers are etched to expose a metal layer). Chen teaches that between etching steps, prior to exposing the metal layer, an isolation layer is formed in the opened created by the etching steps (Paragraph [0055] an isolation layer is formed). Chen teaches that the methods taught are related to the field of 3D integrated circuits, where two or more semiconductor wafers are bonded together and processed (Paragraphs [0007-0008]). Chen further teaches embodiments that comprise a first, second, and third substrate (Paragraphs [0092-0093] Figures 31 and 32 embodiment is taught that includes first substrate (element 3004), second substrate (element 3010), and third substrate (element 3204)).
It would have been obvious to one of ordinary skill in the art to have modified the method of Chou such that the method outlined was conducted on a package that comprised three substrates as taught by Chen. In such a modification the claimed “second substrate” would comprise the taught “first substrate” and “second substrate”, thereby meeting the instant limitation. The taught “third substrate” could be considered equivalent to the claimed “first substrate” and could treated as outlined above in the rejections of claim 1 to meet the limitations of those claims.
This modification would have been obvious as it would have been the combination of a known prior art elements according to known methods to yield predictable results. This combination would have had the predictable result of providing a method for forming a device that includes multiple substrates/wafers while allowing the method of Chou to be conducted on the first substrate. See MPEP 2143(I)(A).
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Chou as applied to claim 1 above, and further in view of Ma et al. (US-20160111351-A1).
Regarding Claim 7, Chou teaches that the isolation layer may comprise a combination of silicon oxide and silicon nitride layers (Paragraph [0035]), but Chou fails to teach wherein the isolation layer comprises a first silicon oxide layer, a silicon nitride layer and a second silicon oxide layer that are sequentially deposited over the sidewall of the opening.
Ma teaches methods for manufacturing semiconductor devices (Paragraph [0003]). Ma teaches methods related to forming vias to reduce leakage improve reliability of semiconductor devices (Paragraph [0018]). Ma teaches forming an isolation layer (element 505) on the sidewalls of a through hole (Paragraph [0052]). Ma teaches that the isolation layer may be an ONO multilayer structure, therefore a multilayer structure that is successive layers of silicon oxide, silicon nitride, and silicon oxide (Paragraph [0053]).
It would have been obvious to one of ordinary skill in the art to have modified the method of Chou by using as the isolation layer a three-layer structure that comprised successive layers there were silicon oxide, silicon nitride, and silicon oxide.
This modification would have been the simple substitution of one form of an isolation layer with another. The simple substitution of one known element for another is likely to be obvious when predictable results are achieved. See MPEP §2143(B). Furthermore, the selection of a known material, which is based upon its suitability for the intended use, is within the ambit of one of ordinary skill in the art. See MPEP § 2144.07.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Chou as applied to claim 1 above, and further in view of Huang et al. (US20190371898-A1) and Demmin et al. (US-6635185-B2).
Regarding Claim 8, Chou teaches that the substrate can be etched with a plasma process that utilizes SF6 (Paragraph [0029]), but does not provide process parameters and therefore Chou fails to teach wherein the first etching process is accomplished by a plasma dry etching process using a reactant gas comprising SF6 and C4F8, performed for a time duration of 800 s to 1000 s at a chamber pressure of 10 mTorr to 14 mTorr, a power level of 1000 W to 3000 W from an RF power supply and a bias voltage of 100 V to 900 V.
Huang teaches methods of forming recesses using etching processes ([Abstract]). Huang teaches that the etching process may etch through a layer comprising silicon oxide (Paragraph [0038] etch process can etch through second ILD (element 230). Paragraph [0032] second ILD (element 230) can be silicon dioxide). Huang teaches that the etch process can include a RF power of 100-2000W, a pressure of 3-20 mTorr, a bias voltage of 20-1500 V, have duration of 155-1800 seconds, and utilize an etch gas that include SF6 and C4F8 (Paragraphs [0040-0041]).
Demmin teaches that plasma etching process conditions, including the etching composition, wafer temperature, pressure, power, time and bias can be optimized in order to etch a material satisfactorily (Column 7 line 15-25).
It would have been obvious to one of ordinary skill in the art to have modified the method of Chou by using, for the first etching process, the process parameters taught by Huang for a plasma etching.
One of ordinary skill in the art would have been motivated to make this modification because Demmin teaches that this process parameters are a result-effective variable which can be optimized for the needs of a particular process. See MPEP 2144.05 IIB. Additionally, this modification would have been obvious as it could be considered the combination of prior art elements according to known methods to yield predictable results. This combination would have had the predictable result of setting suitable processing conditions for the etching process. See MPEP 2143(I)(A).
It would have been obvious to one of ordinary skill in the art to have selected and incorporated an etching duration at a level within the disclosed range of 155-1800 seconds, including at amounts that overlap with the claimed range of 800-1000 seconds. It would have been obvious to one of ordinary skill in the art to have selected and incorporated a chamber pressure at a level within the disclosed range of 3-20 mTorr, including at amounts that overlap with the claimed range of 10-14 mTorr. It would have been obvious to one of ordinary skill in the art to have selected and incorporated a power level at a level within the disclosed range of 100-2000W, including at amounts that overlap with the claimed range of 1000-3000W. It would have been obvious to one of ordinary skill in the art to have selected and incorporated bias voltage at a level within the disclosed range of 20-1500 V, including at amounts that overlap with the claimed range of 100-900 V. It has been held that obviousness exists where the claimed ranges overlap or lie inside ranges disclosed by the prior art. See MPEP 2144.05 (I).
Claims 9-10 is rejected under 35 U.S.C. 103 as being unpatentable over Chou as applied to claim 1 above, and further in view of Huang et al. (US20190371898-A1), Kuo et al. (US-20190097056-A1), and Demmin et al. (US-6635185-B2).
Regarding Claim 9, Chou teaches that the second dielectric layer can be etched with a plasma process (Paragraph [0029]) but Chou fails to teach wherein the second etching process is accomplished by a plasma dry etching process performed with process parameters including a chamber pressure of 10 mTorr to 14 mTorr, a CF4 flow rate of 40 sccm to 60 sccm, a CHF3 flow rate of 60 sccm to 80 sccm, a power level of 800 W to 1000 W from an RF power supply, a bias voltage of 170 V to 190 V and a time duration of 800 s to 1000 s.
Huang teaches methods of forming recesses using etching processes ([Abstract]). Huang teaches that the etching process may etch through a layer comprising silicon oxide (Paragraph [0038] etch process can etch through second ILD (element 230). Paragraph [0032] second ILD (element 230) can be silicon dioxide). Huang teaches that the etch process can include a bias voltage of 20-1500 V and have duration of 155-1800 seconds.
Kuo teaches a plasma etching method that can be used to etch an oxide material (Paragraphs [0030-0032] a plasma bombardment is performed to selectively etch insulating layer (element 120). Paragraph [0015] insulating layer (element 120) is made from first and second oxide layers). Kuo teaches that the etching method utilizes CF4 and CHF3, where CHF3 has a flow rate from 50-200 sccm (Paragraph [0033]).
Demmin teaches that plasma etching process conditions, including the etching composition, wafer temperature, pressure, power, time and bias can be optimized in order to etch a material satisfactorily (Column 7 line 15-25).
It would have been obvious to one of ordinary skill in the art to have modified the method of Chou by using, for the second etch process, the process parameters taught by Huang and Kuo for a plasma etching.
One of ordinary skill in the art would have been motivated to make this modification because Demmin teaches that this process parameters are a result-effective variable which can be optimized for the needs of a particular process. See MPEP 2144.05 IIB. Additionally, this modification would have been obvious as it could be considered the combination of prior art elements according to known methods to yield predictable results. This combination would have had the predictable result of setting suitable processing conditions for the etching process. See MPEP 2143(I)(A).
It would have been obvious to one of ordinary skill in the art to have selected and incorporated an etching duration at a level within the disclosed range of 155-1800 seconds, including at amounts that overlap with the claimed range of 800-1000 seconds. It would have been obvious to one of ordinary skill in the art to have selected and incorporated a chamber pressure at a level within the disclosed range of 10-100 mTorr, including at amounts that overlap with the claimed range of 10-14 mTorr. It would have been obvious to one of ordinary skill in the art to have selected and incorporated a power level at a level within the disclosed range of 0-2000W, including at amounts that overlap with the claimed range of 800-1000W. It would have been obvious to one of ordinary skill in the art to have selected and incorporated bias voltage at a level within the disclosed range of 20-1500 V, including at amounts that overlap with the claimed range of 170-190 V. It would have been obvious to one of ordinary skill in the art to have selected and incorporated flow rate of CF4 at a level within the disclosed range of 20-150 sccm, including at amounts that overlap with the claimed range of 40-60 sccm. It would have been obvious to one of ordinary skill in the art to have selected and incorporated flow rate of CHF3 at a level within the disclosed range of 50-200 sccm, including at amounts that overlap with the claimed range of 60-80 sccm. It has been held that obviousness exists where the claimed ranges overlap or lie inside ranges disclosed by the prior art. See MPEP 2144.05 (I).
Regarding Claim 10, Chou teaches that etching the first dielectric layer can be conducted with a plasma etching process (Paragraph [0029]) but fails to teach wherein the step of exposing the metal layer by etching away the first dielectric layer under the opening is accomplished by a plasma dry etching process performed with process parameters including a chamber pressure of 10 mTorr to 14 mTorr, a CF4 flow rate of 40sccm to 60 sccm, a CHF3 flow rate of 60 sccm to 80 sccm, a power level of 500 W to 1000 W from an RF power supply, a bias voltage of 170 V to 190 V and a time duration of 400 s to 700 s.
Huang teaches methods of forming recesses using etching processes ([Abstract]). Huang teaches that the etching process may etch through a layer comprising silicon oxide (Paragraph [0038] etch process can etch through second ILD (element 230). Paragraph [0032] second ILD (element 230) can be silicon dioxide). Huang teaches that the etch process can include a RF power of 100-2000W, a pressure of 3-20 mTorr, a bias voltage of 20-1500 V, have duration of 155-1800 seconds, and utilize an etch gas that includes CF4 and CHF3 (Paragraphs [0040-0041], claims 19).
Kuo teaches a plasma etching method that can be used to etch an oxide material (Paragraphs [0030-0032] a plasma bombardment is performed to selectively etch insulating layer (element 120). Paragraph [0015] insulating layer (element 120) is made from first and second oxide layers). Kuo teaches that the etching method utilizes CF4 with a flow rate from 50-200 sccm and CF4 with a flow rate of 50-200 sccm (Paragraph [0033]).
Demmin teaches that plasma etching process conditions, including the etching composition, wafer temperature, pressure, power, time and bias can be optimized in order to etch a material satisfactorily (Column 7 line 15-25).
It would have been obvious to one of ordinary skill in the art to have modified the method of Chou by using, for the process of etching the first dielectric layer to expose the metal layer, the process parameters taught by Huang and Kuo for a plasma etching.
One of ordinary skill in the art would have been motivated to make this modification because Demmin teaches that this process parameters are a result-effective variable which can be optimized for the needs of a particular process. See MPEP 2144.05 IIB. Additionally, this modification would have been obvious as it could be considered the combination of prior art elements according to known methods to yield predictable results. This combination would have had the predictable result of setting suitable processing conditions for the etching process. See MPEP 2143(I)(A).
It would have been obvious to one of ordinary skill in the art to have selected and incorporated an etching duration at a level within the disclosed range of 155-1800 seconds, including at amounts that overlap with the claimed range of 400-700 seconds. It would have been obvious to one of ordinary skill in the art to have selected and incorporated a chamber pressure at a level within the disclosed range of 3-20 mTorr, including at amounts that overlap with the claimed range of 10-14 mTorr. It would have been obvious to one of ordinary skill in the art to have selected and incorporated a power level at a level within the disclosed range of 100-2000W, including at amounts that overlap with the claimed range of 500-1000W. It would have been obvious to one of ordinary skill in the art to have selected and incorporated bias voltage at a level within the disclosed range of 20-1500 V, including at amounts that overlap with the claimed range of 170-190 V. It would have been obvious to one of ordinary skill in the art to have selected and incorporated flow rate of CF4 at a level within the disclosed range of 50-200 sccm, including at amounts that overlap with the claimed range of 40-60 sccm. It would have been obvious to one of ordinary skill in the art to have selected and incorporated flow rate of CHF3 at a level within the disclosed range of 50-200 sccm, including at amounts that overlap with the claimed range of 60-80 sccm. It has been held that obviousness exists where the claimed ranges overlap or lie inside ranges disclosed by the prior art. See MPEP 2144.05 (I).
Response to Arguments
Applicant’s arguments, see Remarks Pg. 1-4, filed 05/13/2026, with respect to the 35 U.S.C. § 103 rejection have been fully considered and are not persuasive.
Applicant argues that Chou fails to teach that the metal layer under the opening is continuous.
Examiner respectfully disagrees. As outlined in the rejection of claim 1 above, examiner takes the position that under the broadest reasonable interpretation of the claimed limitation, one could consider the interconnect line labeled 112a in the Figures as being the claimed “metal layer”, while the other interconnect lines (elements 112b-112d) could be considered “other metal layers”. In such an interpretation the metal layer represented by 112a is continuous and meets the claimed limitations. Further, examiner notes that the embodiment of the teachings of Chou represented in the Figures is not the only embodiment taught. Chou teaches an alternative embodiment where there is only one interconnect line within the structure that is under opening and embedded in the dielectric layer. In such an embodiment, the only possible interpretation would be that the metal layer under the opening and between the sidewalls is continuous, thereby meeting the claimed limitations.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANDREW KEELAN LAOBAK whose telephone number is (703)756-5447. The examiner can normally be reached Monday - Friday 8:00am - 5:30pm.
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/A.K.L./ Examiner, Art Unit 1713 /DUY VU N DEO/Primary Examiner, Art Unit 1713
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