Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 11/28/2025 has been entered.
Response to Arguments
Applicant's arguments filed on 11/28/2025 have been fully considered but they are not persuasive.
The Applicant argues that in regard to claims 24 and 36 that applied prior art, CUI reference was filed on May 6, 2020, and published on August 4, 2020, and the present application claims priority to CN applications filed on August 14, 2020. Accordingly, CUI falls within the exception of 35 U.S.C. § 102(b)(2)(A) and is excluded as prior art under 35 U.S.C. § 102(a)(2).
In response to this argument, the Examiner directs the applicant’s attention to the CUI prior art publication date, which is August 4, 2020, which is available to the public before the effective filing date of the claimed invention. Hence, the CUI prior art is applicable as prior art under 35 U.S.C. 102(a)(1) that cannot be excepted under 35 U.S.C. 102(b)(2)(C). In addition, the applied prior art has different inventors than the present application. Hence, it will not be overcome by 35 U.S.C. § 102(a)(2) exception.
Applicant may rely on the exception under 35 U.S.C. 102(b)(1)(A) to overcome this rejection under 35 U.S.C. 102(a)(1) by a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application, and is therefore not prior art under 35 U.S.C. 102(a)(1). Alternatively, applicant may rely on the exception under 35 U.S.C. 102(b)(1)(B) by providing evidence of a prior public disclosure via an affidavit or declaration under 37 CFR 1.130(b).
Therefore, the CUI prior art reference does meet all the limitation in claims 24 and 36.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 24- 34 and 36- 43 are rejected under 35 U.S.C. 103 as being unpatentable over CUI et al. (CN 111490060 A, hereinafter refer to CUI).
Regarding Claim 24: CUI discloses micro spectrum chip based on units of different shapes (see CUI, Figs.3-5 as shown below and abstract), comprising
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a CMOS image sensor (CIS) wafer (120) and an optical modulation layer (110) (see CUI, Figs.3- 5 as shown above);
wherein the optical modulation layer (110) comprises one or more micro-nano structure (112/113/114/115) units provided on a surface of a photosensitive area of the CIS wafer (120), each of the one or more micro-nano structure units (112/113/114/115) comprises one or more micro-nano structure arrays, and the one or more micro-nano structure arrays (112/113/114/115) in at least one of the one or more micro-nano structure units (112/113/114/115) comprise two-dimensional gratings formed of internal units of different shapes (see CUI, Figs.3-5 as shown above).
CUI is silent upon explicitly disclosing a random shape configuration of micro-nano structure units, wherein a micro-nano structure array in at least one of the one or more micro-nano structure units is two-dimensional grating formed of internal units of random shapes, and the internal units of random shapes comprise two or more curvatures.
However, CUI teaches wherein a micro-nano structure array (112/113/114/115) in at least one of the one or more micro-nano structure units (112/113/114/115) is two-dimensional grating formed of internal units of random shapes (a circle, a cross, a regular polygon, a square and so on), and the internal units of random shapes (a circle, a cross, a regular polygon, a square and so on) (see CUI, Figs.3-5 as shown above and page.5).
Hence, the configuration of the claimed micro-nano structure units was a matter of choice which a person of ordinary skill in the art would have found obvious absent persuasive evidence that the particular configuration of the claimed random shape configuration was significant. For support see, ROH et al. (Figs.13A-13H, Figs.4A-4B, ¶ [0004], ¶ [0050], and ¶ [0166]), (U.S. 2021/0126035 A1, hereinafter refer to ROH) teaches random shape configuration of micro-nano structure units as alternative configuration to regular shape configuration of micro-nano structure units.
Regarding Claim 25: CUI as modified teaches micro spectrum chip based on units of different shapes as set forth in claim 24 as above. CUI further teaches wherein each of the one or more micro-nano structure arrays (112/113/114/115) is a two-dimensional grating formed of internal units of different shapes (see CUI, Figs.3-5 as shown above).
Regarding Claim 26: CUI as modified teaches micro spectrum chip based on units of different shapes as set forth in claim 24 as above. CUI further teaches wherein the one or more micro-nano structure units (112/113/114/115) are identical repeating units, and at least one of the following is satisfied:
micro-nano structure arrays (112/113/114/115) located at corresponding positions in different micro-nano structure units (112/113/114/115) are identical (see CUI, Figs.3-5 as shown above),
no micro-nano structure array (112/113/114/115) exists at one or more corresponding positions in different micro-nano structure units (112/113/114/115) (see CUI, Figs.3-5 as shown above);
each of the one or more micro-nano structure units has a size of 0.5 µm2 to 40000 µm2 (see CUI, Figs.3-5 as shown above and Fig.8); or
each of the one or more micro-nano structure arrays has a period of 20 nm to 50 µm (see CUI, Figs.3-5 as shown above and Fig.8).
Regarding Claim 27: CUI as modified teaches micro spectrum chip based on units of different shapes as set forth in claim 24 as above. CUI further teaches wherein at least one of the following is satisfied: a number of micro-nano structure arrays (112/113/114/115) in each of the one or more micro-nano structure units is dynamically adjustable (see CUI, Figs.3-5 as shown above);
the one or more micro-nano structure units have C4 symmetry (see CUI, Figs.3-5 as shown above).
Regarding Claim 28: CUI as modified teaches micro spectrum chip based on units of different shapes as set forth in claim 24 as above. CUI further teaches wherein each of the one or more micro-nano structure arrays (112/113/114/115) corresponds to one or more pixels on the CIS wafer (120) (see CUI, Figs.3-5 as shown above).
Regarding Claim 29: CUI as modified teaches micro spectrum chip based on units of different shapes as set forth in claim 24 as above. CUI further teaches wherein a signal processing circuit (130) connected to the CIS wafer (120) through an electrical contact (see CUI, Figs.3-5 as shown above).
Regarding Claim 30: CUI as modified teaches micro spectrum chip based on units of different shapes as set forth in claim 24 as above. CUI further teaches wherein the CIS wafer (120) comprises an optical detection layer (122) and a metal wire layer (121), wherein the optical detection layer (122) is provided under the metal wire layer (121), and the optical modulation layer (110) is integrated on the metal wire layer (121); or the optical detection layer (122) is provided above the metal wire layer (121), and the optical modulation layer (110) is integrated on the optical detection layer (122) (see CUI, Figs.3-5 as shown above, Figs.6-7, and Fig.12).
Regarding Claim 31: CUI as modified teaches micro spectrum chip based on units of different shapes as set forth in claim 30 as above. CUI further teaches wherein when the optical detection layer (122) is provided above the metal wire layer (121), the optical modulation layer (110) is prepared by etching the optical detection layer (122) of the CIS wafer (120) with an etching depth of 50 nm to 2 µm (60nm to 1200nm) (see CUI, Figs.3-5 as shown above and Fig.12).
Regarding Claim 32: CUI as modified teaches micro spectrum chip based on units of different shapes as set forth in claim 24 as above. CUI further teaches wherein the optical modulation layer (110) is a single-layer structure, a double-layer structure, or a multi-layer structure (see CUI, Figs.3-5 as shown above and Figs.8-10),
a thickness of each of the single-layer structure, the double-layer structure, or the multi-layer structure is 50 nm to 2 µm (60nm to 1200nm) (see CUI, Figs.3-5 as shown above, Figs.8-10, and page.9), and at least one of the following is satisfied:
the optical modulation layer (110) is made of one or more of the following items: silicon, germanium, silicon-germanium material, silicon compound, germanium compound, metal, or III-V group material (see CUI, Figs.3-5 as shown above, Figs.8-10, and page.9), and
wherein the silicon compound comprises one or more of silicon nitride, silicon dioxide, or silicon carbide (see CUI, Figs.3-5 as shown above, Figs.8-10, and page.9); or
when the optical modulation layer (110) is double-layer structure or multi-layer structure, one or more layers of the double-layer structure or the multi-layer structure is not penetrated through (see CUI, Figs.3-5 as shown above, Figs.8-10, and page.9).
Regarding Claim 33: CUI as modified teaches micro spectrum chip based on units of different shapes as set forth in claim 24 as above. CUI further teaches wherein a light-transmitting medium layer (160) is provided between the optical modulation layer (110) and the CIS wafer (120), the light-transmitting medium layer (160) has a thickness of 50 nm to 2 µm (50nm to 1 μm), and comprises silicon dioxide; the light-transmitting medium layer (160) is prepared on the CIS wafer (120) by chemical vapor deposition, sputtering or spin coating, and the optical modulation layer (110) is deposited and etched on the light-transmitting medium layer (160) (see CUI, Figs.3-5 as shown above, Fig.13, and page.13); or
the optical modulation layer (110) is prepared on the light-transmitting medium layer (160), and the light-transmitting medium layer (160) and the optical modulation layer (110) are transferred to the CIS wafer (120) (see CUI, Figs.3-5 as shown above, Fig.13, and page.13).
Regarding Claim 34: CUI as modified teaches micro spectrum chip based on units of different shapes as set forth in claim 24 as above. CUI further teaches wherein at least one of a micro-lens or an optical filter (140), and at least one of the micro-lens (140) or the light filter are provided above or below the optical modulation layer (110) (see CUI, Figs.3-5 as shown above and Figs.14-15).
Regarding Claim 36: CUI discloses a method for generating micro-nano structure array in a spectrum chip (see CUI, Figs.3-5 as shown above and abstract), wherein the spectrum chip comprises
a wafer-level image sensor (120), and an upper surface of a photosensitive area of the wafer-level image sensor (120) is provided with an optical modulation layer (110) (see CUI, Figs.3-5 as shown above);
the optical modulation layer (110) comprises a unit array formed of a plurality of micro-nano units (112/113/114/115), and each of the micro-nano units (112/113/114/115) corresponds to one or more pixel points on the wafer-level image sensor (120) (see CUI, Figs.3-5 as shown above); and
each of the micro-nano units (112/114/115/113) comprises multiple groups of micro-nano structure arrays, each group of the micro-nano structure arrays is formed in a two-dimensional grating structure, and the two-dimensional grating structure in the multiple groups of micro-nano structure arrays of each of the micro-nano units (112/113114/115) is used for modulating an incident light and encoding spectral information of the incident light to different pixel points of the wafer-level image sensor (120) to obtain an image including the spectral information of the incident light (see CUI, Figs.3-5 as shown above);
wherein the method comprises: generating the two-dimensional grating structure, the two-dimensional grating structure being formed by periodically arranging random-shaped structures (note: the micro-nano structure arrays is formed in a two-dimensional grating structure) (see CUI, Figs.3-5 as shown above and page.7); and
the generating the two-dimensional grating structure comprises:
determining an arrangement period of the random-shaped structures (a circle, a cross, a regular polygon, a square and so on) in the two-dimensional grating structure (see CUI, Figs.3-5 as shown above and page.5);
generating each of the random-shaped structures (a circle, a cross, a regular polygon, a square and so on) in the two-dimensional grating structure by the following steps (see CUI, Figs.3-5 as shown above and page.5):
meshing an area within the arrangement period to obtain a plurality of mesh areas (see CUI, Figs.3-5 as shown above);
assigning pixel values to the plurality of mesh areas randomly to obtain an initial pattern corresponding to the random-shaped structure (a circle, a cross, a regular polygon, a square and so on), wherein mesh areas corresponding to different pixel values have different refractive indexes (see CUI, Figs.3-5 as shown above); and
binarizing the initial pattern to obtain a first binarized pattern, wherein the first binarized pattern corresponds to one of the random-shaped structures (a circle, a cross, a regular polygon, a square and so on), 0 and 1 in the first binarized pattern represent air (hole/116) and a medium, respectively (see CUI, Figs.3-5 as shown above and Figs.8-11).
Note: forming the micro-nano units necessarily requires the processing steps of meshing and binarizing the initial pattern in order to obtain the CUI micro-nano units.
CUI is silent upon explicitly disclosing a random shape configuration of micro-nano units.
However, CUI teaches wherein a micro-nano units (112/113/114/115) comprises a circle, a cross, a regular polygon, a square and so on, configuration (see CUI, Figs.3-5 as shown above and page.5).
Hence, the configuration of the claimed micro-nano units was a matter of choice which a person of ordinary skill in the art would have found obvious absent persuasive evidence that the particular configuration of the claimed random-shaped configuration was significant. For support see, ROH et al. (Figs.13A-13H, Figs.4A-4B, ¶ [0004], ¶ [0050], and ¶ [0166]), (U.S. 2021/0126035 A1, hereinafter refer to ROH) teaches random-shaped configuration of micro-nano units as alternative configuration to regular-shaped configuration of micro-nano units.
Regarding Claim 37: CUI as modified teaches a method for generating micro-nano structure array in a spectrum chip as set forth in claim 36 as above. CUI further teaches wherein before being binarized, the initial pattern is filtered and smoothed (see CUI, Figs.3-5 as shown above and Figs.8-11).
Note: forming the micro-nano units necessarily requires the processing steps of meshing and binarizing the initial pattern in order to obtain the CUI micro-nano units.
Regarding Claim 38: CUI as modified teaches a method for generating micro-nano structure array in a spectrum chip as set forth in claim 37 as above. CUI further teaches after obtaining the first binarized pattern (see CUI, Figs.3-5 as shown above and Figs.8-11), further comprising:
fuzzifying and binarizing the first binarized pattern sequentially to obtain a second binarized pattern, wherein the second binarized pattern corresponds to one random-shaped structure (a circle, a cross, a regular polygon, a square and so on) (see CUI, Figs.3-5 as shown above and Figs.8-11).
Note: the configuration of the claimed micro-nano units was a matter of choice which a person of ordinary skill in the art would have found obvious absent persuasive evidence that the particular configuration of the claimed random-shaped configuration was significant. For support see, ROH et al. (Figs.13A-13H, Figs.4A-4B, ¶ [0004], ¶ [0050], and ¶ [0166]), (U.S. 2021/0126035 A1, hereinafter refer to ROH) teaches random-shaped configuration of micro-nano units as alternative configuration to regular-shaped configuration of micro-nano units.
Regarding Claim 39: CUI as modified teaches a method for generating micro-nano structure array in a spectrum chip as set forth in claim 37 as above. CUI further teaches wherein the assigning pixel values to the plurality of mesh areas randomly to obtain the initial pattern corresponding to the random- shaped structure (a circle, a cross, a regular polygon, a square and so on) (see CUI, Figs.3-5 as shown above and Figs.8-11) comprises:
grouping the plurality of mesh areas to obtain multiple groups of meshes, wherein each group of meshes comprises one or more mesh areas (see CUI, Figs.3-5 as shown above and Figs.8-11); and
assigning the pixel values to each group of meshes randomly according to a standard normal distribution to obtain the initial pattern corresponding to the random-shaped structure (a circle, a cross, a regular polygon, a square and so on), wherein the mesh areas in one group have the same pixel value (see CUI, Figs.3-5 as shown above and Figs.8-11).
Note: the configuration of the claimed micro-nano units was a matter of choice which a person of ordinary skill in the art would have found obvious absent persuasive evidence that the particular configuration of the claimed random-shaped configuration was significant. For support see, ROH et al. (Figs.13A-13H, Figs.4A-4B, ¶ [0004], ¶ [0050], and ¶ [0166]), (U.S. 2021/0126035 A1, hereinafter refer to ROH) teaches random-shaped configuration of micro-nano units as alternative configuration to regular-shaped configuration of micro-nano units.
Regarding Claim 40: CUI as modified teaches a method for generating micro-nano structure array in a spectrum chip as set forth in claim 36 as above. CUI further teaches wherein after obtaining the first binarized pattern (see CUI, Figs.3-5 as shown above and Figs.8-11), further comprising:
performing symmetry processing on the first binarized pattern to obtain a pattern with symmetry, wherein the pattern with symmetry corresponds to one of the random-shaped structures (a circle, a cross, a regular polygon, a square and so on) (see CUI, Figs.3-5 as shown above and Figs.8-11);
wherein the symmetry processing comprises one or more of the following items: two-fold rotational symmetry processing, Y-axis mirror symmetry processing, X-axis mirror symmetry processing, both Y-axis and X-axis mirror symmetry processing, four-fold rotational symmetry processing, or both Y-axis and X-axis mirror symmetry and four-fold rotational symmetry processing (see CUI, Figs.3-5 as shown above and Figs.8-11); and
the pattern with symmetry comprises one or more of the following items (see CUI, Figs.3-5 as shown above and Figs.8-11):
a pattern with two-fold rotational symmetry, a pattern with Y-axis mirror symmetry, a pattern with X-axis mirror symmetry, a pattern with both Y-axis and X-axis mirror symmetry, a pattern with four-fold rotational symmetry, or a pattern with both Y-axis and X-axis mirror symmetry and four-fold rotational symmetry (see CUI, Figs.3-5 as shown above and Figs.8-11).
Note: forming the micro-nano units necessarily requires the processing steps of meshing and binarizing the initial pattern in order to obtain the CUI micro-nano units.
Note: the configuration of the claimed micro-nano units was a matter of choice which a person of ordinary skill in the art would have found obvious absent persuasive evidence that the particular configuration of the claimed random-shaped configuration was significant. For support see, ROH et al. (Figs.13A-13H, Figs.4A-4B, ¶ [0004], ¶ [0050], and ¶ [0166]), (U.S. 2021/0126035 A1, hereinafter refer to ROH) teaches random-shaped configuration of micro-nano units as alternative configuration to regular-shaped configuration of micro-nano units.
Regarding Claim 41: CUI as modified teaches a method for generating micro-nano structure array in a spectrum chip as set forth in claim 36 as above. CUI further teaches wherein after obtaining the first binarized pattern, further comprising: dilating or eroding the first binarized pattern to simulate insufficient or excessive etching in the process preparation (see CUI, Figs.3-5 as shown above and Figs.8-11).
Note: forming the micro-nano units necessarily requires the processing steps of meshing and binarizing the initial pattern in order to obtain the CUI micro-nano units.
Regarding Claim 42: CUI as modified teaches a method for generating micro-nano structure array in a spectrum chip as set forth in claim 37 as above. CUI further teaches wherein the spectrum chip further comprises: a signal processing circuit (121) connected with the wafer-level image sensor (120) (see CUI, Figs.3-5 as shown above, Figs.6-7, and Fig.12);
wherein the signal processing circuit (121) is used for processing the image including spectral information of the incident light to obtain the spectral information of the incident light (see CUI, Figs.3-5 as shown above, Figs.6-7, and Fig.12);
wherein a light-transmitting medium layer (160) is provided between the optical modulation layer (110) and the wafer-level image sensor (120) (see CUI, Figs.3-5 as shown above and Fig.13); and
wherein the wafer-level image sensor (120) is front-side illuminated and comprises a metal wire layer (121) and an optical detection layer (122) arranged from up to down, wherein the optical modulation layer (110) is integrated on a side of the metal wire layer (121) distal to the optical detection layer (122) (see CUI, Figs.3-5 as shown above, Figs.6-7, and Fig.12); or
the wafer-level image sensor (120) is back-side illuminated and comprises an optical detection layer (122) and a metal wire layer (121) arranged from up to down, wherein the optical modulation layer (110) is integrated on a side of the optical detection layer (122) distal to the metal wire layer (121) (see CUI, Figs.3-5 as shown above, Figs.6-7, and Fig.12).
Regarding Claim 43: CUI as modified teaches a method for generating micro-nano structure array in a spectrum chip as set forth in claim 37 as above. CUI further teaches wherein the spectrum chip further comprises: at least one of a micro-lens or an optical filter (140) (see CUI, Figs.3-5 as shown above and Figs.15-16);
the micro-lens (140) is arranged on a side of the optical modulation layer (110) distal to the wafer-level image sensor (120), or the micro-lens (140) is arranged on a side of the optical modulation layer (110) proximal to the wafer-level image sensor (120) (see CUI, Figs.3-5 as shown above and Figs.15-16); and
the light filter (140) is arranged on the side of the optical modulation layer (140) distal to the wafer-level image sensor (120), or the light filter (140) is arranged on the side of the optical modulation layer (110) proximal to the wafer-level image sensor (120) (see CUI, Figs.3-5 as shown above and Figs.15-16).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BITEW A DINKE whose telephone number is (571)272-0534. The examiner can normally be reached M-F 7 a.m. - 5 p.m..
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached at (571)272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/BITEW A DINKE/Primary Examiner, Art Unit 2812
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